d494eb0fa3
When assigning numbers to registers, skip any with neither uses nor defs. This is will not have any impact at all on the final SASS but it makes for slightly more readable PTX. This change should also ensure that future minor changes are less likely to cause noisy diffs in register numbering.
91 lines
3.5 KiB
LLVM
91 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_30 -verify-machineinstrs | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
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; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_30 -verify-machineinstrs | %ptxas-verify %}
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target triple = "nvptx-unknown-cuda"
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declare { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64, i32)
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declare i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1))
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define ptx_kernel void @foo(i64 %img, ptr %red, i32 %idx) {
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; CHECK-LABEL: foo(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<6>;
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; CHECK-NEXT: .reg .b64 %rd<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [foo_param_0];
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; CHECK-NEXT: ld.param.b64 %rd2, [foo_param_1];
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; CHECK-NEXT: cvta.to.global.u64 %rd3, %rd2;
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; CHECK-NEXT: ld.param.b32 %r1, [foo_param_2];
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; CHECK-NEXT: tex.1d.v4.f32.s32 {%r2, %r3, %r4, %r5}, [%rd1, {%r1}];
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; CHECK-NEXT: st.global.b32 [%rd3], %r2;
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; CHECK-NEXT: ret;
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%val = tail call { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64 %img, i32 %idx)
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%ret = extractvalue { float, float, float, float } %val, 0
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store float %ret, ptr %red
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ret void
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}
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@tex0 = internal addrspace(1) global i64 0, align 8
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define ptx_kernel void @bar(ptr %red, i32 %idx) {
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; CHECK-LABEL: bar(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<6>;
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; CHECK-NEXT: .reg .b64 %rd<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [bar_param_0];
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; CHECK-NEXT: cvta.to.global.u64 %rd2, %rd1;
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; CHECK-NEXT: ld.param.b32 %r1, [bar_param_1];
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; CHECK-NEXT: tex.1d.v4.f32.s32 {%r2, %r3, %r4, %r5}, [tex0, {%r1}];
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; CHECK-NEXT: st.global.b32 [%rd2], %r2;
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; CHECK-NEXT: ret;
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%texHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1) @tex0)
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%val = tail call { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64 %texHandle, i32 %idx)
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%ret = extractvalue { float, float, float, float } %val, 0
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store float %ret, ptr %red
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ret void
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}
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declare float @texfunc(i64)
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define ptx_kernel void @baz(ptr %red, i32 %idx) {
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; CHECK-LABEL: baz(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<8>;
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; CHECK-NEXT: .reg .b64 %rd<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [baz_param_0];
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; CHECK-NEXT: cvta.to.global.u64 %rd2, %rd1;
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; CHECK-NEXT: ld.param.b32 %r1, [baz_param_1];
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; CHECK-NEXT: mov.u64 %rd3, tex0;
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; CHECK-NEXT: tex.1d.v4.f32.s32 {%r2, %r3, %r4, %r5}, [tex0, {%r1}];
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; CHECK-NEXT: { // callseq 0, 0
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; CHECK-NEXT: .param .b64 param0;
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; CHECK-NEXT: .param .b32 retval0;
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; CHECK-NEXT: st.param.b64 [param0], %rd3;
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; CHECK-NEXT: call.uni (retval0), texfunc, (param0);
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; CHECK-NEXT: ld.param.b32 %r6, [retval0];
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; CHECK-NEXT: } // callseq 0
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; CHECK-NEXT: add.rn.f32 %r7, %r2, %r6;
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; CHECK-NEXT: st.global.b32 [%rd2], %r7;
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; CHECK-NEXT: ret;
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%texHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1) @tex0)
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%val = tail call { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64 %texHandle, i32 %idx)
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%ret = extractvalue { float, float, float, float } %val, 0
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%texcall = tail call float @texfunc(i64 %texHandle)
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%ret2 = fadd float %ret, %texcall
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store float %ret2, ptr %red
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ret void
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}
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!nvvm.annotations = !{!1}
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!1 = !{ptr addrspace(1) @tex0, !"texture", i32 1}
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