369891b674
In most cases, the type information attached to load and store instructions is meaningless and inconsistently applied. We can usually use ".b" loads and avoid the complexity of trying to assign the correct type. The one expectation is sign-extending load, which will continue to use ".s" to ensure the sign extension into a larger register is done correctly.
31 lines
1.1 KiB
LLVM
31 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 | FileCheck %s
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; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -mtriple=nvptx -mcpu=sm_20 | %ptxas-verify -m32 %}
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; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
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; This test makes sure that the result of vector compares are properly
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; scalarized. If codegen fails, then the type legalizer incorrectly
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; tried to promote <2 x i1> to <2 x i8> and instruction selection failed.
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; CHECK-LABEL: .visible .func foo(
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define void @foo(ptr %a, ptr %b, ptr %r1, ptr %r2) {
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; CHECK: ld.v2.b32
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%aval = load <2 x i32>, ptr %a
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; CHECK: ld.v2.b32
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%bval = load <2 x i32>, ptr %b
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; CHECK: setp.lt.s32
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; CHECK: setp.lt.s32
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%res = icmp slt <2 x i32> %aval, %bval
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%t1 = extractelement <2 x i1> %res, i32 0
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%t2 = extractelement <2 x i1> %res, i32 1
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; CHECK: selp.b32 %r{{[0-9]+}}, 1, 0
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; CHECK: selp.b32 %r{{[0-9]+}}, 1, 0
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%t1a = zext i1 %t1 to i32
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%t2a = zext i1 %t2 to i32
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; CHECK: st.b32
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; CHECK: st.b32
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store i32 %t1a, ptr %r1
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store i32 %t2a, ptr %r2
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ret void
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}
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