3d2650bdeb
The logic in RISCVMatInt would previously produce lui+addiw on RV64 whenever a 32-bit integer must be materialised and the Hi20 and Lo12 parts are non-zero. However, sometimes addi can be used equivalently (whenever the sign extension behaviour of addiw would be a no-op). This patch moves to using addiw only when necessary. Although there is absolutely no advantage in terms of compressibility or performance, this has the following advantages: * It's more consistent with logic used elsewhere in the backend. For instance, RISCVOptWInstrs will try to convert addiw to addi on the basis it reduces test diffs vs RV32. * This matches the lowering GCC does in its codegen path. Unlike LLVM, GCC seems to have different expansion logic for the assembler vs codegen. For codegen it will use lui+addi if possible, but expanding `li` in the assembler will always produces lui+addiw as LLVM did prior to this commit. As someone who has been looking at a lot of gcc vs clang diffs lately, reducing unnecessary divergence is of at least some value. * As the diff for fold-mem-offset.ll shows, we can fold memory offsets in more cases when addi is used. Memory offset folding could be taught to recognise when the addiw could be replaced with an addi, but that seems unnecessary when we can simply change the logic in RISCVMatInt. As pointed out by @topperc during review, making this change without modifying RISCVOptWInstrs risks introducing some cases where we fail to remove a sext.w that we removed before. I've incorporated a patch based on a suggestion from Craig that avoids it, and also adds appropriate RISCVOptWInstrs test cases. The initial patch description noted that the main motivation was to avoid unnecessary differences both for RV32/RV64 and when comparing GCC, but noted that very occasionally we see a benefit from memory offset folding kicking in when it didn't before. Looking at the dynamic instruction count difference for SPEC benchmarks targeting rva22u64 and it shows we actually get a meaningful ~4.3% reduction in dynamic icount for 519.lbm_r. Looking at the data more closely, the codegen difference is in `LBM_performStreamCollideTRT` which as a function accounts for ~98% for dynamically executed instructions and the codegen diffs appear to be a knock-on effect of the address merging reducing register pressure right from function entry (for instance, we get a big reduction in dynamically executed loads in that function). Below is the icount data (rva22u64 -O3, no LTO): ``` Benchmark Baseline This PR Diff (%) ============================================================ 500.perlbench_r 174116601991 174115795810 -0.00% 502.gcc_r 218903280858 218903215788 -0.00% 505.mcf_r 131208029185 131207692803 -0.00% 508.namd_r 217497594322 217497594297 -0.00% 510.parest_r 289314486153 289313577652 -0.00% 511.povray_r 30640531048 30640765701 0.00% 519.lbm_r 95897914862 91712688050 -4.36% 520.omnetpp_r 134641549722 134867015683 0.17% 523.xalancbmk_r 281462762992 281432092673 -0.01% 525.x264_r 379776121941 379535558210 -0.06% 526.blender_r 659736022025 659738387343 0.00% 531.deepsjeng_r 349122867552 349122867481 -0.00% 538.imagick_r 238558760552 238558753269 -0.00% 541.leela_r 406578560612 406385135260 -0.05% 544.nab_r 400997131674 400996765827 -0.00% 557.xz_r 130079522194 129945515709 -0.10% ``` The instcounting setup I use doesn't have good support for drilling down into functions from outside the linked executable (e.g. libc). The difference in omnetpp all seems to come from there, and does not reflect any degradation in codegen quality. I can confirm with the current version of the PR there is no change in the number of static sext.w across all the SPEC 2017 benchmarks (rva22u64 O3) Co-authored-by: Craig Topper <craig.topper@sifive.com>
4764 lines
132 KiB
LLVM
4764 lines
132 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \
|
|
; RUN: | FileCheck %s -check-prefix=RV32I
|
|
; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -mattr=+experimental-xqcili \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IXQCILI
|
|
; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \
|
|
; RUN: | FileCheck %s -check-prefixes=RV64I,RV64-NOPOOL
|
|
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
|
|
; RUN: | FileCheck %s -check-prefixes=RV64I,RV64I-POOL
|
|
; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zba \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBA
|
|
; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zbb \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBB
|
|
; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zbs \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBS
|
|
; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+xtheadbb \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IXTHEADBB
|
|
|
|
; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \
|
|
; RUN: -riscv-use-rematerializable-movimm | FileCheck %s -check-prefix=RV32-REMAT
|
|
; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \
|
|
; RUN: -riscv-use-rematerializable-movimm | FileCheck %s -check-prefix=RV64-REMAT
|
|
|
|
; Materializing constants
|
|
|
|
; TODO: It would be preferable if anyext constant returns were sign rather
|
|
; than zero extended. See PR39092. For now, mark returns as explicitly signext
|
|
; (this matches what Clang would generate for equivalent C/C++ anyway).
|
|
|
|
define signext i32 @zero() nounwind {
|
|
; RV32I-LABEL: zero:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a0, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: zero:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a0, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: zero:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, 0
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: zero:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, 0
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: zero:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, 0
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: zero:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, 0
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: zero:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, 0
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: zero:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a0, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: zero:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, 0
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 0
|
|
}
|
|
|
|
define signext i32 @pos_small() nounwind {
|
|
; RV32I-LABEL: pos_small:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a0, 2047
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: pos_small:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a0, 2047
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: pos_small:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, 2047
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: pos_small:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, 2047
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: pos_small:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, 2047
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: pos_small:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, 2047
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: pos_small:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, 2047
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: pos_small:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a0, 2047
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: pos_small:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, 2047
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 2047
|
|
}
|
|
|
|
define signext i32 @neg_small() nounwind {
|
|
; RV32I-LABEL: neg_small:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a0, -2048
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: neg_small:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a0, -2048
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: neg_small:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, -2048
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: neg_small:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, -2048
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: neg_small:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, -2048
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: neg_small:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, -2048
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: neg_small:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, -2048
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: neg_small:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a0, -2048
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: neg_small:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, -2048
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 -2048
|
|
}
|
|
|
|
define signext i32 @pos_i32() nounwind {
|
|
; RV32I-LABEL: pos_i32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 423811
|
|
; RV32I-NEXT: addi a0, a0, -1297
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: pos_i32:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 1735928559
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: pos_i32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 423811
|
|
; RV64I-NEXT: addi a0, a0, -1297
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: pos_i32:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 423811
|
|
; RV64IZBA-NEXT: addi a0, a0, -1297
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: pos_i32:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 423811
|
|
; RV64IZBB-NEXT: addi a0, a0, -1297
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: pos_i32:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 423811
|
|
; RV64IZBS-NEXT: addi a0, a0, -1297
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: pos_i32:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 423811
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1297
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: pos_i32:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 423811
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1297
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: pos_i32:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 423811
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1297
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 1735928559
|
|
}
|
|
|
|
define signext i32 @neg_i32() nounwind {
|
|
; RV32I-LABEL: neg_i32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 912092
|
|
; RV32I-NEXT: addi a0, a0, -273
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: neg_i32:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -559038737
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: neg_i32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 912092
|
|
; RV64I-NEXT: addi a0, a0, -273
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: neg_i32:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 912092
|
|
; RV64IZBA-NEXT: addi a0, a0, -273
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: neg_i32:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 912092
|
|
; RV64IZBB-NEXT: addi a0, a0, -273
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: neg_i32:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 912092
|
|
; RV64IZBS-NEXT: addi a0, a0, -273
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: neg_i32:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 912092
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -273
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: neg_i32:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 912092
|
|
; RV32-REMAT-NEXT: addi a0, a0, -273
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: neg_i32:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 912092
|
|
; RV64-REMAT-NEXT: addi a0, a0, -273
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 -559038737
|
|
}
|
|
|
|
define signext i32 @pos_i32_hi20_only() nounwind {
|
|
; RV32I-LABEL: pos_i32_hi20_only:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: pos_i32_hi20_only:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: lui a0, 16
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: pos_i32_hi20_only:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: pos_i32_hi20_only:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 16
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: pos_i32_hi20_only:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 16
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: pos_i32_hi20_only:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 16
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: pos_i32_hi20_only:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 16
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: pos_i32_hi20_only:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 16
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: pos_i32_hi20_only:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 16
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 65536 ; 0x10000
|
|
}
|
|
|
|
define signext i32 @neg_i32_hi20_only() nounwind {
|
|
; RV32I-LABEL: neg_i32_hi20_only:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 1048560
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: neg_i32_hi20_only:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: lui a0, 1048560
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: neg_i32_hi20_only:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 1048560
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: neg_i32_hi20_only:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 1048560
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: neg_i32_hi20_only:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 1048560
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: neg_i32_hi20_only:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 1048560
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: neg_i32_hi20_only:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 1048560
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: neg_i32_hi20_only:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 1048560
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: neg_i32_hi20_only:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 1048560
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 -65536 ; -0x10000
|
|
}
|
|
|
|
; This can be materialized with ADDI+SLLI, improving compressibility.
|
|
|
|
define signext i32 @imm_left_shifted_addi() nounwind {
|
|
; RV32I-LABEL: imm_left_shifted_addi:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 32
|
|
; RV32I-NEXT: addi a0, a0, -64
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_left_shifted_addi:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.li a0, 131008
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_left_shifted_addi:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 32
|
|
; RV64I-NEXT: addi a0, a0, -64
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_left_shifted_addi:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 32
|
|
; RV64IZBA-NEXT: addi a0, a0, -64
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_left_shifted_addi:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 32
|
|
; RV64IZBB-NEXT: addi a0, a0, -64
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_left_shifted_addi:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 32
|
|
; RV64IZBS-NEXT: addi a0, a0, -64
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_left_shifted_addi:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 32
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -64
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_left_shifted_addi:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 32
|
|
; RV32-REMAT-NEXT: addi a0, a0, -64
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_left_shifted_addi:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 32
|
|
; RV64-REMAT-NEXT: addi a0, a0, -64
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 131008 ; 0x1FFC0
|
|
}
|
|
|
|
; This can be materialized with ADDI+SRLI, improving compressibility.
|
|
|
|
define signext i32 @imm_right_shifted_addi() nounwind {
|
|
; RV32I-LABEL: imm_right_shifted_addi:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 524288
|
|
; RV32I-NEXT: addi a0, a0, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_right_shifted_addi:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 2147483647
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_right_shifted_addi:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 524288
|
|
; RV64I-NEXT: addiw a0, a0, -1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_right_shifted_addi:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 524288
|
|
; RV64IZBA-NEXT: addiw a0, a0, -1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_right_shifted_addi:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 524288
|
|
; RV64IZBB-NEXT: addiw a0, a0, -1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_right_shifted_addi:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 524288
|
|
; RV64IZBS-NEXT: addiw a0, a0, -1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_right_shifted_addi:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 524288
|
|
; RV64IXTHEADBB-NEXT: addiw a0, a0, -1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_right_shifted_addi:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 524288
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_right_shifted_addi:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 524288
|
|
; RV64-REMAT-NEXT: addiw a0, a0, -1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 2147483647 ; 0x7FFFFFFF
|
|
}
|
|
|
|
; This can be materialized with LUI+SRLI, improving compressibility.
|
|
|
|
define signext i32 @imm_right_shifted_lui() nounwind {
|
|
; RV32I-LABEL: imm_right_shifted_lui:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 56
|
|
; RV32I-NEXT: addi a0, a0, 580
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_right_shifted_lui:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.li a0, 229956
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_right_shifted_lui:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 56
|
|
; RV64I-NEXT: addi a0, a0, 580
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_right_shifted_lui:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 56
|
|
; RV64IZBA-NEXT: addi a0, a0, 580
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_right_shifted_lui:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 56
|
|
; RV64IZBB-NEXT: addi a0, a0, 580
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_right_shifted_lui:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 56
|
|
; RV64IZBS-NEXT: addi a0, a0, 580
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_right_shifted_lui:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 56
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 580
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_right_shifted_lui:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 56
|
|
; RV32-REMAT-NEXT: addi a0, a0, 580
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_right_shifted_lui:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 56
|
|
; RV64-REMAT-NEXT: addi a0, a0, 580
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 229956 ; 0x38244
|
|
}
|
|
|
|
define i64 @imm64_1() nounwind {
|
|
; RV32I-LABEL: imm64_1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 524288
|
|
; RV32I-NEXT: li a1, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_1:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: lui a0, 524288
|
|
; RV32IXQCILI-NEXT: li a1, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, 1
|
|
; RV64I-NEXT: slli a0, a0, 31
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_1:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, 1
|
|
; RV64IZBA-NEXT: slli a0, a0, 31
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_1:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, 1
|
|
; RV64IZBB-NEXT: slli a0, a0, 31
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_1:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: bseti a0, zero, 31
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_1:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, 1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 31
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_1:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 524288
|
|
; RV32-REMAT-NEXT: li a1, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_1:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, 1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 31
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 2147483648 ; 0x8000_0000
|
|
}
|
|
|
|
define i64 @imm64_2() nounwind {
|
|
; RV32I-LABEL: imm64_2:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a0, -1
|
|
; RV32I-NEXT: li a1, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_2:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a0, -1
|
|
; RV32IXQCILI-NEXT: li a1, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_2:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, -1
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_2:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, -1
|
|
; RV64IZBA-NEXT: srli a0, a0, 32
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_2:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, -1
|
|
; RV64IZBB-NEXT: srli a0, a0, 32
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_2:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, -1
|
|
; RV64IZBS-NEXT: srli a0, a0, 32
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_2:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, -1
|
|
; RV64IXTHEADBB-NEXT: srli a0, a0, 32
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_2:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a0, -1
|
|
; RV32-REMAT-NEXT: li a1, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_2:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, -1
|
|
; RV64-REMAT-NEXT: srli a0, a0, 32
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 4294967295 ; 0xFFFF_FFFF
|
|
}
|
|
|
|
define i64 @imm64_3() nounwind {
|
|
; RV32I-LABEL: imm64_3:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a1, 1
|
|
; RV32I-NEXT: li a0, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_3:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a1, 1
|
|
; RV32IXQCILI-NEXT: li a0, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_3:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, 1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_3:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, 1
|
|
; RV64IZBA-NEXT: slli a0, a0, 32
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_3:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, 1
|
|
; RV64IZBB-NEXT: slli a0, a0, 32
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_3:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: bseti a0, zero, 32
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_3:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, 1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 32
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_3:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a1, 1
|
|
; RV32-REMAT-NEXT: li a0, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_3:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, 1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 32
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 4294967296 ; 0x1_0000_0000
|
|
}
|
|
|
|
define i64 @imm64_4() nounwind {
|
|
; RV32I-LABEL: imm64_4:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a1, 524288
|
|
; RV32I-NEXT: li a0, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_4:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: lui a1, 524288
|
|
; RV32IXQCILI-NEXT: li a0, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_4:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, -1
|
|
; RV64I-NEXT: slli a0, a0, 63
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_4:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, -1
|
|
; RV64IZBA-NEXT: slli a0, a0, 63
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_4:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, -1
|
|
; RV64IZBB-NEXT: slli a0, a0, 63
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_4:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: bseti a0, zero, 63
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_4:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, -1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 63
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_4:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a1, 524288
|
|
; RV32-REMAT-NEXT: li a0, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_4:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, -1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 63
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 9223372036854775808 ; 0x8000_0000_0000_0000
|
|
}
|
|
|
|
define i64 @imm64_5() nounwind {
|
|
; RV32I-LABEL: imm64_5:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a1, 524288
|
|
; RV32I-NEXT: li a0, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_5:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: lui a1, 524288
|
|
; RV32IXQCILI-NEXT: li a0, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_5:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, -1
|
|
; RV64I-NEXT: slli a0, a0, 63
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_5:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, -1
|
|
; RV64IZBA-NEXT: slli a0, a0, 63
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_5:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, -1
|
|
; RV64IZBB-NEXT: slli a0, a0, 63
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_5:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: bseti a0, zero, 63
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_5:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, -1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 63
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_5:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a1, 524288
|
|
; RV32-REMAT-NEXT: li a0, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_5:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, -1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 63
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -9223372036854775808 ; 0x8000_0000_0000_0000
|
|
}
|
|
|
|
define i64 @imm64_6() nounwind {
|
|
; RV32I-LABEL: imm64_6:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 74565
|
|
; RV32I-NEXT: addi a1, a0, 1656
|
|
; RV32I-NEXT: li a0, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_6:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a1, 305419896
|
|
; RV32IXQCILI-NEXT: li a0, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_6:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 9321
|
|
; RV64I-NEXT: addi a0, a0, -1329
|
|
; RV64I-NEXT: slli a0, a0, 35
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_6:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 9321
|
|
; RV64IZBA-NEXT: addi a0, a0, -1329
|
|
; RV64IZBA-NEXT: slli a0, a0, 35
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_6:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 9321
|
|
; RV64IZBB-NEXT: addi a0, a0, -1329
|
|
; RV64IZBB-NEXT: slli a0, a0, 35
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_6:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 9321
|
|
; RV64IZBS-NEXT: addi a0, a0, -1329
|
|
; RV64IZBS-NEXT: slli a0, a0, 35
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_6:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 9321
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1329
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 35
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_6:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a1, 74565
|
|
; RV32-REMAT-NEXT: addi a1, a1, 1656
|
|
; RV32-REMAT-NEXT: li a0, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_6:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 9321
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1329
|
|
; RV64-REMAT-NEXT: slli a0, a0, 35
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 1311768464867721216 ; 0x1234_5678_0000_0000
|
|
}
|
|
|
|
define i64 @imm64_7() nounwind {
|
|
; RV32I-LABEL: imm64_7:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 45056
|
|
; RV32I-NEXT: addi a0, a0, 15
|
|
; RV32I-NEXT: lui a1, 458752
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_7:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 184549391
|
|
; RV32IXQCILI-NEXT: lui a1, 458752
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_7:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, 7
|
|
; RV64I-NEXT: slli a0, a0, 36
|
|
; RV64I-NEXT: addi a0, a0, 11
|
|
; RV64I-NEXT: slli a0, a0, 24
|
|
; RV64I-NEXT: addi a0, a0, 15
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_7:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, 7
|
|
; RV64IZBA-NEXT: slli a0, a0, 36
|
|
; RV64IZBA-NEXT: addi a0, a0, 11
|
|
; RV64IZBA-NEXT: slli a0, a0, 24
|
|
; RV64IZBA-NEXT: addi a0, a0, 15
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_7:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, 7
|
|
; RV64IZBB-NEXT: slli a0, a0, 36
|
|
; RV64IZBB-NEXT: addi a0, a0, 11
|
|
; RV64IZBB-NEXT: slli a0, a0, 24
|
|
; RV64IZBB-NEXT: addi a0, a0, 15
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_7:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, 7
|
|
; RV64IZBS-NEXT: slli a0, a0, 36
|
|
; RV64IZBS-NEXT: addi a0, a0, 11
|
|
; RV64IZBS-NEXT: slli a0, a0, 24
|
|
; RV64IZBS-NEXT: addi a0, a0, 15
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_7:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, 7
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 36
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 11
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 24
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 15
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_7:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 45056
|
|
; RV32-REMAT-NEXT: addi a0, a0, 15
|
|
; RV32-REMAT-NEXT: lui a1, 458752
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_7:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, 7
|
|
; RV64-REMAT-NEXT: slli a0, a0, 36
|
|
; RV64-REMAT-NEXT: addi a0, a0, 11
|
|
; RV64-REMAT-NEXT: slli a0, a0, 24
|
|
; RV64-REMAT-NEXT: addi a0, a0, 15
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 8070450532432478223 ; 0x7000_0000_0B00_000F
|
|
}
|
|
|
|
; TODO: it can be preferable to put constants that are expensive to materialise
|
|
; into the constant pool, especially for -Os.
|
|
define i64 @imm64_8() nounwind {
|
|
; RV32I-LABEL: imm64_8:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 633806
|
|
; RV32I-NEXT: lui a1, 74565
|
|
; RV32I-NEXT: addi a0, a0, -272
|
|
; RV32I-NEXT: addi a1, a1, 1656
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_8:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1698898192
|
|
; RV32IXQCILI-NEXT: qc.e.li a1, 305419896
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64-NOPOOL-LABEL: imm64_8:
|
|
; RV64-NOPOOL: # %bb.0:
|
|
; RV64-NOPOOL-NEXT: lui a0, 583
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, -1875
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 14
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, -947
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 12
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, 1511
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 13
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, -272
|
|
; RV64-NOPOOL-NEXT: ret
|
|
;
|
|
; RV64I-POOL-LABEL: imm64_8:
|
|
; RV64I-POOL: # %bb.0:
|
|
; RV64I-POOL-NEXT: lui a0, %hi(.LCPI17_0)
|
|
; RV64I-POOL-NEXT: ld a0, %lo(.LCPI17_0)(a0)
|
|
; RV64I-POOL-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_8:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 596523
|
|
; RV64IZBA-NEXT: addi a0, a0, 965
|
|
; RV64IZBA-NEXT: slli.uw a0, a0, 13
|
|
; RV64IZBA-NEXT: addi a0, a0, -1347
|
|
; RV64IZBA-NEXT: slli a0, a0, 12
|
|
; RV64IZBA-NEXT: addi a0, a0, -529
|
|
; RV64IZBA-NEXT: slli a0, a0, 4
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_8:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 583
|
|
; RV64IZBB-NEXT: addi a0, a0, -1875
|
|
; RV64IZBB-NEXT: slli a0, a0, 14
|
|
; RV64IZBB-NEXT: addi a0, a0, -947
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, 1511
|
|
; RV64IZBB-NEXT: slli a0, a0, 13
|
|
; RV64IZBB-NEXT: addi a0, a0, -272
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_8:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 583
|
|
; RV64IZBS-NEXT: addi a0, a0, -1875
|
|
; RV64IZBS-NEXT: slli a0, a0, 14
|
|
; RV64IZBS-NEXT: addi a0, a0, -947
|
|
; RV64IZBS-NEXT: slli a0, a0, 12
|
|
; RV64IZBS-NEXT: addi a0, a0, 1511
|
|
; RV64IZBS-NEXT: slli a0, a0, 13
|
|
; RV64IZBS-NEXT: addi a0, a0, -272
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_8:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 583
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1875
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 14
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -947
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1511
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 13
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -272
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_8:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 633806
|
|
; RV32-REMAT-NEXT: addi a0, a0, -272
|
|
; RV32-REMAT-NEXT: lui a1, 74565
|
|
; RV32-REMAT-NEXT: addi a1, a1, 1656
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_8:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 583
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1875
|
|
; RV64-REMAT-NEXT: slli a0, a0, 14
|
|
; RV64-REMAT-NEXT: addi a0, a0, -947
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1511
|
|
; RV64-REMAT-NEXT: slli a0, a0, 13
|
|
; RV64-REMAT-NEXT: addi a0, a0, -272
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 1311768467463790320 ; 0x1234_5678_9ABC_DEF0
|
|
}
|
|
|
|
define i64 @imm64_9() nounwind {
|
|
; RV32I-LABEL: imm64_9:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a0, -1
|
|
; RV32I-NEXT: li a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_9:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a0, -1
|
|
; RV32IXQCILI-NEXT: li a1, -1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_9:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, -1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_9:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, -1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_9:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, -1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_9:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, -1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_9:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, -1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_9:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a0, -1
|
|
; RV32-REMAT-NEXT: li a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_9:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, -1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -1
|
|
}
|
|
|
|
; Various cases where extraneous ADDIs can be inserted where a (left shifted)
|
|
; LUI suffices.
|
|
|
|
define i64 @imm_left_shifted_lui_1() nounwind {
|
|
; RV32I-LABEL: imm_left_shifted_lui_1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 524290
|
|
; RV32I-NEXT: li a1, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_left_shifted_lui_1:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: lui a0, 524290
|
|
; RV32IXQCILI-NEXT: li a1, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_left_shifted_lui_1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 262145
|
|
; RV64I-NEXT: slli a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_left_shifted_lui_1:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 262145
|
|
; RV64IZBA-NEXT: slli a0, a0, 1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_left_shifted_lui_1:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 262145
|
|
; RV64IZBB-NEXT: slli a0, a0, 1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_left_shifted_lui_1:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 262145
|
|
; RV64IZBS-NEXT: slli a0, a0, 1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_left_shifted_lui_1:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 262145
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_left_shifted_lui_1:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 524290
|
|
; RV32-REMAT-NEXT: li a1, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_left_shifted_lui_1:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 262145
|
|
; RV64-REMAT-NEXT: slli a0, a0, 1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 2147491840 ; 0x8000_2000
|
|
}
|
|
|
|
define i64 @imm_left_shifted_lui_2() nounwind {
|
|
; RV32I-LABEL: imm_left_shifted_lui_2:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 4
|
|
; RV32I-NEXT: li a1, 1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_left_shifted_lui_2:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: lui a0, 4
|
|
; RV32IXQCILI-NEXT: li a1, 1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_left_shifted_lui_2:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 262145
|
|
; RV64I-NEXT: slli a0, a0, 2
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_left_shifted_lui_2:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 262145
|
|
; RV64IZBA-NEXT: slli a0, a0, 2
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_left_shifted_lui_2:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 262145
|
|
; RV64IZBB-NEXT: slli a0, a0, 2
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_left_shifted_lui_2:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 262145
|
|
; RV64IZBS-NEXT: slli a0, a0, 2
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_left_shifted_lui_2:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 262145
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 2
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_left_shifted_lui_2:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 4
|
|
; RV32-REMAT-NEXT: li a1, 1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_left_shifted_lui_2:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 262145
|
|
; RV64-REMAT-NEXT: slli a0, a0, 2
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 4294983680 ; 0x1_0000_4000
|
|
}
|
|
|
|
define i64 @imm_left_shifted_lui_3() nounwind {
|
|
; RV32I-LABEL: imm_left_shifted_lui_3:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a1, 1
|
|
; RV32I-NEXT: addi a1, a1, 1
|
|
; RV32I-NEXT: li a0, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_left_shifted_lui_3:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.li a1, 4097
|
|
; RV32IXQCILI-NEXT: li a0, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_left_shifted_lui_3:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 4097
|
|
; RV64I-NEXT: slli a0, a0, 20
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_left_shifted_lui_3:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 4097
|
|
; RV64IZBA-NEXT: slli a0, a0, 20
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_left_shifted_lui_3:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 4097
|
|
; RV64IZBB-NEXT: slli a0, a0, 20
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_left_shifted_lui_3:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 4097
|
|
; RV64IZBS-NEXT: slli a0, a0, 20
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_left_shifted_lui_3:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 4097
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 20
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_left_shifted_lui_3:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a1, 1
|
|
; RV32-REMAT-NEXT: addi a1, a1, 1
|
|
; RV32-REMAT-NEXT: li a0, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_left_shifted_lui_3:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 4097
|
|
; RV64-REMAT-NEXT: slli a0, a0, 20
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 17596481011712 ; 0x1001_0000_0000
|
|
}
|
|
|
|
; Various cases where extraneous ADDIs can be inserted where a (right shifted)
|
|
; LUI suffices, or where multiple ADDIs can be used instead of a single LUI.
|
|
|
|
define i64 @imm_right_shifted_lui_1() nounwind {
|
|
; RV32I-LABEL: imm_right_shifted_lui_1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 1048575
|
|
; RV32I-NEXT: lui a1, 16
|
|
; RV32I-NEXT: addi a0, a0, 1
|
|
; RV32I-NEXT: addi a1, a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_right_shifted_lui_1:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.li a0, -4095
|
|
; RV32IXQCILI-NEXT: qc.li a1, 65535
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_right_shifted_lui_1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 983056
|
|
; RV64I-NEXT: srli a0, a0, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_right_shifted_lui_1:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 983056
|
|
; RV64IZBA-NEXT: srli a0, a0, 16
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_right_shifted_lui_1:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 983056
|
|
; RV64IZBB-NEXT: srli a0, a0, 16
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_right_shifted_lui_1:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 983056
|
|
; RV64IZBS-NEXT: srli a0, a0, 16
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_right_shifted_lui_1:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 983056
|
|
; RV64IXTHEADBB-NEXT: srli a0, a0, 16
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_right_shifted_lui_1:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 1048575
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1
|
|
; RV32-REMAT-NEXT: lui a1, 16
|
|
; RV32-REMAT-NEXT: addi a1, a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_right_shifted_lui_1:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 983056
|
|
; RV64-REMAT-NEXT: srli a0, a0, 16
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 281474976706561 ; 0xFFFF_FFFF_F001
|
|
}
|
|
|
|
define i64 @imm_right_shifted_lui_2() nounwind {
|
|
; RV32I-LABEL: imm_right_shifted_lui_2:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 1048575
|
|
; RV32I-NEXT: addi a0, a0, 1
|
|
; RV32I-NEXT: li a1, 255
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_right_shifted_lui_2:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.li a0, -4095
|
|
; RV32IXQCILI-NEXT: li a1, 255
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_right_shifted_lui_2:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 1044481
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: srli a0, a0, 24
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_right_shifted_lui_2:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 1044481
|
|
; RV64IZBA-NEXT: slli a0, a0, 12
|
|
; RV64IZBA-NEXT: srli a0, a0, 24
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_right_shifted_lui_2:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 1044481
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: srli a0, a0, 24
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_right_shifted_lui_2:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 1044481
|
|
; RV64IZBS-NEXT: slli a0, a0, 12
|
|
; RV64IZBS-NEXT: srli a0, a0, 24
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_right_shifted_lui_2:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 1044481
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: srli a0, a0, 24
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_right_shifted_lui_2:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 1048575
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1
|
|
; RV32-REMAT-NEXT: li a1, 255
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_right_shifted_lui_2:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 1044481
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: srli a0, a0, 24
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 1099511623681 ; 0xFF_FFFF_F001
|
|
}
|
|
|
|
; We can materialize the upper bits with a single (shifted) LUI, but that option
|
|
; can be missed due to the lower bits, which aren't just 1s or just 0s.
|
|
|
|
define i64 @imm_decoupled_lui_addi() nounwind {
|
|
; RV32I-LABEL: imm_decoupled_lui_addi:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a0, -3
|
|
; RV32I-NEXT: lui a1, 1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_decoupled_lui_addi:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a0, -3
|
|
; RV32IXQCILI-NEXT: lui a1, 1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_decoupled_lui_addi:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 4097
|
|
; RV64I-NEXT: slli a0, a0, 20
|
|
; RV64I-NEXT: addi a0, a0, -3
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_decoupled_lui_addi:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 4097
|
|
; RV64IZBA-NEXT: slli a0, a0, 20
|
|
; RV64IZBA-NEXT: addi a0, a0, -3
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_decoupled_lui_addi:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 4097
|
|
; RV64IZBB-NEXT: slli a0, a0, 20
|
|
; RV64IZBB-NEXT: addi a0, a0, -3
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_decoupled_lui_addi:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 4097
|
|
; RV64IZBS-NEXT: slli a0, a0, 20
|
|
; RV64IZBS-NEXT: addi a0, a0, -3
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_decoupled_lui_addi:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 4097
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 20
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -3
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_decoupled_lui_addi:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a0, -3
|
|
; RV32-REMAT-NEXT: lui a1, 1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_decoupled_lui_addi:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 4097
|
|
; RV64-REMAT-NEXT: slli a0, a0, 20
|
|
; RV64-REMAT-NEXT: addi a0, a0, -3
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 17596481011709 ; 0x1000_FFFF_FFFD
|
|
}
|
|
|
|
; This constant can be materialized for RV64 with LUI+SRLI+XORI.
|
|
|
|
define i64 @imm_end_xori_1() nounwind {
|
|
; RV32I-LABEL: imm_end_xori_1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 8192
|
|
; RV32I-NEXT: addi a0, a0, -1
|
|
; RV32I-NEXT: lui a1, 917504
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_end_xori_1:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 33554431
|
|
; RV32IXQCILI-NEXT: lui a1, 917504
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_end_xori_1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 983040
|
|
; RV64I-NEXT: srli a0, a0, 3
|
|
; RV64I-NEXT: not a0, a0
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_end_xori_1:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 983040
|
|
; RV64IZBA-NEXT: srli a0, a0, 3
|
|
; RV64IZBA-NEXT: not a0, a0
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_end_xori_1:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 983040
|
|
; RV64IZBB-NEXT: srli a0, a0, 3
|
|
; RV64IZBB-NEXT: not a0, a0
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_end_xori_1:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 983040
|
|
; RV64IZBS-NEXT: srli a0, a0, 3
|
|
; RV64IZBS-NEXT: not a0, a0
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_end_xori_1:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 983040
|
|
; RV64IXTHEADBB-NEXT: srli a0, a0, 3
|
|
; RV64IXTHEADBB-NEXT: not a0, a0
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_end_xori_1:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 8192
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1
|
|
; RV32-REMAT-NEXT: lui a1, 917504
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_end_xori_1:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 983040
|
|
; RV64-REMAT-NEXT: srli a0, a0, 3
|
|
; RV64-REMAT-NEXT: not a0, a0
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -2305843009180139521 ; 0xE000_0000_01FF_FFFF
|
|
}
|
|
|
|
; This constant can be materialized for RV64 with ADDI+SLLI+ADDI+ADDI.
|
|
|
|
define i64 @imm_end_2addi_1() nounwind {
|
|
; RV32I-LABEL: imm_end_2addi_1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 1048575
|
|
; RV32I-NEXT: lui a1, 1048512
|
|
; RV32I-NEXT: addi a0, a0, 2047
|
|
; RV32I-NEXT: addi a1, a1, 127
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_end_2addi_1:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.li a0, -2049
|
|
; RV32IXQCILI-NEXT: qc.li a1, -262017
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_end_2addi_1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, -2047
|
|
; RV64I-NEXT: slli a0, a0, 39
|
|
; RV64I-NEXT: addi a0, a0, -2048
|
|
; RV64I-NEXT: addi a0, a0, -1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_end_2addi_1:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, -2047
|
|
; RV64IZBA-NEXT: slli a0, a0, 39
|
|
; RV64IZBA-NEXT: addi a0, a0, -2048
|
|
; RV64IZBA-NEXT: addi a0, a0, -1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_end_2addi_1:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, -2047
|
|
; RV64IZBB-NEXT: slli a0, a0, 39
|
|
; RV64IZBB-NEXT: addi a0, a0, -2048
|
|
; RV64IZBB-NEXT: addi a0, a0, -1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_end_2addi_1:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, -2047
|
|
; RV64IZBS-NEXT: slli a0, a0, 39
|
|
; RV64IZBS-NEXT: addi a0, a0, -2048
|
|
; RV64IZBS-NEXT: addi a0, a0, -1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_end_2addi_1:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, -2047
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 39
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -2048
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_end_2addi_1:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 1048575
|
|
; RV32-REMAT-NEXT: addi a0, a0, 2047
|
|
; RV32-REMAT-NEXT: lui a1, 1048512
|
|
; RV32-REMAT-NEXT: addi a1, a1, 127
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_end_2addi_1:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, -2047
|
|
; RV64-REMAT-NEXT: slli a0, a0, 39
|
|
; RV64-REMAT-NEXT: addi a0, a0, -2048
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -1125350151030785 ; 0xFFFC_007F_FFFF_F7FF
|
|
}
|
|
|
|
; This constant can be more efficiently materialized for RV64 if we use two
|
|
; registers instead of one.
|
|
|
|
define i64 @imm_2reg_1() nounwind {
|
|
; RV32I-LABEL: imm_2reg_1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 74565
|
|
; RV32I-NEXT: addi a0, a0, 1656
|
|
; RV32I-NEXT: lui a1, 983040
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_2reg_1:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 305419896
|
|
; RV32IXQCILI-NEXT: lui a1, 983040
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_2reg_1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 74565
|
|
; RV64I-NEXT: addi a0, a0, 1656
|
|
; RV64I-NEXT: slli a1, a0, 57
|
|
; RV64I-NEXT: add a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_2reg_1:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 74565
|
|
; RV64IZBA-NEXT: addi a0, a0, 1656
|
|
; RV64IZBA-NEXT: slli a1, a0, 57
|
|
; RV64IZBA-NEXT: add a0, a0, a1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_2reg_1:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 74565
|
|
; RV64IZBB-NEXT: addi a0, a0, 1656
|
|
; RV64IZBB-NEXT: slli a1, a0, 57
|
|
; RV64IZBB-NEXT: add a0, a0, a1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_2reg_1:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 74565
|
|
; RV64IZBS-NEXT: addi a0, a0, 1656
|
|
; RV64IZBS-NEXT: slli a1, a0, 57
|
|
; RV64IZBS-NEXT: add a0, a0, a1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_2reg_1:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 74565
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1656
|
|
; RV64IXTHEADBB-NEXT: slli a1, a0, 57
|
|
; RV64IXTHEADBB-NEXT: add a0, a0, a1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_2reg_1:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 74565
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1656
|
|
; RV32-REMAT-NEXT: lui a1, 983040
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_2reg_1:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 74565
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1656
|
|
; RV64-REMAT-NEXT: slli a1, a0, 57
|
|
; RV64-REMAT-NEXT: add a0, a0, a1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -1152921504301427080 ; 0xF000_0000_1234_5678
|
|
}
|
|
|
|
define void @imm_store_i8_neg1(ptr %p) nounwind {
|
|
; RV32I-LABEL: imm_store_i8_neg1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a1, -1
|
|
; RV32I-NEXT: sb a1, 0(a0)
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_store_i8_neg1:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a1, -1
|
|
; RV32IXQCILI-NEXT: sb a1, 0(a0)
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_store_i8_neg1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a1, -1
|
|
; RV64I-NEXT: sb a1, 0(a0)
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_store_i8_neg1:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a1, -1
|
|
; RV64IZBA-NEXT: sb a1, 0(a0)
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_store_i8_neg1:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a1, -1
|
|
; RV64IZBB-NEXT: sb a1, 0(a0)
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_store_i8_neg1:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a1, -1
|
|
; RV64IZBS-NEXT: sb a1, 0(a0)
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_store_i8_neg1:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a1, -1
|
|
; RV64IXTHEADBB-NEXT: sb a1, 0(a0)
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_store_i8_neg1:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a1, -1
|
|
; RV32-REMAT-NEXT: sb a1, 0(a0)
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_store_i8_neg1:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a1, -1
|
|
; RV64-REMAT-NEXT: sb a1, 0(a0)
|
|
; RV64-REMAT-NEXT: ret
|
|
store i8 -1, ptr %p
|
|
ret void
|
|
}
|
|
|
|
define void @imm_store_i16_neg1(ptr %p) nounwind {
|
|
; RV32I-LABEL: imm_store_i16_neg1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a1, -1
|
|
; RV32I-NEXT: sh a1, 0(a0)
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_store_i16_neg1:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a1, -1
|
|
; RV32IXQCILI-NEXT: sh a1, 0(a0)
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_store_i16_neg1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a1, -1
|
|
; RV64I-NEXT: sh a1, 0(a0)
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_store_i16_neg1:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a1, -1
|
|
; RV64IZBA-NEXT: sh a1, 0(a0)
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_store_i16_neg1:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a1, -1
|
|
; RV64IZBB-NEXT: sh a1, 0(a0)
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_store_i16_neg1:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a1, -1
|
|
; RV64IZBS-NEXT: sh a1, 0(a0)
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_store_i16_neg1:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a1, -1
|
|
; RV64IXTHEADBB-NEXT: sh a1, 0(a0)
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_store_i16_neg1:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a1, -1
|
|
; RV32-REMAT-NEXT: sh a1, 0(a0)
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_store_i16_neg1:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a1, -1
|
|
; RV64-REMAT-NEXT: sh a1, 0(a0)
|
|
; RV64-REMAT-NEXT: ret
|
|
store i16 -1, ptr %p
|
|
ret void
|
|
}
|
|
|
|
define void @imm_store_i32_neg1(ptr %p) nounwind {
|
|
; RV32I-LABEL: imm_store_i32_neg1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a1, -1
|
|
; RV32I-NEXT: sw a1, 0(a0)
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_store_i32_neg1:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a1, -1
|
|
; RV32IXQCILI-NEXT: sw a1, 0(a0)
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_store_i32_neg1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a1, -1
|
|
; RV64I-NEXT: sw a1, 0(a0)
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_store_i32_neg1:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a1, -1
|
|
; RV64IZBA-NEXT: sw a1, 0(a0)
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_store_i32_neg1:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a1, -1
|
|
; RV64IZBB-NEXT: sw a1, 0(a0)
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_store_i32_neg1:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a1, -1
|
|
; RV64IZBS-NEXT: sw a1, 0(a0)
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_store_i32_neg1:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a1, -1
|
|
; RV64IXTHEADBB-NEXT: sw a1, 0(a0)
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_store_i32_neg1:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a1, -1
|
|
; RV32-REMAT-NEXT: sw a1, 0(a0)
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_store_i32_neg1:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a1, -1
|
|
; RV64-REMAT-NEXT: sw a1, 0(a0)
|
|
; RV64-REMAT-NEXT: ret
|
|
store i32 -1, ptr %p
|
|
ret void
|
|
}
|
|
|
|
define i64 @imm_5372288229() {
|
|
; RV32I-LABEL: imm_5372288229:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 263018
|
|
; RV32I-NEXT: addi a0, a0, -795
|
|
; RV32I-NEXT: li a1, 1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_5372288229:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 1077320933
|
|
; RV32IXQCILI-NEXT: li a1, 1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_5372288229:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 160
|
|
; RV64I-NEXT: addi a0, a0, 437
|
|
; RV64I-NEXT: slli a0, a0, 13
|
|
; RV64I-NEXT: addi a0, a0, -795
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_5372288229:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 655797
|
|
; RV64IZBA-NEXT: slli.uw a0, a0, 1
|
|
; RV64IZBA-NEXT: addi a0, a0, -795
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_5372288229:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 160
|
|
; RV64IZBB-NEXT: addi a0, a0, 437
|
|
; RV64IZBB-NEXT: slli a0, a0, 13
|
|
; RV64IZBB-NEXT: addi a0, a0, -795
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_5372288229:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 263018
|
|
; RV64IZBS-NEXT: addi a0, a0, -795
|
|
; RV64IZBS-NEXT: bseti a0, a0, 32
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_5372288229:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 160
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 437
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 13
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -795
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_5372288229:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 263018
|
|
; RV32-REMAT-NEXT: addi a0, a0, -795
|
|
; RV32-REMAT-NEXT: li a1, 1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_5372288229:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 160
|
|
; RV64-REMAT-NEXT: addi a0, a0, 437
|
|
; RV64-REMAT-NEXT: slli a0, a0, 13
|
|
; RV64-REMAT-NEXT: addi a0, a0, -795
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 5372288229
|
|
}
|
|
|
|
define i64 @imm_neg_5372288229() {
|
|
; RV32I-LABEL: imm_neg_5372288229:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 785558
|
|
; RV32I-NEXT: addi a0, a0, 795
|
|
; RV32I-NEXT: li a1, -2
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_5372288229:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1077320933
|
|
; RV32IXQCILI-NEXT: li a1, -2
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_5372288229:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 1048416
|
|
; RV64I-NEXT: addi a0, a0, -437
|
|
; RV64I-NEXT: slli a0, a0, 13
|
|
; RV64I-NEXT: addi a0, a0, 795
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_5372288229:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 611378
|
|
; RV64IZBA-NEXT: addi a0, a0, 265
|
|
; RV64IZBA-NEXT: sh1add a0, a0, a0
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_5372288229:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 1048416
|
|
; RV64IZBB-NEXT: addi a0, a0, -437
|
|
; RV64IZBB-NEXT: slli a0, a0, 13
|
|
; RV64IZBB-NEXT: addi a0, a0, 795
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_5372288229:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 785558
|
|
; RV64IZBS-NEXT: addi a0, a0, 795
|
|
; RV64IZBS-NEXT: bclri a0, a0, 32
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_5372288229:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 1048416
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -437
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 13
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 795
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_5372288229:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 785558
|
|
; RV32-REMAT-NEXT: addi a0, a0, 795
|
|
; RV32-REMAT-NEXT: li a1, -2
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_5372288229:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 1048416
|
|
; RV64-REMAT-NEXT: addi a0, a0, -437
|
|
; RV64-REMAT-NEXT: slli a0, a0, 13
|
|
; RV64-REMAT-NEXT: addi a0, a0, 795
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -5372288229
|
|
}
|
|
|
|
define i64 @imm_8953813715() {
|
|
; RV32I-LABEL: imm_8953813715:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 88838
|
|
; RV32I-NEXT: addi a0, a0, -1325
|
|
; RV32I-NEXT: li a1, 2
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_8953813715:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 363879123
|
|
; RV32IXQCILI-NEXT: li a1, 2
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_8953813715:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 267
|
|
; RV64I-NEXT: addi a0, a0, -637
|
|
; RV64I-NEXT: slli a0, a0, 13
|
|
; RV64I-NEXT: addi a0, a0, -1325
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_8953813715:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 437198
|
|
; RV64IZBA-NEXT: addi a0, a0, -265
|
|
; RV64IZBA-NEXT: sh2add a0, a0, a0
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_8953813715:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 267
|
|
; RV64IZBB-NEXT: addi a0, a0, -637
|
|
; RV64IZBB-NEXT: slli a0, a0, 13
|
|
; RV64IZBB-NEXT: addi a0, a0, -1325
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_8953813715:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 88838
|
|
; RV64IZBS-NEXT: addi a0, a0, -1325
|
|
; RV64IZBS-NEXT: bseti a0, a0, 33
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_8953813715:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 267
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -637
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 13
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1325
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_8953813715:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 88838
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1325
|
|
; RV32-REMAT-NEXT: li a1, 2
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_8953813715:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 267
|
|
; RV64-REMAT-NEXT: addi a0, a0, -637
|
|
; RV64-REMAT-NEXT: slli a0, a0, 13
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1325
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 8953813715
|
|
}
|
|
|
|
define i64 @imm_neg_8953813715() {
|
|
; RV32I-LABEL: imm_neg_8953813715:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 959738
|
|
; RV32I-NEXT: addi a0, a0, 1325
|
|
; RV32I-NEXT: li a1, -3
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_8953813715:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -363879123
|
|
; RV32IXQCILI-NEXT: li a1, -3
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_8953813715:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 1048309
|
|
; RV64I-NEXT: addi a0, a0, 637
|
|
; RV64I-NEXT: slli a0, a0, 13
|
|
; RV64I-NEXT: addi a0, a0, 1325
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_8953813715:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 611378
|
|
; RV64IZBA-NEXT: addi a0, a0, 265
|
|
; RV64IZBA-NEXT: sh2add a0, a0, a0
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_8953813715:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 1048309
|
|
; RV64IZBB-NEXT: addi a0, a0, 637
|
|
; RV64IZBB-NEXT: slli a0, a0, 13
|
|
; RV64IZBB-NEXT: addi a0, a0, 1325
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_8953813715:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 959738
|
|
; RV64IZBS-NEXT: addi a0, a0, 1325
|
|
; RV64IZBS-NEXT: bclri a0, a0, 33
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_8953813715:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 1048309
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 637
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 13
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1325
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_8953813715:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 959738
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1325
|
|
; RV32-REMAT-NEXT: li a1, -3
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_8953813715:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 1048309
|
|
; RV64-REMAT-NEXT: addi a0, a0, 637
|
|
; RV64-REMAT-NEXT: slli a0, a0, 13
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1325
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -8953813715
|
|
}
|
|
|
|
define i64 @imm_16116864687() {
|
|
; RV32I-LABEL: imm_16116864687:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 789053
|
|
; RV32I-NEXT: addi a0, a0, 1711
|
|
; RV32I-NEXT: li a1, 3
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_16116864687:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1063004497
|
|
; RV32IXQCILI-NEXT: li a1, 3
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_16116864687:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 961
|
|
; RV64I-NEXT: addi a0, a0, -1475
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, 1711
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_16116864687:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 437198
|
|
; RV64IZBA-NEXT: addi a0, a0, -265
|
|
; RV64IZBA-NEXT: sh3add a0, a0, a0
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_16116864687:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 961
|
|
; RV64IZBB-NEXT: addi a0, a0, -1475
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, 1711
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_16116864687:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 961
|
|
; RV64IZBS-NEXT: addi a0, a0, -1475
|
|
; RV64IZBS-NEXT: slli a0, a0, 12
|
|
; RV64IZBS-NEXT: addi a0, a0, 1711
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_16116864687:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 961
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1475
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1711
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_16116864687:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 789053
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1711
|
|
; RV32-REMAT-NEXT: li a1, 3
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_16116864687:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 961
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1475
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1711
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 16116864687
|
|
}
|
|
|
|
define i64 @imm_neg_16116864687() {
|
|
; RV32I-LABEL: imm_neg_16116864687:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 259523
|
|
; RV32I-NEXT: addi a0, a0, -1711
|
|
; RV32I-NEXT: li a1, -4
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_16116864687:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 1063004497
|
|
; RV32IXQCILI-NEXT: li a1, -4
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_16116864687:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 1047615
|
|
; RV64I-NEXT: addi a0, a0, 1475
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, -1711
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_16116864687:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 611378
|
|
; RV64IZBA-NEXT: addi a0, a0, 265
|
|
; RV64IZBA-NEXT: sh3add a0, a0, a0
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_16116864687:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 1047615
|
|
; RV64IZBB-NEXT: addi a0, a0, 1475
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, -1711
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_16116864687:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 1047615
|
|
; RV64IZBS-NEXT: addi a0, a0, 1475
|
|
; RV64IZBS-NEXT: slli a0, a0, 12
|
|
; RV64IZBS-NEXT: addi a0, a0, -1711
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_16116864687:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 1047615
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1475
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1711
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_16116864687:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 259523
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1711
|
|
; RV32-REMAT-NEXT: li a1, -4
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_16116864687:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 1047615
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1475
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1711
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -16116864687
|
|
}
|
|
|
|
define i64 @imm_2344336315() {
|
|
; RV32I-LABEL: imm_2344336315:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 572348
|
|
; RV32I-NEXT: addi a0, a0, -1093
|
|
; RV32I-NEXT: li a1, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_2344336315:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1950630981
|
|
; RV32IXQCILI-NEXT: li a1, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_2344336315:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 143087
|
|
; RV64I-NEXT: slli a0, a0, 2
|
|
; RV64I-NEXT: addi a0, a0, -1093
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_2344336315:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 143087
|
|
; RV64IZBA-NEXT: slli a0, a0, 2
|
|
; RV64IZBA-NEXT: addi a0, a0, -1093
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_2344336315:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 143087
|
|
; RV64IZBB-NEXT: slli a0, a0, 2
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_2344336315:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 143087
|
|
; RV64IZBS-NEXT: slli a0, a0, 2
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_2344336315:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 143087
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 2
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_2344336315:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 572348
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV32-REMAT-NEXT: li a1, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_2344336315:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 143087
|
|
; RV64-REMAT-NEXT: slli a0, a0, 2
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 2344336315 ; 0x8bbbbbbb
|
|
}
|
|
|
|
define i64 @imm_70370820078523() {
|
|
; RV32I-LABEL: imm_70370820078523:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 506812
|
|
; RV32I-NEXT: addi a0, a0, -1093
|
|
; RV32I-NEXT: lui a1, 4
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_70370820078523:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 2075900859
|
|
; RV32IXQCILI-NEXT: lui a1, 4
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64-NOPOOL-LABEL: imm_70370820078523:
|
|
; RV64-NOPOOL: # %bb.0:
|
|
; RV64-NOPOOL-NEXT: lui a0, 256
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, 31
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 12
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, -273
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 14
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, -1093
|
|
; RV64-NOPOOL-NEXT: ret
|
|
;
|
|
; RV64I-POOL-LABEL: imm_70370820078523:
|
|
; RV64I-POOL: # %bb.0:
|
|
; RV64I-POOL-NEXT: lui a0, %hi(.LCPI38_0)
|
|
; RV64I-POOL-NEXT: ld a0, %lo(.LCPI38_0)(a0)
|
|
; RV64I-POOL-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_70370820078523:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 256
|
|
; RV64IZBA-NEXT: addi a0, a0, 31
|
|
; RV64IZBA-NEXT: slli a0, a0, 12
|
|
; RV64IZBA-NEXT: addi a0, a0, -273
|
|
; RV64IZBA-NEXT: slli a0, a0, 14
|
|
; RV64IZBA-NEXT: addi a0, a0, -1093
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_70370820078523:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 256
|
|
; RV64IZBB-NEXT: addi a0, a0, 31
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, -273
|
|
; RV64IZBB-NEXT: slli a0, a0, 14
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_70370820078523:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 506812
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: bseti a0, a0, 46
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_70370820078523:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 256
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 31
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -273
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 14
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_70370820078523:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 506812
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV32-REMAT-NEXT: lui a1, 4
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_70370820078523:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 256
|
|
; RV64-REMAT-NEXT: addi a0, a0, 31
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, -273
|
|
; RV64-REMAT-NEXT: slli a0, a0, 14
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 70370820078523 ; 0x40007bbbbbbb
|
|
}
|
|
|
|
define i64 @imm_neg_9223372034778874949() {
|
|
; RV32I-LABEL: imm_neg_9223372034778874949:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 506812
|
|
; RV32I-NEXT: addi a0, a0, -1093
|
|
; RV32I-NEXT: lui a1, 524288
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_9223372034778874949:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 2075900859
|
|
; RV32IXQCILI-NEXT: lui a1, 524288
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_9223372034778874949:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 506812
|
|
; RV64I-NEXT: addi a0, a0, -1093
|
|
; RV64I-NEXT: slli a1, a0, 63
|
|
; RV64I-NEXT: add a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_9223372034778874949:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 506812
|
|
; RV64IZBA-NEXT: addi a0, a0, -1093
|
|
; RV64IZBA-NEXT: slli a1, a0, 63
|
|
; RV64IZBA-NEXT: add a0, a0, a1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_9223372034778874949:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 506812
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: slli a1, a0, 63
|
|
; RV64IZBB-NEXT: add a0, a0, a1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_9223372034778874949:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 506812
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: bseti a0, a0, 63
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_9223372034778874949:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 506812
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: slli a1, a0, 63
|
|
; RV64IXTHEADBB-NEXT: add a0, a0, a1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_9223372034778874949:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 506812
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV32-REMAT-NEXT: lui a1, 524288
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_9223372034778874949:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 506812
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: slli a1, a0, 63
|
|
; RV64-REMAT-NEXT: add a0, a0, a1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -9223372034778874949 ; 0x800000007bbbbbbb
|
|
}
|
|
|
|
define i64 @imm_neg_9223301666034697285() {
|
|
; RV32I-LABEL: imm_neg_9223301666034697285:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 506812
|
|
; RV32I-NEXT: addi a0, a0, -1093
|
|
; RV32I-NEXT: lui a1, 524292
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_9223301666034697285:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 2075900859
|
|
; RV32IXQCILI-NEXT: lui a1, 524292
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64-NOPOOL-LABEL: imm_neg_9223301666034697285:
|
|
; RV64-NOPOOL: # %bb.0:
|
|
; RV64-NOPOOL-NEXT: lui a0, 917505
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 8
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, 31
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 12
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, -273
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 14
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, -1093
|
|
; RV64-NOPOOL-NEXT: ret
|
|
;
|
|
; RV64I-POOL-LABEL: imm_neg_9223301666034697285:
|
|
; RV64I-POOL: # %bb.0:
|
|
; RV64I-POOL-NEXT: lui a0, %hi(.LCPI40_0)
|
|
; RV64I-POOL-NEXT: ld a0, %lo(.LCPI40_0)(a0)
|
|
; RV64I-POOL-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_9223301666034697285:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 917505
|
|
; RV64IZBA-NEXT: slli a0, a0, 8
|
|
; RV64IZBA-NEXT: addi a0, a0, 31
|
|
; RV64IZBA-NEXT: slli a0, a0, 12
|
|
; RV64IZBA-NEXT: addi a0, a0, -273
|
|
; RV64IZBA-NEXT: slli a0, a0, 14
|
|
; RV64IZBA-NEXT: addi a0, a0, -1093
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_9223301666034697285:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 917505
|
|
; RV64IZBB-NEXT: slli a0, a0, 8
|
|
; RV64IZBB-NEXT: addi a0, a0, 31
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, -273
|
|
; RV64IZBB-NEXT: slli a0, a0, 14
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_9223301666034697285:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 506812
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: bseti a0, a0, 46
|
|
; RV64IZBS-NEXT: bseti a0, a0, 63
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_9223301666034697285:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 917505
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 8
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 31
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -273
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 14
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_9223301666034697285:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 506812
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV32-REMAT-NEXT: lui a1, 524292
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_9223301666034697285:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 917505
|
|
; RV64-REMAT-NEXT: slli a0, a0, 8
|
|
; RV64-REMAT-NEXT: addi a0, a0, 31
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, -273
|
|
; RV64-REMAT-NEXT: slli a0, a0, 14
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -9223301666034697285 ; 0x800040007bbbbbbb
|
|
}
|
|
|
|
define i64 @imm_neg_2219066437() {
|
|
; RV32I-LABEL: imm_neg_2219066437:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 506812
|
|
; RV32I-NEXT: addi a0, a0, -1093
|
|
; RV32I-NEXT: li a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_2219066437:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 2075900859
|
|
; RV32IXQCILI-NEXT: li a1, -1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_2219066437:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 913135
|
|
; RV64I-NEXT: slli a0, a0, 2
|
|
; RV64I-NEXT: addi a0, a0, -1093
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_2219066437:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 913135
|
|
; RV64IZBA-NEXT: slli a0, a0, 2
|
|
; RV64IZBA-NEXT: addi a0, a0, -1093
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_2219066437:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 913135
|
|
; RV64IZBB-NEXT: slli a0, a0, 2
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_2219066437:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 913135
|
|
; RV64IZBS-NEXT: slli a0, a0, 2
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_2219066437:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 913135
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 2
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_2219066437:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 506812
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV32-REMAT-NEXT: li a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_2219066437:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 913135
|
|
; RV64-REMAT-NEXT: slli a0, a0, 2
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -2219066437 ; 0xffffffff7bbbbbbb
|
|
}
|
|
|
|
define i64 @imm_neg_8798043653189() {
|
|
; RV32I-LABEL: imm_neg_8798043653189:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 572348
|
|
; RV32I-NEXT: lui a1, 1048575
|
|
; RV32I-NEXT: addi a0, a0, -1093
|
|
; RV32I-NEXT: addi a1, a1, 2047
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_8798043653189:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1950630981
|
|
; RV32IXQCILI-NEXT: qc.li a1, -2049
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_8798043653189:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 917475
|
|
; RV64I-NEXT: addi a0, a0, -273
|
|
; RV64I-NEXT: slli a0, a0, 14
|
|
; RV64I-NEXT: addi a0, a0, -1093
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_8798043653189:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 917475
|
|
; RV64IZBA-NEXT: addi a0, a0, -273
|
|
; RV64IZBA-NEXT: slli a0, a0, 14
|
|
; RV64IZBA-NEXT: addi a0, a0, -1093
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_8798043653189:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 917475
|
|
; RV64IZBB-NEXT: addi a0, a0, -273
|
|
; RV64IZBB-NEXT: slli a0, a0, 14
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_8798043653189:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 572348
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: bclri a0, a0, 43
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_8798043653189:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 917475
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -273
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 14
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_8798043653189:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 572348
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV32-REMAT-NEXT: lui a1, 1048575
|
|
; RV32-REMAT-NEXT: addi a1, a1, 2047
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_8798043653189:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 917475
|
|
; RV64-REMAT-NEXT: addi a0, a0, -273
|
|
; RV64-REMAT-NEXT: slli a0, a0, 14
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -8798043653189 ; 0xfffff7ff8bbbbbbb
|
|
}
|
|
|
|
define i64 @imm_9223372034904144827() {
|
|
; RV32I-LABEL: imm_9223372034904144827:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 572348
|
|
; RV32I-NEXT: lui a1, 524288
|
|
; RV32I-NEXT: addi a0, a0, -1093
|
|
; RV32I-NEXT: addi a1, a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_9223372034904144827:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1950630981
|
|
; RV32IXQCILI-NEXT: qc.e.li a1, 2147483647
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_9223372034904144827:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 572348
|
|
; RV64I-NEXT: addi a0, a0, -1093
|
|
; RV64I-NEXT: slli a1, a0, 63
|
|
; RV64I-NEXT: add a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_9223372034904144827:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 572348
|
|
; RV64IZBA-NEXT: addi a0, a0, -1093
|
|
; RV64IZBA-NEXT: slli a1, a0, 63
|
|
; RV64IZBA-NEXT: add a0, a0, a1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_9223372034904144827:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 572348
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: slli a1, a0, 63
|
|
; RV64IZBB-NEXT: add a0, a0, a1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_9223372034904144827:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 572348
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: bclri a0, a0, 63
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_9223372034904144827:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 572348
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: slli a1, a0, 63
|
|
; RV64IXTHEADBB-NEXT: add a0, a0, a1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_9223372034904144827:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 572348
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV32-REMAT-NEXT: lui a1, 524288
|
|
; RV32-REMAT-NEXT: addi a1, a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_9223372034904144827:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 572348
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: slli a1, a0, 63
|
|
; RV64-REMAT-NEXT: add a0, a0, a1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 9223372034904144827 ; 0x7fffffff8bbbbbbb
|
|
}
|
|
|
|
define i64 @imm_neg_9223354442718100411() {
|
|
; RV32I-LABEL: imm_neg_9223354442718100411:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 572348
|
|
; RV32I-NEXT: lui a1, 524287
|
|
; RV32I-NEXT: addi a0, a0, -1093
|
|
; RV32I-NEXT: addi a1, a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_9223354442718100411:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1950630981
|
|
; RV32IXQCILI-NEXT: qc.e.li a1, 2147479551
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64-NOPOOL-LABEL: imm_neg_9223354442718100411:
|
|
; RV64-NOPOOL: # %bb.0:
|
|
; RV64-NOPOOL-NEXT: lui a0, 524287
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 6
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, -29
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 12
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, -273
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 14
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, -1093
|
|
; RV64-NOPOOL-NEXT: ret
|
|
;
|
|
; RV64I-POOL-LABEL: imm_neg_9223354442718100411:
|
|
; RV64I-POOL: # %bb.0:
|
|
; RV64I-POOL-NEXT: lui a0, %hi(.LCPI44_0)
|
|
; RV64I-POOL-NEXT: ld a0, %lo(.LCPI44_0)(a0)
|
|
; RV64I-POOL-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_9223354442718100411:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 524287
|
|
; RV64IZBA-NEXT: slli a0, a0, 6
|
|
; RV64IZBA-NEXT: addi a0, a0, -29
|
|
; RV64IZBA-NEXT: slli a0, a0, 12
|
|
; RV64IZBA-NEXT: addi a0, a0, -273
|
|
; RV64IZBA-NEXT: slli a0, a0, 14
|
|
; RV64IZBA-NEXT: addi a0, a0, -1093
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_9223354442718100411:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 524287
|
|
; RV64IZBB-NEXT: slli a0, a0, 6
|
|
; RV64IZBB-NEXT: addi a0, a0, -29
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, -273
|
|
; RV64IZBB-NEXT: slli a0, a0, 14
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_9223354442718100411:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 572348
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: bclri a0, a0, 44
|
|
; RV64IZBS-NEXT: bclri a0, a0, 63
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_9223354442718100411:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 524287
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 6
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -29
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -273
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 14
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_9223354442718100411:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 572348
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV32-REMAT-NEXT: lui a1, 524287
|
|
; RV32-REMAT-NEXT: addi a1, a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_9223354442718100411:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 524287
|
|
; RV64-REMAT-NEXT: slli a0, a0, 6
|
|
; RV64-REMAT-NEXT: addi a0, a0, -29
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, -273
|
|
; RV64-REMAT-NEXT: slli a0, a0, 14
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 9223354442718100411 ; 0x7fffefff8bbbbbbb
|
|
}
|
|
|
|
define i64 @imm_2863311530() {
|
|
; RV32I-LABEL: imm_2863311530:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 699051
|
|
; RV32I-NEXT: addi a0, a0, -1366
|
|
; RV32I-NEXT: li a1, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_2863311530:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1431655766
|
|
; RV32IXQCILI-NEXT: li a1, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_2863311530:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 349525
|
|
; RV64I-NEXT: addi a0, a0, 1365
|
|
; RV64I-NEXT: slli a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_2863311530:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 349525
|
|
; RV64IZBA-NEXT: addi a0, a0, 1365
|
|
; RV64IZBA-NEXT: slli a0, a0, 1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_2863311530:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 349525
|
|
; RV64IZBB-NEXT: addi a0, a0, 1365
|
|
; RV64IZBB-NEXT: slli a0, a0, 1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_2863311530:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 349525
|
|
; RV64IZBS-NEXT: addi a0, a0, 1365
|
|
; RV64IZBS-NEXT: slli a0, a0, 1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_2863311530:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 349525
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1365
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_2863311530:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 699051
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1366
|
|
; RV32-REMAT-NEXT: li a1, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_2863311530:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 349525
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1365
|
|
; RV64-REMAT-NEXT: slli a0, a0, 1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 2863311530 ; #0xaaaaaaaa
|
|
}
|
|
|
|
define i64 @imm_neg_2863311530() {
|
|
; RV32I-LABEL: imm_neg_2863311530:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 349525
|
|
; RV32I-NEXT: addi a0, a0, 1366
|
|
; RV32I-NEXT: li a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_2863311530:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 1431655766
|
|
; RV32IXQCILI-NEXT: li a1, -1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_2863311530:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 699051
|
|
; RV64I-NEXT: addi a0, a0, -1365
|
|
; RV64I-NEXT: slli a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_2863311530:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 699051
|
|
; RV64IZBA-NEXT: addi a0, a0, -1365
|
|
; RV64IZBA-NEXT: slli a0, a0, 1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_2863311530:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 699051
|
|
; RV64IZBB-NEXT: addi a0, a0, -1365
|
|
; RV64IZBB-NEXT: slli a0, a0, 1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_2863311530:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 699051
|
|
; RV64IZBS-NEXT: addi a0, a0, -1365
|
|
; RV64IZBS-NEXT: slli a0, a0, 1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_2863311530:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 699051
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1365
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_2863311530:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 349525
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1366
|
|
; RV32-REMAT-NEXT: li a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_2863311530:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 699051
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1365
|
|
; RV64-REMAT-NEXT: slli a0, a0, 1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -2863311530 ; #0xffffffff55555556
|
|
}
|
|
|
|
define i64 @imm_2147486378() {
|
|
; RV32I-LABEL: imm_2147486378:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 524288
|
|
; RV32I-NEXT: addi a0, a0, 1365
|
|
; RV32I-NEXT: li a1, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_2147486378:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -2147482283
|
|
; RV32IXQCILI-NEXT: li a1, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_2147486378:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, 1
|
|
; RV64I-NEXT: slli a0, a0, 31
|
|
; RV64I-NEXT: addi a0, a0, 1365
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_2147486378:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, 1
|
|
; RV64IZBA-NEXT: slli a0, a0, 31
|
|
; RV64IZBA-NEXT: addi a0, a0, 1365
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_2147486378:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, 1
|
|
; RV64IZBB-NEXT: slli a0, a0, 31
|
|
; RV64IZBB-NEXT: addi a0, a0, 1365
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_2147486378:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, 1365
|
|
; RV64IZBS-NEXT: bseti a0, a0, 31
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_2147486378:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, 1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 31
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1365
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_2147486378:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 524288
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1365
|
|
; RV32-REMAT-NEXT: li a1, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_2147486378:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, 1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 31
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1365
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 2147485013
|
|
}
|
|
|
|
define i64 @imm_neg_2147485013() {
|
|
; RV32I-LABEL: imm_neg_2147485013:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 524288
|
|
; RV32I-NEXT: addi a0, a0, -1365
|
|
; RV32I-NEXT: li a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_2147485013:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 2147482283
|
|
; RV32IXQCILI-NEXT: li a1, -1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_2147485013:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 524288
|
|
; RV64I-NEXT: addi a0, a0, -1365
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_2147485013:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 524288
|
|
; RV64IZBA-NEXT: addi a0, a0, -1365
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_2147485013:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 524288
|
|
; RV64IZBB-NEXT: addi a0, a0, -1365
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_2147485013:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 524288
|
|
; RV64IZBS-NEXT: addi a0, a0, -1365
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_2147485013:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 524288
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1365
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_2147485013:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 524288
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1365
|
|
; RV32-REMAT-NEXT: li a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_2147485013:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 524288
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1365
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -2147485013
|
|
}
|
|
|
|
define i64 @imm_12900924131259() {
|
|
; RV32I-LABEL: imm_12900924131259:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 765952
|
|
; RV32I-NEXT: lui a1, 1
|
|
; RV32I-NEXT: addi a0, a0, 1979
|
|
; RV32I-NEXT: addi a1, a1, -1093
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_12900924131259:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1157625925
|
|
; RV32IXQCILI-NEXT: qc.li a1, 3003
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_12900924131259:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 188
|
|
; RV64I-NEXT: addi a0, a0, -1093
|
|
; RV64I-NEXT: slli a0, a0, 24
|
|
; RV64I-NEXT: addi a0, a0, 1979
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_12900924131259:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 768955
|
|
; RV64IZBA-NEXT: slli.uw a0, a0, 12
|
|
; RV64IZBA-NEXT: addi a0, a0, 1979
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_12900924131259:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 188
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: slli a0, a0, 24
|
|
; RV64IZBB-NEXT: addi a0, a0, 1979
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_12900924131259:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 188
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: slli a0, a0, 24
|
|
; RV64IZBS-NEXT: addi a0, a0, 1979
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_12900924131259:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 188
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 24
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1979
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_12900924131259:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 765952
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1979
|
|
; RV32-REMAT-NEXT: lui a1, 1
|
|
; RV32-REMAT-NEXT: addi a1, a1, -1093
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_12900924131259:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 188
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: slli a0, a0, 24
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1979
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 12900924131259
|
|
}
|
|
|
|
define i64 @imm_50394234880() {
|
|
; RV32I-LABEL: imm_50394234880:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 768944
|
|
; RV32I-NEXT: li a1, 11
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_50394234880:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: lui a0, 768944
|
|
; RV32IXQCILI-NEXT: li a1, 11
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_50394234880:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 188
|
|
; RV64I-NEXT: addi a0, a0, -1093
|
|
; RV64I-NEXT: slli a0, a0, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_50394234880:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 768955
|
|
; RV64IZBA-NEXT: slli.uw a0, a0, 4
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_50394234880:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 188
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: slli a0, a0, 16
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_50394234880:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 188
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: slli a0, a0, 16
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_50394234880:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 188
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 16
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_50394234880:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 768944
|
|
; RV32-REMAT-NEXT: li a1, 11
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_50394234880:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 188
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: slli a0, a0, 16
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 50394234880
|
|
}
|
|
|
|
define i64 @imm_12900936431479() {
|
|
; RV32I-LABEL: imm_12900936431479:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 768955
|
|
; RV32I-NEXT: lui a1, 1
|
|
; RV32I-NEXT: addi a0, a0, 1911
|
|
; RV32I-NEXT: addi a1, a1, -1093
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_12900936431479:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1145325705
|
|
; RV32IXQCILI-NEXT: qc.li a1, 3003
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_12900936431479:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 192239
|
|
; RV64I-NEXT: slli a0, a0, 2
|
|
; RV64I-NEXT: addi a0, a0, -1093
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, 1911
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_12900936431479:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 768956
|
|
; RV64IZBA-NEXT: addi a0, a0, -1093
|
|
; RV64IZBA-NEXT: slli.uw a0, a0, 12
|
|
; RV64IZBA-NEXT: addi a0, a0, 1911
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_12900936431479:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 192239
|
|
; RV64IZBB-NEXT: slli a0, a0, 2
|
|
; RV64IZBB-NEXT: addi a0, a0, -1093
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, 1911
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_12900936431479:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 192239
|
|
; RV64IZBS-NEXT: slli a0, a0, 2
|
|
; RV64IZBS-NEXT: addi a0, a0, -1093
|
|
; RV64IZBS-NEXT: slli a0, a0, 12
|
|
; RV64IZBS-NEXT: addi a0, a0, 1911
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_12900936431479:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 192239
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 2
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1911
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_12900936431479:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 768955
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1911
|
|
; RV32-REMAT-NEXT: lui a1, 1
|
|
; RV32-REMAT-NEXT: addi a1, a1, -1093
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_12900936431479:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 192239
|
|
; RV64-REMAT-NEXT: slli a0, a0, 2
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1093
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1911
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 12900936431479
|
|
}
|
|
|
|
define i64 @imm_12900918536874() {
|
|
; RV32I-LABEL: imm_12900918536874:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 764587
|
|
; RV32I-NEXT: lui a1, 1
|
|
; RV32I-NEXT: addi a0, a0, -1366
|
|
; RV32I-NEXT: addi a1, a1, -1093
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_12900918536874:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1163220310
|
|
; RV32IXQCILI-NEXT: qc.li a1, 3003
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_12900918536874:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 384477
|
|
; RV64I-NEXT: addi a0, a0, 1365
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, 1365
|
|
; RV64I-NEXT: slli a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_12900918536874:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 768955
|
|
; RV64IZBA-NEXT: addi a0, a0, -1365
|
|
; RV64IZBA-NEXT: slli.uw a0, a0, 12
|
|
; RV64IZBA-NEXT: addi a0, a0, -1366
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_12900918536874:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 384477
|
|
; RV64IZBB-NEXT: addi a0, a0, 1365
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, 1365
|
|
; RV64IZBB-NEXT: slli a0, a0, 1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_12900918536874:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 384477
|
|
; RV64IZBS-NEXT: addi a0, a0, 1365
|
|
; RV64IZBS-NEXT: slli a0, a0, 12
|
|
; RV64IZBS-NEXT: addi a0, a0, 1365
|
|
; RV64IZBS-NEXT: slli a0, a0, 1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_12900918536874:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 384477
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1365
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1365
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_12900918536874:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 764587
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1366
|
|
; RV32-REMAT-NEXT: lui a1, 1
|
|
; RV32-REMAT-NEXT: addi a1, a1, -1093
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_12900918536874:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 384477
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1365
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1365
|
|
; RV64-REMAT-NEXT: slli a0, a0, 1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 12900918536874
|
|
}
|
|
|
|
define i64 @imm_12900925247761() {
|
|
; RV32I-LABEL: imm_12900925247761:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 766225
|
|
; RV32I-NEXT: lui a1, 1
|
|
; RV32I-NEXT: addi a0, a0, 273
|
|
; RV32I-NEXT: addi a1, a1, -1093
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_12900925247761:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1156509423
|
|
; RV32IXQCILI-NEXT: qc.li a1, 3003
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_12900925247761:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 384478
|
|
; RV64I-NEXT: addi a0, a0, -1911
|
|
; RV64I-NEXT: slli a0, a0, 13
|
|
; RV64I-NEXT: addi a0, a0, -2048
|
|
; RV64I-NEXT: addi a0, a0, -1775
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_12900925247761:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 768955
|
|
; RV64IZBA-NEXT: addi a0, a0, 273
|
|
; RV64IZBA-NEXT: slli.uw a0, a0, 12
|
|
; RV64IZBA-NEXT: addi a0, a0, 273
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_12900925247761:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 384478
|
|
; RV64IZBB-NEXT: addi a0, a0, -1911
|
|
; RV64IZBB-NEXT: slli a0, a0, 13
|
|
; RV64IZBB-NEXT: addi a0, a0, -2048
|
|
; RV64IZBB-NEXT: addi a0, a0, -1775
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_12900925247761:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 384478
|
|
; RV64IZBS-NEXT: addi a0, a0, -1911
|
|
; RV64IZBS-NEXT: slli a0, a0, 13
|
|
; RV64IZBS-NEXT: addi a0, a0, -2048
|
|
; RV64IZBS-NEXT: addi a0, a0, -1775
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_12900925247761:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 384478
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1911
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 13
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -2048
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1775
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_12900925247761:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 766225
|
|
; RV32-REMAT-NEXT: addi a0, a0, 273
|
|
; RV32-REMAT-NEXT: lui a1, 1
|
|
; RV32-REMAT-NEXT: addi a1, a1, -1093
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_12900925247761:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 384478
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1911
|
|
; RV64-REMAT-NEXT: slli a0, a0, 13
|
|
; RV64-REMAT-NEXT: addi a0, a0, -2048
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1775
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 12900925247761
|
|
}
|
|
|
|
define i64 @imm_7158272001() {
|
|
; RV32I-LABEL: imm_7158272001:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 699049
|
|
; RV32I-NEXT: addi a0, a0, 1
|
|
; RV32I-NEXT: li a1, 1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_7158272001:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1431662591
|
|
; RV32IXQCILI-NEXT: li a1, 1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_7158272001:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 427
|
|
; RV64I-NEXT: addi a0, a0, -1367
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_7158272001:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 349525
|
|
; RV64IZBA-NEXT: sh2add a0, a0, a0
|
|
; RV64IZBA-NEXT: addi a0, a0, 1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_7158272001:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 427
|
|
; RV64IZBB-NEXT: addi a0, a0, -1367
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, 1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_7158272001:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 427
|
|
; RV64IZBS-NEXT: addi a0, a0, -1367
|
|
; RV64IZBS-NEXT: slli a0, a0, 12
|
|
; RV64IZBS-NEXT: addi a0, a0, 1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_7158272001:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 427
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1367
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_7158272001:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 699049
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1
|
|
; RV32-REMAT-NEXT: li a1, 1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_7158272001:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 427
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1367
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 7158272001 ; 0x0000_0001_aaaa_9001
|
|
}
|
|
|
|
define i64 @imm_12884889601() {
|
|
; RV32I-LABEL: imm_12884889601:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 1048573
|
|
; RV32I-NEXT: addi a0, a0, 1
|
|
; RV32I-NEXT: li a1, 2
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_12884889601:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.li a0, -12287
|
|
; RV32IXQCILI-NEXT: li a1, 2
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_12884889601:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 768
|
|
; RV64I-NEXT: addi a0, a0, -3
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_12884889601:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 349525
|
|
; RV64IZBA-NEXT: sh3add a0, a0, a0
|
|
; RV64IZBA-NEXT: addi a0, a0, 1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_12884889601:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 768
|
|
; RV64IZBB-NEXT: addi a0, a0, -3
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, 1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_12884889601:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 768
|
|
; RV64IZBS-NEXT: addi a0, a0, -3
|
|
; RV64IZBS-NEXT: slli a0, a0, 12
|
|
; RV64IZBS-NEXT: addi a0, a0, 1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_12884889601:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 768
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -3
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_12884889601:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 1048573
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1
|
|
; RV32-REMAT-NEXT: li a1, 2
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_12884889601:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 768
|
|
; RV64-REMAT-NEXT: addi a0, a0, -3
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 12884889601 ; 0x0000_0002_ffff_d001
|
|
}
|
|
|
|
define i64 @imm_neg_3435982847() {
|
|
; RV32I-LABEL: imm_neg_3435982847:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 209713
|
|
; RV32I-NEXT: addi a0, a0, 1
|
|
; RV32I-NEXT: li a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_3435982847:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 858984449
|
|
; RV32IXQCILI-NEXT: li a1, -1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_3435982847:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 1048371
|
|
; RV64I-NEXT: addi a0, a0, 817
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_3435982847:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 768955
|
|
; RV64IZBA-NEXT: sh1add a0, a0, a0
|
|
; RV64IZBA-NEXT: addi a0, a0, 1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_3435982847:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 1048371
|
|
; RV64IZBB-NEXT: addi a0, a0, 817
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, 1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_3435982847:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 734001
|
|
; RV64IZBS-NEXT: addi a0, a0, 1
|
|
; RV64IZBS-NEXT: bclri a0, a0, 31
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_3435982847:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 1048371
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 817
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_3435982847:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 209713
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1
|
|
; RV32-REMAT-NEXT: li a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_3435982847:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 1048371
|
|
; RV64-REMAT-NEXT: addi a0, a0, 817
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -3435982847 ; 0xffff_ffff_3333_1001
|
|
}
|
|
|
|
define i64 @imm_neg_5726842879() {
|
|
; RV32I-LABEL: imm_neg_5726842879:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 698997
|
|
; RV32I-NEXT: addi a0, a0, 1
|
|
; RV32I-NEXT: li a1, -2
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_5726842879:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1431875583
|
|
; RV32IXQCILI-NEXT: li a1, -2
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_5726842879:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 1048235
|
|
; RV64I-NEXT: addi a0, a0, -1419
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_5726842879:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 768945
|
|
; RV64IZBA-NEXT: sh2add a0, a0, a0
|
|
; RV64IZBA-NEXT: addi a0, a0, 1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_5726842879:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 1048235
|
|
; RV64IZBB-NEXT: addi a0, a0, -1419
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, 1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_5726842879:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 698997
|
|
; RV64IZBS-NEXT: addi a0, a0, 1
|
|
; RV64IZBS-NEXT: bclri a0, a0, 32
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_5726842879:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 1048235
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1419
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_5726842879:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 698997
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1
|
|
; RV32-REMAT-NEXT: li a1, -2
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_5726842879:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 1048235
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1419
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -5726842879 ; 0xffff_fffe_aaa7_5001
|
|
}
|
|
|
|
define i64 @imm_neg_10307948543() {
|
|
; RV32I-LABEL: imm_neg_10307948543:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 629139
|
|
; RV32I-NEXT: addi a0, a0, 1
|
|
; RV32I-NEXT: li a1, -3
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm_neg_10307948543:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -1718013951
|
|
; RV32IXQCILI-NEXT: li a1, -3
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_neg_10307948543:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 1047962
|
|
; RV64I-NEXT: addi a0, a0, -1645
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm_neg_10307948543:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 768955
|
|
; RV64IZBA-NEXT: sh3add a0, a0, a0
|
|
; RV64IZBA-NEXT: addi a0, a0, 1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm_neg_10307948543:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 1047962
|
|
; RV64IZBB-NEXT: addi a0, a0, -1645
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: addi a0, a0, 1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm_neg_10307948543:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 629139
|
|
; RV64IZBS-NEXT: addi a0, a0, 1
|
|
; RV64IZBS-NEXT: bclri a0, a0, 33
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm_neg_10307948543:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 1047962
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1645
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm_neg_10307948543:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 629139
|
|
; RV32-REMAT-NEXT: addi a0, a0, 1
|
|
; RV32-REMAT-NEXT: li a1, -3
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm_neg_10307948543:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 1047962
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1645
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -10307948543 ; 0xffff_fffd_9999_3001
|
|
}
|
|
|
|
define i64 @li_rori_1() {
|
|
; RV32I-LABEL: li_rori_1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 1048567
|
|
; RV32I-NEXT: addi a1, a0, 2047
|
|
; RV32I-NEXT: li a0, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: li_rori_1:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.li a1, -34817
|
|
; RV32IXQCILI-NEXT: li a0, -1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: li_rori_1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, -17
|
|
; RV64I-NEXT: slli a0, a0, 43
|
|
; RV64I-NEXT: addi a0, a0, -1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: li_rori_1:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, -17
|
|
; RV64IZBA-NEXT: slli a0, a0, 43
|
|
; RV64IZBA-NEXT: addi a0, a0, -1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: li_rori_1:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, -18
|
|
; RV64IZBB-NEXT: rori a0, a0, 21
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: li_rori_1:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, -17
|
|
; RV64IZBS-NEXT: slli a0, a0, 43
|
|
; RV64IZBS-NEXT: addi a0, a0, -1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: li_rori_1:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, -18
|
|
; RV64IXTHEADBB-NEXT: th.srri a0, a0, 21
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: li_rori_1:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a1, 1048567
|
|
; RV32-REMAT-NEXT: addi a1, a1, 2047
|
|
; RV32-REMAT-NEXT: li a0, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: li_rori_1:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, -17
|
|
; RV64-REMAT-NEXT: slli a0, a0, 43
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -149533581377537
|
|
}
|
|
|
|
define i64 @li_rori_2() {
|
|
; RV32I-LABEL: li_rori_2:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a1, 720896
|
|
; RV32I-NEXT: addi a1, a1, -1
|
|
; RV32I-NEXT: li a0, -6
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: li_rori_2:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a1, -1342177281
|
|
; RV32IXQCILI-NEXT: li a0, -6
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: li_rori_2:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, -5
|
|
; RV64I-NEXT: slli a0, a0, 60
|
|
; RV64I-NEXT: addi a0, a0, -6
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: li_rori_2:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, -5
|
|
; RV64IZBA-NEXT: slli a0, a0, 60
|
|
; RV64IZBA-NEXT: addi a0, a0, -6
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: li_rori_2:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, -86
|
|
; RV64IZBB-NEXT: rori a0, a0, 4
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: li_rori_2:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, -5
|
|
; RV64IZBS-NEXT: slli a0, a0, 60
|
|
; RV64IZBS-NEXT: addi a0, a0, -6
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: li_rori_2:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, -86
|
|
; RV64IXTHEADBB-NEXT: th.srri a0, a0, 4
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: li_rori_2:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a1, 720896
|
|
; RV32-REMAT-NEXT: addi a1, a1, -1
|
|
; RV32-REMAT-NEXT: li a0, -6
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: li_rori_2:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, -5
|
|
; RV64-REMAT-NEXT: slli a0, a0, 60
|
|
; RV64-REMAT-NEXT: addi a0, a0, -6
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -5764607523034234886
|
|
}
|
|
|
|
define i64 @li_rori_3() {
|
|
; RV32I-LABEL: li_rori_3:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 491520
|
|
; RV32I-NEXT: addi a0, a0, -1
|
|
; RV32I-NEXT: li a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: li_rori_3:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 2013265919
|
|
; RV32IXQCILI-NEXT: li a1, -1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: li_rori_3:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, -17
|
|
; RV64I-NEXT: slli a0, a0, 27
|
|
; RV64I-NEXT: addi a0, a0, -1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: li_rori_3:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, -17
|
|
; RV64IZBA-NEXT: slli a0, a0, 27
|
|
; RV64IZBA-NEXT: addi a0, a0, -1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: li_rori_3:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, -18
|
|
; RV64IZBB-NEXT: rori a0, a0, 37
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: li_rori_3:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, -17
|
|
; RV64IZBS-NEXT: slli a0, a0, 27
|
|
; RV64IZBS-NEXT: addi a0, a0, -1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: li_rori_3:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, -18
|
|
; RV64IXTHEADBB-NEXT: th.srri a0, a0, 37
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: li_rori_3:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 491520
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1
|
|
; RV32-REMAT-NEXT: li a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: li_rori_3:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, -17
|
|
; RV64-REMAT-NEXT: slli a0, a0, 27
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -2281701377
|
|
}
|
|
|
|
; This used to assert when compiled with Zba.
|
|
define i64 @PR54812() {
|
|
; RV32I-LABEL: PR54812:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 521599
|
|
; RV32I-NEXT: li a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: PR54812:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: lui a0, 521599
|
|
; RV32IXQCILI-NEXT: li a1, -1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: PR54812:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 1048447
|
|
; RV64I-NEXT: addi a0, a0, 1407
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: PR54812:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 872917
|
|
; RV64IZBA-NEXT: sh1add a0, a0, a0
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: PR54812:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 1048447
|
|
; RV64IZBB-NEXT: addi a0, a0, 1407
|
|
; RV64IZBB-NEXT: slli a0, a0, 12
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: PR54812:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 1045887
|
|
; RV64IZBS-NEXT: bclri a0, a0, 31
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: PR54812:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 1048447
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1407
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: PR54812:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 521599
|
|
; RV32-REMAT-NEXT: li a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: PR54812:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 1048447
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1407
|
|
; RV64-REMAT-NEXT: slli a0, a0, 12
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -2158497792;
|
|
}
|
|
|
|
define signext i32 @pos_2048() nounwind {
|
|
; RV32I-LABEL: pos_2048:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a0, 1
|
|
; RV32I-NEXT: slli a0, a0, 11
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: pos_2048:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.li a0, 2048
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: pos_2048:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, 1
|
|
; RV64I-NEXT: slli a0, a0, 11
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: pos_2048:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, 1
|
|
; RV64IZBA-NEXT: slli a0, a0, 11
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: pos_2048:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, 1
|
|
; RV64IZBB-NEXT: slli a0, a0, 11
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: pos_2048:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: bseti a0, zero, 11
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: pos_2048:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, 1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 11
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: pos_2048:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a0, 1
|
|
; RV32-REMAT-NEXT: slli a0, a0, 11
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: pos_2048:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, 1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 11
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i32 2048
|
|
}
|
|
|
|
define i64 @imm64_same_lo_hi() nounwind {
|
|
; RV32I-LABEL: imm64_same_lo_hi:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 65793
|
|
; RV32I-NEXT: addi a0, a0, 16
|
|
; RV32I-NEXT: mv a1, a0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_same_lo_hi:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 269488144
|
|
; RV32IXQCILI-NEXT: mv a1, a0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_same_lo_hi:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 65793
|
|
; RV64I-NEXT: addi a0, a0, 16
|
|
; RV64I-NEXT: slli a1, a0, 32
|
|
; RV64I-NEXT: add a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_same_lo_hi:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 65793
|
|
; RV64IZBA-NEXT: addi a0, a0, 16
|
|
; RV64IZBA-NEXT: slli a1, a0, 32
|
|
; RV64IZBA-NEXT: add a0, a0, a1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_same_lo_hi:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 65793
|
|
; RV64IZBB-NEXT: addi a0, a0, 16
|
|
; RV64IZBB-NEXT: slli a1, a0, 32
|
|
; RV64IZBB-NEXT: add a0, a0, a1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_same_lo_hi:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 65793
|
|
; RV64IZBS-NEXT: addi a0, a0, 16
|
|
; RV64IZBS-NEXT: slli a1, a0, 32
|
|
; RV64IZBS-NEXT: add a0, a0, a1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_same_lo_hi:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 65793
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 16
|
|
; RV64IXTHEADBB-NEXT: slli a1, a0, 32
|
|
; RV64IXTHEADBB-NEXT: add a0, a0, a1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_same_lo_hi:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 65793
|
|
; RV32-REMAT-NEXT: addi a0, a0, 16
|
|
; RV32-REMAT-NEXT: mv a1, a0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_same_lo_hi:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 65793
|
|
; RV64-REMAT-NEXT: addi a0, a0, 16
|
|
; RV64-REMAT-NEXT: slli a1, a0, 32
|
|
; RV64-REMAT-NEXT: add a0, a0, a1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 1157442765409226768 ; 0x0101010101010101
|
|
}
|
|
|
|
; Same as above with optsize. Make sure we use constant pool on RV64
|
|
define i64 @imm64_same_lo_hi_optsize() nounwind optsize {
|
|
; RV32I-LABEL: imm64_same_lo_hi_optsize:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 65793
|
|
; RV32I-NEXT: addi a0, a0, 16
|
|
; RV32I-NEXT: mv a1, a0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_same_lo_hi_optsize:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 269488144
|
|
; RV32IXQCILI-NEXT: mv a1, a0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64-NOPOOL-LABEL: imm64_same_lo_hi_optsize:
|
|
; RV64-NOPOOL: # %bb.0:
|
|
; RV64-NOPOOL-NEXT: lui a0, 65793
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, 16
|
|
; RV64-NOPOOL-NEXT: slli a1, a0, 32
|
|
; RV64-NOPOOL-NEXT: add a0, a0, a1
|
|
; RV64-NOPOOL-NEXT: ret
|
|
;
|
|
; RV64I-POOL-LABEL: imm64_same_lo_hi_optsize:
|
|
; RV64I-POOL: # %bb.0:
|
|
; RV64I-POOL-NEXT: lui a0, %hi(.LCPI65_0)
|
|
; RV64I-POOL-NEXT: ld a0, %lo(.LCPI65_0)(a0)
|
|
; RV64I-POOL-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_same_lo_hi_optsize:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 65793
|
|
; RV64IZBA-NEXT: addi a0, a0, 16
|
|
; RV64IZBA-NEXT: slli a1, a0, 32
|
|
; RV64IZBA-NEXT: add a0, a0, a1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_same_lo_hi_optsize:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 65793
|
|
; RV64IZBB-NEXT: addi a0, a0, 16
|
|
; RV64IZBB-NEXT: slli a1, a0, 32
|
|
; RV64IZBB-NEXT: add a0, a0, a1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_same_lo_hi_optsize:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 65793
|
|
; RV64IZBS-NEXT: addi a0, a0, 16
|
|
; RV64IZBS-NEXT: slli a1, a0, 32
|
|
; RV64IZBS-NEXT: add a0, a0, a1
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_same_lo_hi_optsize:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 65793
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 16
|
|
; RV64IXTHEADBB-NEXT: slli a1, a0, 32
|
|
; RV64IXTHEADBB-NEXT: add a0, a0, a1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_same_lo_hi_optsize:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 65793
|
|
; RV32-REMAT-NEXT: addi a0, a0, 16
|
|
; RV32-REMAT-NEXT: mv a1, a0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_same_lo_hi_optsize:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 65793
|
|
; RV64-REMAT-NEXT: addi a0, a0, 16
|
|
; RV64-REMAT-NEXT: slli a1, a0, 32
|
|
; RV64-REMAT-NEXT: add a0, a0, a1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 1157442765409226768 ; 0x0101010101010101
|
|
}
|
|
|
|
; Hi and lo are the same and also negative.
|
|
define i64 @imm64_same_lo_hi_negative() nounwind {
|
|
; RV32I-LABEL: imm64_same_lo_hi_negative:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 526344
|
|
; RV32I-NEXT: addi a0, a0, 128
|
|
; RV32I-NEXT: mv a1, a0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_same_lo_hi_negative:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, -2139062144
|
|
; RV32IXQCILI-NEXT: mv a1, a0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64-NOPOOL-LABEL: imm64_same_lo_hi_negative:
|
|
; RV64-NOPOOL: # %bb.0:
|
|
; RV64-NOPOOL-NEXT: lui a0, 983297
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 4
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, 257
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 16
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, 257
|
|
; RV64-NOPOOL-NEXT: slli a0, a0, 15
|
|
; RV64-NOPOOL-NEXT: addi a0, a0, 128
|
|
; RV64-NOPOOL-NEXT: ret
|
|
;
|
|
; RV64I-POOL-LABEL: imm64_same_lo_hi_negative:
|
|
; RV64I-POOL: # %bb.0:
|
|
; RV64I-POOL-NEXT: lui a0, %hi(.LCPI66_0)
|
|
; RV64I-POOL-NEXT: ld a0, %lo(.LCPI66_0)(a0)
|
|
; RV64I-POOL-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_same_lo_hi_negative:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 526344
|
|
; RV64IZBA-NEXT: addi a0, a0, 128
|
|
; RV64IZBA-NEXT: slli a1, a0, 32
|
|
; RV64IZBA-NEXT: add.uw a0, a0, a1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_same_lo_hi_negative:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 983297
|
|
; RV64IZBB-NEXT: slli a0, a0, 4
|
|
; RV64IZBB-NEXT: addi a0, a0, 257
|
|
; RV64IZBB-NEXT: slli a0, a0, 16
|
|
; RV64IZBB-NEXT: addi a0, a0, 257
|
|
; RV64IZBB-NEXT: slli a0, a0, 15
|
|
; RV64IZBB-NEXT: addi a0, a0, 128
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_same_lo_hi_negative:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: lui a0, 983297
|
|
; RV64IZBS-NEXT: slli a0, a0, 4
|
|
; RV64IZBS-NEXT: addi a0, a0, 257
|
|
; RV64IZBS-NEXT: slli a0, a0, 16
|
|
; RV64IZBS-NEXT: addi a0, a0, 257
|
|
; RV64IZBS-NEXT: slli a0, a0, 15
|
|
; RV64IZBS-NEXT: addi a0, a0, 128
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_same_lo_hi_negative:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 983297
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 4
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 257
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 16
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 257
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 15
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 128
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_same_lo_hi_negative:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 526344
|
|
; RV32-REMAT-NEXT: addi a0, a0, 128
|
|
; RV32-REMAT-NEXT: mv a1, a0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_same_lo_hi_negative:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 983297
|
|
; RV64-REMAT-NEXT: slli a0, a0, 4
|
|
; RV64-REMAT-NEXT: addi a0, a0, 257
|
|
; RV64-REMAT-NEXT: slli a0, a0, 16
|
|
; RV64-REMAT-NEXT: addi a0, a0, 257
|
|
; RV64-REMAT-NEXT: slli a0, a0, 15
|
|
; RV64-REMAT-NEXT: addi a0, a0, 128
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 9259542123273814144 ; 0x8080808080808080
|
|
}
|
|
|
|
define i64 @imm64_0x8000080000000() {
|
|
; RV32I-LABEL: imm64_0x8000080000000:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 524288
|
|
; RV32I-NEXT: lui a1, 128
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_0x8000080000000:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: lui a0, 524288
|
|
; RV32IXQCILI-NEXT: lui a1, 128
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_0x8000080000000:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 256
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
; RV64I-NEXT: slli a0, a0, 31
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_0x8000080000000:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 256
|
|
; RV64IZBA-NEXT: addi a0, a0, 1
|
|
; RV64IZBA-NEXT: slli a0, a0, 31
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_0x8000080000000:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 256
|
|
; RV64IZBB-NEXT: addi a0, a0, 1
|
|
; RV64IZBB-NEXT: slli a0, a0, 31
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_0x8000080000000:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: bseti a0, zero, 31
|
|
; RV64IZBS-NEXT: bseti a0, a0, 51
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_0x8000080000000:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 256
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 31
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_0x8000080000000:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 524288
|
|
; RV32-REMAT-NEXT: lui a1, 128
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_0x8000080000000:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 256
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 31
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 2251801961168896 ; 0x8000080000000
|
|
}
|
|
|
|
define i64 @imm64_0x10000100000000() {
|
|
; RV32I-LABEL: imm64_0x10000100000000:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a1, 256
|
|
; RV32I-NEXT: addi a1, a1, 1
|
|
; RV32I-NEXT: li a0, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_0x10000100000000:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a1, 1048577
|
|
; RV32IXQCILI-NEXT: li a0, 0
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_0x10000100000000:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 256
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_0x10000100000000:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 256
|
|
; RV64IZBA-NEXT: addi a0, a0, 1
|
|
; RV64IZBA-NEXT: slli a0, a0, 32
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_0x10000100000000:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 256
|
|
; RV64IZBB-NEXT: addi a0, a0, 1
|
|
; RV64IZBB-NEXT: slli a0, a0, 32
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_0x10000100000000:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: bseti a0, zero, 32
|
|
; RV64IZBS-NEXT: bseti a0, a0, 52
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_0x10000100000000:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 256
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, 1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 32
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_0x10000100000000:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a1, 256
|
|
; RV32-REMAT-NEXT: addi a1, a1, 1
|
|
; RV32-REMAT-NEXT: li a0, 0
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_0x10000100000000:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 256
|
|
; RV64-REMAT-NEXT: addi a0, a0, 1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 32
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 4503603922337792 ; 0x10000100000000
|
|
}
|
|
|
|
define i64 @imm64_0xFF7FFFFF7FFFFFFE() {
|
|
; RV32I-LABEL: imm64_0xFF7FFFFF7FFFFFFE:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 524288
|
|
; RV32I-NEXT: lui a1, 1046528
|
|
; RV32I-NEXT: addi a0, a0, -1
|
|
; RV32I-NEXT: addi a1, a1, -1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_0xFF7FFFFF7FFFFFFE:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: qc.e.li a0, 2147483647
|
|
; RV32IXQCILI-NEXT: qc.e.li a1, -8388609
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_0xFF7FFFFF7FFFFFFE:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, 1044480
|
|
; RV64I-NEXT: addi a0, a0, -1
|
|
; RV64I-NEXT: slli a0, a0, 31
|
|
; RV64I-NEXT: addi a0, a0, -1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_0xFF7FFFFF7FFFFFFE:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: lui a0, 1044480
|
|
; RV64IZBA-NEXT: addi a0, a0, -1
|
|
; RV64IZBA-NEXT: slli a0, a0, 31
|
|
; RV64IZBA-NEXT: addi a0, a0, -1
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_0xFF7FFFFF7FFFFFFE:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: lui a0, 1044480
|
|
; RV64IZBB-NEXT: addi a0, a0, -1
|
|
; RV64IZBB-NEXT: slli a0, a0, 31
|
|
; RV64IZBB-NEXT: addi a0, a0, -1
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_0xFF7FFFFF7FFFFFFE:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: li a0, -1
|
|
; RV64IZBS-NEXT: bclri a0, a0, 31
|
|
; RV64IZBS-NEXT: bclri a0, a0, 55
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_0xFF7FFFFF7FFFFFFE:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: lui a0, 1044480
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 31
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -1
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_0xFF7FFFFF7FFFFFFE:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: lui a0, 524288
|
|
; RV32-REMAT-NEXT: addi a0, a0, -1
|
|
; RV32-REMAT-NEXT: lui a1, 1046528
|
|
; RV32-REMAT-NEXT: addi a1, a1, -1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_0xFF7FFFFF7FFFFFFE:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: lui a0, 1044480
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 31
|
|
; RV64-REMAT-NEXT: addi a0, a0, -1
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 -36028799166447617 ; 0xFF7FFFFF7FFFFFFE
|
|
}
|
|
|
|
define i64 @imm64_0xFFFFFFFF0() {
|
|
; RV32I-LABEL: imm64_0xFFFFFFFF0:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a0, -16
|
|
; RV32I-NEXT: li a1, 15
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_0xFFFFFFFF0:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a0, -16
|
|
; RV32IXQCILI-NEXT: li a1, 15
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_0xFFFFFFFF0:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, 1
|
|
; RV64I-NEXT: slli a0, a0, 36
|
|
; RV64I-NEXT: addi a0, a0, -16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_0xFFFFFFFF0:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, 1
|
|
; RV64IZBA-NEXT: slli a0, a0, 36
|
|
; RV64IZBA-NEXT: addi a0, a0, -16
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_0xFFFFFFFF0:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, 1
|
|
; RV64IZBB-NEXT: slli a0, a0, 36
|
|
; RV64IZBB-NEXT: addi a0, a0, -16
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_0xFFFFFFFF0:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: bseti a0, zero, 36
|
|
; RV64IZBS-NEXT: addi a0, a0, -16
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_0xFFFFFFFF0:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, 1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 36
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -16
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_0xFFFFFFFF0:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a0, -16
|
|
; RV32-REMAT-NEXT: li a1, 15
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_0xFFFFFFFF0:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, 1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 36
|
|
; RV64-REMAT-NEXT: addi a0, a0, -16
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 68719476720 ; 0xFFFFFFFF0
|
|
}
|
|
|
|
define i64 @imm64_0x1FFFFFF08() {
|
|
; RV32I-LABEL: imm64_0x1FFFFFF08:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: li a0, -248
|
|
; RV32I-NEXT: li a1, 1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IXQCILI-LABEL: imm64_0x1FFFFFF08:
|
|
; RV32IXQCILI: # %bb.0:
|
|
; RV32IXQCILI-NEXT: li a0, -248
|
|
; RV32IXQCILI-NEXT: li a1, 1
|
|
; RV32IXQCILI-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm64_0x1FFFFFF08:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: li a0, 1
|
|
; RV64I-NEXT: slli a0, a0, 33
|
|
; RV64I-NEXT: addi a0, a0, -248
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IZBA-LABEL: imm64_0x1FFFFFF08:
|
|
; RV64IZBA: # %bb.0:
|
|
; RV64IZBA-NEXT: li a0, 1
|
|
; RV64IZBA-NEXT: slli a0, a0, 33
|
|
; RV64IZBA-NEXT: addi a0, a0, -248
|
|
; RV64IZBA-NEXT: ret
|
|
;
|
|
; RV64IZBB-LABEL: imm64_0x1FFFFFF08:
|
|
; RV64IZBB: # %bb.0:
|
|
; RV64IZBB-NEXT: li a0, 1
|
|
; RV64IZBB-NEXT: slli a0, a0, 33
|
|
; RV64IZBB-NEXT: addi a0, a0, -248
|
|
; RV64IZBB-NEXT: ret
|
|
;
|
|
; RV64IZBS-LABEL: imm64_0x1FFFFFF08:
|
|
; RV64IZBS: # %bb.0:
|
|
; RV64IZBS-NEXT: bseti a0, zero, 33
|
|
; RV64IZBS-NEXT: addi a0, a0, -248
|
|
; RV64IZBS-NEXT: ret
|
|
;
|
|
; RV64IXTHEADBB-LABEL: imm64_0x1FFFFFF08:
|
|
; RV64IXTHEADBB: # %bb.0:
|
|
; RV64IXTHEADBB-NEXT: li a0, 1
|
|
; RV64IXTHEADBB-NEXT: slli a0, a0, 33
|
|
; RV64IXTHEADBB-NEXT: addi a0, a0, -248
|
|
; RV64IXTHEADBB-NEXT: ret
|
|
;
|
|
; RV32-REMAT-LABEL: imm64_0x1FFFFFF08:
|
|
; RV32-REMAT: # %bb.0:
|
|
; RV32-REMAT-NEXT: li a0, -248
|
|
; RV32-REMAT-NEXT: li a1, 1
|
|
; RV32-REMAT-NEXT: ret
|
|
;
|
|
; RV64-REMAT-LABEL: imm64_0x1FFFFFF08:
|
|
; RV64-REMAT: # %bb.0:
|
|
; RV64-REMAT-NEXT: li a0, 1
|
|
; RV64-REMAT-NEXT: slli a0, a0, 33
|
|
; RV64-REMAT-NEXT: addi a0, a0, -248
|
|
; RV64-REMAT-NEXT: ret
|
|
ret i64 8589934344 ; 0x1FFFFFF08
|
|
}
|