3d2650bdeb
The logic in RISCVMatInt would previously produce lui+addiw on RV64 whenever a 32-bit integer must be materialised and the Hi20 and Lo12 parts are non-zero. However, sometimes addi can be used equivalently (whenever the sign extension behaviour of addiw would be a no-op). This patch moves to using addiw only when necessary. Although there is absolutely no advantage in terms of compressibility or performance, this has the following advantages: * It's more consistent with logic used elsewhere in the backend. For instance, RISCVOptWInstrs will try to convert addiw to addi on the basis it reduces test diffs vs RV32. * This matches the lowering GCC does in its codegen path. Unlike LLVM, GCC seems to have different expansion logic for the assembler vs codegen. For codegen it will use lui+addi if possible, but expanding `li` in the assembler will always produces lui+addiw as LLVM did prior to this commit. As someone who has been looking at a lot of gcc vs clang diffs lately, reducing unnecessary divergence is of at least some value. * As the diff for fold-mem-offset.ll shows, we can fold memory offsets in more cases when addi is used. Memory offset folding could be taught to recognise when the addiw could be replaced with an addi, but that seems unnecessary when we can simply change the logic in RISCVMatInt. As pointed out by @topperc during review, making this change without modifying RISCVOptWInstrs risks introducing some cases where we fail to remove a sext.w that we removed before. I've incorporated a patch based on a suggestion from Craig that avoids it, and also adds appropriate RISCVOptWInstrs test cases. The initial patch description noted that the main motivation was to avoid unnecessary differences both for RV32/RV64 and when comparing GCC, but noted that very occasionally we see a benefit from memory offset folding kicking in when it didn't before. Looking at the dynamic instruction count difference for SPEC benchmarks targeting rva22u64 and it shows we actually get a meaningful ~4.3% reduction in dynamic icount for 519.lbm_r. Looking at the data more closely, the codegen difference is in `LBM_performStreamCollideTRT` which as a function accounts for ~98% for dynamically executed instructions and the codegen diffs appear to be a knock-on effect of the address merging reducing register pressure right from function entry (for instance, we get a big reduction in dynamically executed loads in that function). Below is the icount data (rva22u64 -O3, no LTO): ``` Benchmark Baseline This PR Diff (%) ============================================================ 500.perlbench_r 174116601991 174115795810 -0.00% 502.gcc_r 218903280858 218903215788 -0.00% 505.mcf_r 131208029185 131207692803 -0.00% 508.namd_r 217497594322 217497594297 -0.00% 510.parest_r 289314486153 289313577652 -0.00% 511.povray_r 30640531048 30640765701 0.00% 519.lbm_r 95897914862 91712688050 -4.36% 520.omnetpp_r 134641549722 134867015683 0.17% 523.xalancbmk_r 281462762992 281432092673 -0.01% 525.x264_r 379776121941 379535558210 -0.06% 526.blender_r 659736022025 659738387343 0.00% 531.deepsjeng_r 349122867552 349122867481 -0.00% 538.imagick_r 238558760552 238558753269 -0.00% 541.leela_r 406578560612 406385135260 -0.05% 544.nab_r 400997131674 400996765827 -0.00% 557.xz_r 130079522194 129945515709 -0.10% ``` The instcounting setup I use doesn't have good support for drilling down into functions from outside the linked executable (e.g. libc). The difference in omnetpp all seems to come from there, and does not reflect any degradation in codegen quality. I can confirm with the current version of the PR there is no change in the number of static sext.w across all the SPEC 2017 benchmarks (rva22u64 O3) Co-authored-by: Craig Topper <craig.topper@sifive.com>
82 lines
3.2 KiB
YAML
82 lines
3.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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# REQUIRES: asserts
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# RUN: llc -mtriple riscv64 -start-before=prologepilog -o - \
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# RUN: -verify-machineinstrs %s | FileCheck %s
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#
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# RUN: llc -mtriple riscv64 -start-before=prologepilog -o /dev/null \
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# RUN: -debug-only=prologepilog -verify-machineinstrs %s 2>&1 \
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# RUN: | FileCheck --check-prefix=DEBUG %s
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#
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# DEBUG: Adjusting emergency spill slots!
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# DEBUG: Adjusting offset of emergency spill slot #4 from -4112 to -8192
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# FIXME: The code generated here is incorrect. It stores a0 to 0(sp) before
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# sub sp, sp, a0 but restores it after sub sp, sp, a0. We may need to implement
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# the target hook saveScavengerRegister to solve it.
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--- |
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; ModuleID = 'reduced.ll'
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source_filename = "frame_layout-1253b1.cpp"
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64"
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; Function Attrs: nounwind
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define weak_odr dso_local void @foo(ptr %ay) nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi sp, sp, -2032
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; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
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; CHECK-NEXT: addi s0, sp, 2032
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; CHECK-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
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; CHECK-NEXT: lui a0, 2
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; CHECK-NEXT: addi a0, a0, -2032
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; CHECK-NEXT: sub sp, sp, a0
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; CHECK-NEXT: srli a0, sp, 12
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; CHECK-NEXT: slli sp, a0, 12
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; CHECK-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
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; CHECK-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
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; CHECK-NEXT: lui a1, 1
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; CHECK-NEXT: add a1, sp, a1
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; CHECK-NEXT: sd a0, -8(a1)
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; CHECK-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
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; CHECK-NEXT: call foo
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; CHECK-NEXT: addi sp, s0, -2032
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; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 2032
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; CHECK-NEXT: ret
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entry:
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ret void
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}
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...
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---
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name: foo
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alignment: 2
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tracksRegLiveness: false
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frameInfo:
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maxAlignment: 4096
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stack:
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- { id: 0, size: 8, alignment: 4096 }
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- { id: 1, type: spill-slot, size: 8, alignment: 8 }
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31
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; This is to store something to the (non-emergency) spill slot %stack.1.
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SD $x10, %stack.1, 0
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; This is here just to make all the eligible registers live at this point.
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; This way when we replace the frame index %stack.1 with its actual address
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; we have to allocate a virtual register to compute it.
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; A later run of the the register scavenger won't find an available register
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; either so it will have to spill one to the emergency spill slot.
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PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
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PseudoRET
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...
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## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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# DEBUG: {{.*}}
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