shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel
History
Jun Wang ce7851f6b7
[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and GFX10 (#142188) 
In GFX9 and GFX10, the op_sel modifier should be allowed in the
instructions v_align_bit_b32 and v_alignbyte_b32.
2025-07-08 17:06:18 -07:00
..
add_shl.ll
[GlobalISel] Implement commuting shl (add/or x, c1), c2 -> add/or (shl x, c2), c1 << c2
2023-05-08 22:37:43 -07:00
add.v2i16.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
add.vni16.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
addo.ll
[AMDGPU] Add identity_combines to RegBankCombiner (#131305)
2025-03-17 10:11:28 +01:00
addsubu64.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
amdgpu-irtranslator.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
amdgpu-prelegalizer-combiner-crash.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
and.ll
[GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (#138574)
2025-05-08 19:31:28 +02:00
andn2.i1.ll
AMDGPU/GlobalISel: Add test showing s_andn2_b32/b64 is not formed from booleans (#115537)
2024-11-08 13:09:58 -08:00
andn2.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
artifact-combiner-anyext.mir
…
artifact-combiner-asserts.ll
AMDGPU/GlobalISel: Run redundant_and combine in RegBankCombiner (#112353)
2024-10-16 09:43:16 +02:00
artifact-combiner-build-vector.mir
…
artifact-combiner-concat-vectors.mir
…
artifact-combiner-cse-leaves-dead-cast.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
artifact-combiner-extract.mir
…
artifact-combiner-sext.mir
…
artifact-combiner-trunc.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
artifact-combiner-unmerge-values.mir
[GlobalISel] Combine unmerge(unmerge()) if the result is legal. (#109606)
2024-09-25 07:04:09 +01:00
artifact-combiner-zext.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
ashr.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
assert-align.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
atomic_load_flat.ll
GlobalISel: Fix combine duplicating atomic loads (#111730)
2024-10-31 07:55:12 -07:00
atomic_load_global.ll
GlobalISel: Fix combine duplicating atomic loads (#111730)
2024-10-31 07:55:12 -07:00
atomic_load_local_2.ll
GlobalISel: Fix combine duplicating atomic loads (#111730)
2024-10-31 07:55:12 -07:00
atomic_load_local.ll
…
atomic_optimizations_mul_one.ll
[GlobalISel] Combine G_MERGE_VALUES of x and zero (#116283)
2024-11-16 08:00:21 +01:00
atomic_store_local.ll
…
atomicrmw_fmax.ll
[PHIElimination] Revert #131837 #146320 #146337 (#146850)
2025-07-03 07:48:08 -04:00
atomicrmw_fmin.ll
[PHIElimination] Revert #131837 #146320 #146337 (#146850)
2025-07-03 07:48:08 -04:00
atomicrmw_udec_wrap.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
atomicrmw_uinc_wrap.ll
[AMDGPU] Fix bad removal of s_delay_alu (#145728)
2025-06-27 16:15:10 +02:00
bitcast_38_i16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
bool-legalization.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
br-constant-invalid-sgpr-copy.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
bswap.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
buffer-atomic-fadd.f32-no-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-atomic-fadd.f32-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-atomic-fadd.f64.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
buffer-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-atomic-fadd.v2f16-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-load-store-pointers.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
buffer-schedule.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
bug_shuffle_vector_to_scalar.ll
[GISel] Fix ShuffleVector assert (#139769)
2025-05-20 21:25:31 -04:00
bug-legalization-artifact-combiner-dead-def.ll
AMDGPU: Replace tests using undef in shufflevector with poison (#130899)
2025-03-12 20:45:02 +07:00
bug-legalization-artifact-combiner-dead-def.mir
…
call-outgoing-stack-args.ll
AMDGPU: Replace some test undef uses with poison (#131103)
2025-03-14 09:56:47 +07:00
clamp-fmed3-const-combine.ll
[AMDGPU][True16][CodeGen] add -real-true16 flag to a few gisel gfx12 test (#141503)
2025-05-27 09:58:27 -04:00
clamp-minmax-const-combine.ll
[AMDGPU][True16][CodeGen] add -real-true16 flag to a few gisel gfx12 test (#141503)
2025-05-27 09:58:27 -04:00
combine-add-nullptr.mir
…
combine-add-to-ptradd.mir
…
combine-amdgpu-cvt-f32-ubyte.mir
Revert "[GlobalISel] Combine [s,z]ext of undef into 0" (#118746)
2024-12-05 07:48:20 +01:00
combine-ashr-narrow.mir
…
combine-ext-legalizer.mir
…
combine-extract-vector-load.mir
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
combine-fabs-fneg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fcanonicalize.mir
[GlobalISel] Handle more commutable instructions in commute_constant_to_rhs
2024-04-16 02:36:12 -04:00
combine-fdiv-sqrt-to-rsq.mir
[AMDGPU][GlobalISel] Add fdiv / sqrt to rsq combine (#78673)
2024-02-22 09:47:36 +01:00
combine-fma-add-ext-fma.ll
AMDGPU/GlobalISel: Fix isExtractHiElt when selecting fma_mix (#102130)
2024-08-07 12:13:39 +02:00
combine-fma-add-ext-mul.ll
[AMDGPU][GlobalISel] Align selectVOP3PMadMixModsImpl with the SelectionDAG counterpart (#110168)
2024-10-08 09:41:24 -04:00
combine-fma-add-fma-mul.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
combine-fma-add-mul-post-legalize.mir
[AArch64][AMDGPU][GlobalISel] Remove vector handling from unmerge_dead_to_trunc (#82224)
2024-02-20 10:54:44 +00:00
combine-fma-add-mul-pre-legalize.mir
[AArch64][AMDGPU][GlobalISel] Remove vector handling from unmerge_dead_to_trunc (#82224)
2024-02-20 10:54:44 +00:00
combine-fma-add-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-sub-ext-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-sub-ext-neg-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-sub-mul.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
combine-fma-sub-neg-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-unmerge-values.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fold-binop-into-select.mir
[GlobalIsel] Combine selects with constants (#76089)
2024-01-02 17:26:39 +01:00
combine-foldable-fneg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fpneg-one-fneg.mir
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
combine-fsh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fsub-fneg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-itofp.mir
[GlobalIsel] Combine trunc of binop (#107721)
2024-09-11 15:04:55 +02:00
combine-lshr-narrow.mir
[GlobalISel] Combine G_MERGE_VALUES of x and zero (#116283)
2024-11-16 08:00:21 +01:00
combine-or-redundant.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-redundant-and.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-redundant-neg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-redundant-sext-inreg.mir
[GlobalISel] Combine redundant sext_inreg (#131624)
2025-04-14 11:48:08 +02:00
combine-rot.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-rsq.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-rsq.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-sext-inreg.mir
…
combine-sext-trunc-sextinreg.mir
[GlobalISel] Combine redundant sext_inreg (#131624)
2025-04-14 11:48:08 +02:00
combine-shift-amount-zext.mir
[AMDGPU] Canonicalize G_ZEXT of the shift amount in RegBankCombiner (#131792)
2025-05-14 10:48:51 +02:00
combine-shift-imm-chain-illegal-types.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-shift-imm-chain-shlsat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-shift-imm-chain.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-shift-of-shifted-logic-shlsat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-shift-of-shifted-logic.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-shifts.mir
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
combine-shl-from-extend-narrow.postlegal.mir
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
combine-shl-from-extend-narrow.prelegal.mir
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
combine-shl-narrow.mir
…
combine-short-clamp.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
combine-trunc-sext.mir
[AMDGPU] Add sext_trunc in RegBankCombiner (#131623)
2025-04-14 10:15:29 +02:00
combine-trunc-shift.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-urem-pow-2.mir
…
combine-zext-trunc.mir
[GlobalIsel] Combine trunc of binop (#107721)
2024-09-11 15:04:55 +02:00
combiner-crash.ll
…
compute-num-sign-bits-med3.mir
AMDGPU: Implement known bits functions for min3/max3/med3
2023-06-10 10:58:44 -04:00
constant-bus-restriction.ll
…
crash-stack-address-O0.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
cvt_f32_ubyte.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
dereferenceable-declaration.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
divergence-divergent-i1-phis-no-lane-mask-merging.ll
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-divergent-i1-phis-no-lane-mask-merging.mir
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-divergent-i1-used-outside-loop.ll
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-divergent-i1-used-outside-loop.mir
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-structurizer.ll
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-structurizer.mir
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-temporal-divergent-i1.ll
[PHIElimination] Revert #131837 #146320 #146337 (#146850)
2025-07-03 07:48:08 -04:00
divergence-temporal-divergent-i1.mir
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-temporal-divergent-reg.ll
AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)
2025-03-12 12:09:37 +01:00
divergence-temporal-divergent-reg.mir
AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)
2025-03-12 12:09:37 +01:00
divergent-control-flow.ll
[AMDGPU] Move InferAddressSpacesPass to middle end optimization pipeline (#138604)
2025-05-29 17:20:56 -04:00
dropped_debug_info_assert.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
dummy-target.ll
…
dynamic-alloca-uniform.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
extractelement-stack-lower.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
extractelement.i8.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
extractelement.i16.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
extractelement.i128.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
extractelement.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
fdiv.f16.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
fdiv.f32.ll
Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)
2025-03-13 10:26:20 +01:00
fdiv.f64.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
flat-atomic-fadd.f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
flat-atomic-fadd.f64.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
flat-atomic-fadd.v2f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
flat-scratch-init.gfx.ll
AMDGPU/GlobalISel: Permit mapping G_FRAME_INDEX to sgprs (#101325)
2024-08-01 09:42:04 +04:00
flat-scratch-init.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
flat-scratch.ll
[SeparateConstOffsetFromGEP] Don't set unsound inbounds flag (#130616)
2025-03-18 12:30:20 +01:00
floor.f64.ll
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
fma.ll
[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)
2025-02-19 11:37:24 -05:00
fmamix-constant-bus-violation.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fmamix-constant-bus-violation.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
fmax_legacy.ll
AMDGPU: Replace ptr addrspace(3) undef in tests with poison (#131049)
2025-03-13 13:28:55 +07:00
fmed3-min-max-const-combine.ll
[AMDGPU][True16][CodeGen] add -real-true16 flag to a few gisel gfx12 test (#141503)
2025-05-27 09:58:27 -04:00
fmin_legacy.ll
AMDGPU: Replace ptr addrspace(3) undef in tests with poison (#131049)
2025-03-13 13:28:55 +07:00
fmul.v2f16.ll
[AMDGPU] Re-Re-apply: Implement vop3p complex pattern optmization for gisel (#146984)
2025-07-08 15:10:44 +08:00
fp64-atomics-gfx90a.ll
AMDGPU: Replace ptr undef in tests with poison (#131050)
2025-03-13 13:34:52 +07:00
fp-atomics-gfx942.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
fpow.ll
[AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (#128905)
2025-02-26 23:55:29 +07:00
frem.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fshl.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
fshr.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
function-returns.ll
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
function-returns.v2i65.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
global-atomic-fadd.f32-no-rtn.ll
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
global-atomic-fadd.f32-rtn.ll
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
global-atomic-fadd.f64.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
global-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-atomic-fadd.v2f16-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-value.illegal.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
global-value.ll
[AMDGPU] Tweak handling of GlobalAddress operands in SI_PC_ADD_REL_OFFSET (#70960)
2023-11-01 19:48:30 +00:00
hip.extern.shared.array.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
i1-copy.ll
AMDGPU: Replace some float undef test uses with poison (#131090)
2025-03-13 20:07:48 +07:00
image-waterfall-loop-O0.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
implicit-kernarg-backend-usage-global-isel.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
inline-asm-mismatched-size.ll
Revert "[GlobalISel] Diagnose inline assembly constraint lowering errors (#135782)"
2025-05-07 14:50:45 +02:00
inline-asm.ll
…
insertelement-stack-lower.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
insertelement.i8.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
insertelement.i16.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
insertelement.large.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
insertelement.ll
Reland: [GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements (#144661)
2025-06-18 13:04:24 +02:00
inst-select-abs.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-add.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-add.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-amdgcn.class.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.class.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cos.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cos.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cvt.pk.i16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cvt.pk.u16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cvt.pknorm.i16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cvt.pknorm.u16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cvt.pkrtz.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.ds.swizzle.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.exp.compr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.exp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fcmp.constants.w32.mir
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00
inst-select-amdgcn.fcmp.constants.w64.mir
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00
inst-select-amdgcn.fmad.ftz.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fmed3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fmed3.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fract.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fract.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.groupstaticsize.mir
…
inst-select-amdgcn.mbcnt.lo.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.mul.u24.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.mulhi.i24.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.mulhi.u24.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rcp.legacy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rcp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rcp.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.readfirstlane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
inst-select-amdgcn.reloc.constant.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rsq.clamp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rsq.legacy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rsq.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rsq.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.s.barrier.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.s.sendmsg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.sffbh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.sin.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.sin.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgpu-atomic-cmpxchg-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgpu-atomic-cmpxchg-global.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-amdgpu-ffbh-u32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgpu-ffbl-b32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgpu-wave-address.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-and.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-anyext.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-ashr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ashr.s16.mir
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
inst-select-ashr.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomic-cmpxchg-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomic-cmpxchg-region.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-add-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-add-global.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-fadd-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-fadd-region.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-xchg-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-xchg-region.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-bitcast.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-bitreverse.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-br.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-brcond.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
inst-select-bswap.mir
[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and GFX10 (#142188)
2025-07-08 17:06:18 -07:00
inst-select-build-vector-trunc.v2s16.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-build-vector.mir
…
inst-select-concat-vectors.mir
…
inst-select-constant.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-copy.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-ctlz-zero-undef.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ctpop.mir
[TableGen][GISel] Import more "multi-level" patterns (#120332)
2024-12-18 14:44:55 +03:00
inst-select-cttz-zero-undef.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-extract-vector-elt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-extract.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fabs.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fadd.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fadd.s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fadd.s64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fcanonicalize.mir
[AMDGPU][True16][CodeGen] true16 codegen pattern for f16 canonicalize (#122000)
2025-01-24 10:44:00 -05:00
inst-select-fceil.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fceil.s16.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-fcmp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fcmp.s16.gfx11plus-fake16.mir
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
2025-02-04 11:20:40 -05:00
inst-select-fcmp.s16.gfx11plus.mir
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
2025-02-04 11:20:40 -05:00
inst-select-fcmp.s16.mir
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
2025-02-04 11:20:40 -05:00
inst-select-fconstant.mir
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
inst-select-fexp2.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ffloor.s16.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-ffloor.s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ffloor.s64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fma.s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmad.s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmaxnum-ieee.mir
…
inst-select-fmaxnum-ieee.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fmaxnum-ieee.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmaxnum.mir
…
inst-select-fmaxnum.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fmaxnum.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fminnum-ieee.mir
…
inst-select-fminnum-ieee.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fminnum-ieee.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fminnum.mir
…
inst-select-fminnum.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fminnum.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmul.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmul.v2s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fneg.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fptosi.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-fptoui.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-fract.f64.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-frame-index.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-freeze.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fshr.mir
[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and GFX10 (#142188)
2025-07-08 17:06:18 -07:00
inst-select-i1-copy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-icmp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-icmp.s16.mir
[AMDGPU][True16][CodeGen] gisel true16 for ICMP (#128913)
2025-03-13 12:03:17 -04:00
inst-select-icmp.s64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-implicit-def.mir
…
inst-select-insert-vector-elt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-insert.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-intrinsic-trunc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-intrinsic-trunc.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-inttoptr.mir
…
inst-select-load-atomic-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-atomic-global.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-atomic-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-constant.mir
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
inst-select-load-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-global-old-legalization.mir
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
inst-select-load-global-saddr.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-load-global.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-global.s96.mir
[AMDGPU] Regenerate checks in inst-select-load-global.s96.mir
2024-05-30 14:02:15 +01:00
inst-select-load-local-128.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-local.mir
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
inst-select-load-private.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-smrd.mir
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
inst-select-lshr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-lshr.s16.mir
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
inst-select-lshr.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-mad_64_32.mir
[AMDGPU] Disable V_MAD_U64_U32/V_MAD_I64_I32 workaround for GFX11.5 (#79460)
2024-01-25 16:28:49 +00:00
inst-select-merge-values.mir
…
inst-select-mul.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-or.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-pattern-add3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-and-or.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-or3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-smed3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-smed3.s16.mir
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
inst-select-pattern-umed3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-umed3.s16.mir
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
inst-select-pattern-xor3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-phi.mir
AMDGPU\GlobalISel: remove amdgpu-global-isel-risky-select flag (#83426)
2024-02-29 15:38:54 +01:00
inst-select-pseudo-scalar-transcendental.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ptr-add.mir
[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)
2024-07-28 11:26:29 +04:00
inst-select-ptrmask.mir
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
inst-select-ptrtoint.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-returnaddress.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-sbfx.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-scalar-float-sop1.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
inst-select-scalar-float-sop2.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
inst-select-scalar-float-sopc.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
inst-select-scalar-packed.xfail.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-select.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-sext-inreg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-sext.mir
[TableGen][GISel] Extract helper function for constraining operands (#115148)
2024-11-07 07:16:54 +03:00
inst-select-sextload-local.mir
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
inst-select-shl.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-shl.s16.mir
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
inst-select-shl.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-sitofp.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-smax.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-smin.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-smulh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-stacksave-stackrestore.invalid.mir
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
inst-select-stacksave-stackrestore.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-atomic-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-atomic-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-global.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-global.s96.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-private.mir
[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)
2024-07-28 11:26:29 +04:00
inst-select-sub.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-trunc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-trunc.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-uadde.gfx10.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-uadde.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-uaddo.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ubfx.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-uitofp.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-umax.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-umin.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-umulh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-unmerge-values.mir
[AMDGPU] Fix failing test after #109958 (#109964)
2024-09-25 15:02:23 +02:00
inst-select-usube.gfx10.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-usube.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-usubo.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-xor.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-zext.mir
[TableGen][GISel] Extract helper function for constraining operands (#115148)
2024-11-07 07:16:54 +03:00
inst-select-zextload-local.mir
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
irtranslate-bf16.ll
[GlobalISel] Fix buildCopyFromRegs for split vectors (#77448)
2024-01-16 10:04:20 +01:00
irtranslator-amdgcn-cs-chain.ll
[AMDGPU] Fix @llvm.amdgcn.cs.chain with SGPR args not provably uniform (#114232)
2024-10-30 16:12:37 +00:00
irtranslator-amdgcn-sendmsg.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
irtranslator-amdgpu_kernel-system-sgprs.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-amdgpu_kernel.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-amdgpu_ps.ll
AMDGPU: Replace undef with poison in tests using insertvalue (#130895)
2025-03-12 16:11:11 +07:00
irtranslator-amdgpu_vs.ll
AMDGPU: Replace some float undef test uses with poison (#131090)
2025-03-13 20:07:48 +07:00
irtranslator-assert-align.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
irtranslator-atomicrmw.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
irtranslator-call-abi-attribute-hints.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
irtranslator-call-implicit-args.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-call-non-fixed.ll
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
irtranslator-call-return-values.ll
[AMDGPU] Fix UB in tests due to mismatched calling conventions (#137957)
2025-05-06 18:31:27 +02:00
irtranslator-call-sret.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
irtranslator-call.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
irtranslator-constant-fold-vector-op.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
irtranslator-constantexpr.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
irtranslator-constrained-fp.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
irtranslator-fast-math-flags.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-fence.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-fixed-function-abi-vgpr-args.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-function-args.ll
AMDGPU: Replace ptr addrspace(3) undef in tests with poison (#131049)
2025-03-13 13:28:55 +07:00
irtranslator-function-args.v2i65.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-getelementptr.ll
…
irtranslator-indirect-call.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
irtranslator-inline-asm.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
irtranslator-invariant.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
irtranslator-memory-intrinsics.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
irtranslator-metadata.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
irtranslator-non-integral-address-spaces-vectors.ll
[AMDGPULowerBufferFatPointers] Use InstSimplifyFolder during rewrites (#134137)
2025-04-03 10:12:18 -05:00
irtranslator-non-integral-address-spaces.ll
[AMDGPU] Add IR-level pass to rewrite away address space 7 (#77952)
2024-03-06 09:49:58 -06:00
irtranslator-prefetch.ll
[GlobalISel] Add G_PREFETCH (#74863)
2023-12-11 11:06:50 +00:00
irtranslator-ptrmask.ll
[IR] Require that ptrmask mask matches pointer index size (#69343)
2023-10-24 09:54:29 +02:00
irtranslator-readnone-intrinsic-callsite.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-sat.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
irtranslator-sibling-call.ll
[AMDGPU] Fix UB in tests due to mismatched calling conventions (#137957)
2025-05-06 18:31:27 +02:00
irtranslator-struct-return-intrinsics.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-tail-call.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
irtranslator-zext-vec-index.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
is-safe-to-sink-bug.ll
AMDGPU: fix isSafeToSink expecting exactly one predecessor (#89224)
2024-05-10 13:02:05 +02:00
knownbits-ptrtoint.mir
[GISelValueTracking] Add test case for G_PTRTOINT
2025-06-11 10:47:17 -07:00
lds-global-value.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
lds-misaligned-bug.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
lds-relocs.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
lds-zero-initializer.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
legalize-abs.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-add.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-addrspacecast.mir
[AMDGPU][GlobalISel] Save a copy in one case of addrspacecast (#104789)
2024-08-19 18:22:29 +01:00
legalize-amdgcn.if-invalid.mir
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
legalize-amdgcn.if.xfail.mir
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
legalize-amdgcn.rsq.clamp.mir
…
legalize-amdgcn.wavefrontsize.mir
…
legalize-amdgcn.workitem.id.mir
…
legalize-and.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-anyext.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ashr.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-atomic-cmpxchg-with-success.mir
[GlobalISel] Fold G_ICMP if possible (#86357)
2024-03-29 15:59:50 -04:00
legalize-atomic-cmpxchg.mir
…
legalize-atomicrmw-add.mir
…
legalize-atomicrmw-and.mir
…
legalize-atomicrmw-fadd-global.mir
…
legalize-atomicrmw-fadd-local.mir
…
legalize-atomicrmw-max.mir
…
legalize-atomicrmw-min.mir
…
legalize-atomicrmw-nand.mir
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
legalize-atomicrmw-or.mir
…
legalize-atomicrmw-sub.mir
…
legalize-atomicrmw-umax.mir
…
legalize-atomicrmw-umin.mir
…
legalize-atomicrmw-xchg-flat.mir
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
legalize-atomicrmw-xchg.mir
…
legalize-atomicrmw-xor.mir
…
legalize-bitcast.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-bitreverse.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-block-addr.mir
…
legalize-brcond.mir
[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)
2024-07-28 11:26:29 +04:00
legalize-bswap.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-build-vector-splat.mir
…
legalize-build-vector-trunc.mir
…
legalize-build-vector.mir
[AMDGPU][GlobalIsel] Introduce isRegisterClassType to check for legal types, instead of checking bit width. (#68189)
2024-02-13 08:26:10 +01:00
legalize-build-vector.s16.mir
…
legalize-concat-vectors.mir
…
legalize-constant.mir
…
legalize-ctlz-zero-undef.mir
[LegalizeDAG] Optimize CodeGen for ISD::CTLZ_ZERO_UNDEF (#83039)
2024-07-08 14:01:32 +01:00
legalize-ctlz.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ctpop.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-cttz-zero-undef.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
legalize-cttz.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-extract-vector-elt.mir
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
legalize-extract.mir
…
legalize-extractelement-crash.mir
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
legalize-fabs.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fadd.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fcanonicalize.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fceil.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fcmp-s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-fcmp.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fconstant.mir
…
legalize-fcopysign.mir
DAG/GlobalISel: Set disjoint for or in copysign lowering (#97057)
2024-06-28 23:03:39 +02:00
legalize-fcos.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fdiv.mir
[AMDGPU] Adopt new lowering sequence for fdiv16 (#109295)
2024-10-08 09:49:20 -04:00
legalize-fexp2.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fexp.mir
[AMDGPU] Generic lowering for rint and nearbyint (#69596)
2023-11-14 18:49:21 +01:00
legalize-ffloor.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-flog2.mir
AMDGPU: Use correct lowering for llvm.log2.f32
2023-06-23 08:37:37 -04:00
legalize-flog10.mir
AMDGPU: Correctly lower llvm.log.f32 and llvm.log10.f32
2023-07-05 15:30:35 -04:00
legalize-flog.mir
AMDGPU: Correctly lower llvm.log.f32 and llvm.log10.f32
2023-07-05 15:30:35 -04:00
legalize-fma.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fmad.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fmad.s32.mir
…
legalize-fmad.s64.mir
…
legalize-fmaxnum.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fminnum.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fmul.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fneg.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fpext.mir
…
legalize-fpow.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fpowi.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
legalize-fptosi.mir
…
legalize-fptoui.mir
…
legalize-fptrunc.mir
…
legalize-freeze.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
legalize-fshl.mir
[AArch64][GlobalISel] Add disjoint handling for add_and_or_is_add. (#123594)
2025-02-02 21:01:49 +00:00
legalize-fshr.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fsin.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fsqrt.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fsub.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-icmp.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-implicit-def-s1025.mir
…
legalize-implicit-def.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
legalize-insert-vector-elt.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
legalize-insert.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-intrinsic-amdgcn-fdiv-fast.mir
AMDGPU: Use hex floats instead of ugly bitcasting
2023-07-17 19:54:04 -04:00
legalize-intrinsic-round.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-intrinsic-trunc.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-inttoptr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-jump-table.mir
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
legalize-llvm.amdgcn.image.dim.a16.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
legalize-llvm.amdgcn.image.load.2d.d16.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
legalize-llvm.amdgcn.image.load.2d.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.load.3d.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
legalize-llvm.amdgcn.image.sample.a16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
legalize-llvm.amdgcn.image.sample.d.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.sample.g16.a16.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.sample.g16.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
legalize-llvm.amdgcn.s.buffer.load.mir
[AMDGPU][GISel] Use datalayout alignment for buffer-load legalization (#95578)
2024-06-15 18:19:52 +05:30
legalize-load-constant-32bit.mir
…
legalize-load-constant.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-load-flat.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-load-global.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-load-local.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-load-memory-metadata.mir
MachineVerifier: Fix check for range type (#124894)
2025-01-30 10:56:12 +07:00
legalize-load-private.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-lshr.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-memcpy.mir
…
legalize-memcpyinline.mir
…
legalize-memmove.mir
…
legalize-memset.mir
…
legalize-merge-values-build-vector.mir
…
legalize-merge-values.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-mul.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-or.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-phi.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-ptr-add.mir
[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)
2024-03-09 09:07:22 +00:00
legalize-ptrmask.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ptrtoint.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-rotl-rotr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-sadde.mir
…
legalize-saddo.mir
[GISel] LegalizationArtifactCombiner: Elide redundant G_SEXT_INREG (#93687)
2024-05-30 12:40:42 +03:00
legalize-saddsat.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-sbfx.mir
[AMDGPU] Remove unused check lines from GlobalISel MIR tests
2023-04-19 15:03:32 +01:00
legalize-sdiv.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-select.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-sext-inreg.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-sext.mir
[AMDGPU][Legalizer] Widen i16 G_SEXT_INREG (#131308)
2025-05-07 10:22:15 +02:00
legalize-sextload-constant-32bit.mir
…
legalize-sextload-flat.mir
…
legalize-sextload-global.mir
…
legalize-sextload-local.mir
…
legalize-sextload-private.mir
…
legalize-shl.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-shuffle-vector.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-shuffle-vector.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-sitofp.mir
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics
2023-06-06 17:07:18 -04:00
legalize-smax.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-smin.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-smulh.mir
[AMDGPU][Legalizer] Widen i16 G_SEXT_INREG (#131308)
2025-05-07 10:22:15 +02:00
legalize-smulo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-srem.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-sshlsat.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-ssube.mir
…
legalize-ssubo.mir
[GISel] LegalizationArtifactCombiner: Elide redundant G_SEXT_INREG (#93687)
2024-05-30 12:40:42 +03:00
legalize-ssubsat.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-store-global.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-store.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-strict_fsub.mir
…
legalize-sub.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-trap-gfx11.mir
[AMDGPU] Fix broken MIR generated by gfx11 simulated trap lowering (#91652)
2024-05-22 10:55:19 -04:00
legalize-trap.mir
[GlobalISel] Introduce G_TRAP, G_DEBUGTRAP, G_UBSANTRAP (#84941)
2024-03-23 13:12:44 +01:00
legalize-trunc.mir
[GlobalISel] Combine unmerge(unmerge()) if the result is legal. (#109606)
2024-09-25 07:04:09 +01:00
legalize-uadde.mir
…
legalize-uaddo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-uaddsat.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-ubfx.mir
…
legalize-udiv.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-uitofp.mir
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics
2023-06-06 17:07:18 -04:00
legalize-umax.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-umin.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-umulh.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-umulo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-unmerge-values.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-urem.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-ushlsat.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-usube.mir
…
legalize-usubo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-usubsat.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-vector-args-gfx7.mir
…
legalize-vector-args-gfx8-plus.mir
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
legalize-xor.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-zext.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-zextload-constant-32bit.mir
…
legalize-zextload-flat.mir
…
legalize-zextload-global.mir
…
legalize-zextload-local.mir
…
legalize-zextload-private.mir
…
llvm.abs.ll
[AMDGPU][Legalizer] Widen i16 G_SEXT_INREG (#131308)
2025-05-07 10:22:15 +02:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.ballot.i64.ll
AMDGPU/GlobalISel: Fix inst-selection of ballot (#109986)
2024-10-11 11:40:27 +02:00
llvm.amdgcn.dispatch.ptr.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
llvm.amdgcn.div.fmas.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.div.scale.ll
AMDGPU: Migrate some tests away from undef (#131277)
2025-03-15 00:29:10 +07:00
llvm.amdgcn.end.cf.i32.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
llvm.amdgcn.end.cf.i64.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
llvm.amdgcn.fdot2.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.fmul.legacy.ll
AMDGPU: Replace some float undef test uses with poison (#131090)
2025-03-13 20:07:48 +07:00
llvm.amdgcn.global.atomic.csub.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
llvm.amdgcn.if.break.i32.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
llvm.amdgcn.if.break.i64.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.image.atomic.dim.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.atomic.dim.mir
[AMDGPU][MC] Fix disassembler problem for image_atomic with TFE (#112622)
2024-10-24 16:19:18 -07:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.gather4.o.dim.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.image.getresinfo.a16.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.image.getresinfo.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.1d.d16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.1d.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.2d.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.2darraymsaa.a16.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.image.load.2darraymsaa.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.3d.a16.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.image.load.3d.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.sample.cd.g16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.sample.g16.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.store.2d.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.implicit.ptr.buffer.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
llvm.amdgcn.interp.inreg.ll
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
llvm.amdgcn.interp.p1.f16.ll
…
llvm.amdgcn.intersect_ray.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.kernarg.segment.ptr.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
llvm.amdgcn.make.buffer.rsrc.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.mfma.gfx90a.ll
AMDGPU: Try to perform copy to agpr from reg_sequence at the copy (#129463)
2025-03-04 14:41:56 +07:00
llvm.amdgcn.mov.dpp.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.queue.ptr.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.raw.buffer.atomic.add.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.load.format.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.load.tfe.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.raw.buffer.store.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.store.format.f32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.load.format.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.tbuffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.tbuffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.tbuffer.store.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.tbuffer.store.i8.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.rsq.clamp.ll
AMDGPU: Migrate some tests away from undef (#131277)
2025-03-15 00:29:10 +07:00
llvm.amdgcn.s.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.s.setreg.ll
Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)
2025-03-13 10:26:20 +01:00
llvm.amdgcn.s.sleep.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sbfe.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.sdot2.ll
[AMDGPU] Re-Re-apply: Implement vop3p complex pattern optmization for gisel (#146984)
2025-07-08 15:10:44 +08:00
llvm.amdgcn.sdot4.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sdot8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.set.inactive.ll
[AMDGPU] Add identity_combines to RegBankCombiner (#131305)
2025-03-17 10:11:28 +01:00
llvm.amdgcn.softwqm.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.buffer.atomic.add.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.load.tfe.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.struct.buffer.store.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.load.format.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.tbuffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.sudot4.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sudot8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.trig.preop.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
llvm.amdgcn.ubfe.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.udot2.ll
[AMDGPU] Re-Re-apply: Implement vop3p complex pattern optmization for gisel (#146984)
2025-07-08 15:10:44 +08:00
llvm.amdgcn.udot4.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.udot8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.update.dpp.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.wmma_32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.wmma_64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.workgroup.id.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.workitem.id.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.wqm.demote.ll
[AMDGPU] Fix computed kill mask (#122736)
2025-01-14 10:00:40 +01:00
llvm.amdgcn.wqm.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.writelane.ll
…
llvm.amdgcn.wwm.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.memcpy.inline.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.memcpy.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
llvm.memmove.ll
[LowerMemIntrinsics] Lower llvm.memmove to wide memory accesses (#100122)
2024-07-26 08:43:30 +02:00
llvm.memset.ll
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
llvm.powi.ll
[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)
2025-01-06 17:42:38 +05:30
load-constant32bit.ll
…
load-constant.96.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
load-legalize-range-metadata.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
load-local.96.ll
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
load-local.128.ll
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
load-unaligned.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
localizer-wrong-insert-point.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
localizer.ll
[AMDGPU] Add identity_combines to RegBankCombiner (#131305)
2025-03-17 10:11:28 +01:00
lshr.ll
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
madmix-constant-bus-violation.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
madmix-constant-bus-violation.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
memory-legalizer-atomic-fence.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
merge-buffer-stores.ll
[SeperateConstOffsetFromGEP] Handle or disjoint flags (#76997)
2024-01-26 09:56:06 -06:00
minmaxabs.ll
…
mmra.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
mubuf-global.ll
[AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (#135340)
2025-04-22 14:53:55 +02:00
mul-known-bits.i64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
mul-known-bits.i64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mul.ll
[AMDGPU] Fix bad removal of s_delay_alu (#145728)
2025-06-27 16:15:10 +02:00
mul.v2i16.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
no-cse-nonlocal-convergent-instrs.mir
[CodeGen][NewPM] Port MachineCSE pass to new pass manager. (#106605)
2024-09-04 18:54:07 +05:30
no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
[GlobalISel] Check whether G_CTLZ is legal in matchUMulHToLShr (#126457)
2025-02-10 00:11:09 -05:00
no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
[GlobalISel] Check whether G_CTLZ is legal in matchUMulHToLShr (#126457)
2025-02-10 00:11:09 -05:00
no-legalize-atomic.mir
…
non-entry-alloca.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
or.ll
[GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (#138574)
2025-05-08 19:31:28 +02:00
orn2.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
postlegalizer-combiner-buildvector-identities.mir
…
postlegalizer-combiner-divrem.mir
…
postlegalizer-combiner-fcanonicalize.mir
…
postlegalizer-combiner-freeze.mir
…
postlegalizer-combiner-reassoc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
postlegalizer-combiner-sextload-from-sextinreg.mir
GlobalISel: Fix combine duplicating atomic loads (#111730)
2024-10-31 07:55:12 -07:00
postlegalizer-combiner-trunc-bitcast-buildvector.mir
…
postlegalizer-combiner-unmerge-undef.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
postlegalizer-combiner-zextload-from-and.mir
…
postlegalizercombiner-and.mir
[AMDGPU][GlobalISel] Disable fixed-point iteration in all Combiners (#105517)
2024-08-22 17:14:53 +01:00
postlegalizercombiner-ashr.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-load-and-mask.mir
…
postlegalizercombiner-lshr.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-mul.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
postlegalizercombiner-sbfx.mir
…
postlegalizercombiner-select.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
postlegalizercombiner-shl.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-ubfx.mir
…
prelegalizer-combiner-divrem.mir
AMDGPU: Replace more undef test pointer uses with poison (#131102)
2025-03-14 09:53:45 +07:00
prelegalizer-combiner-fptrunc_fpext.mir
GlobalISel: Fold out G_FPTRUNC(G_FPEXT)
2023-05-10 08:01:27 +01:00
prelegalizer-combiner-redundant-bitcast.mir
…
prelegalizer-combiner-sext_inreg-to-and.mir
…
prelegalizer-combiner-shuffle.mir
[GISel] Fix ShuffleVector assert (#139769)
2025-05-20 21:25:31 -04:00
promote-dependency-on-invariant-result.ll
GlobalISel: Fix defined register of invariant.start (#125664)
2025-02-04 23:59:03 +07:00
regbankcombiner-clamp-fmed3-const.mir
[AMDGPU] Update IEEE and DX10_CLAMP for GFX12 (#75030)
2023-12-13 13:52:40 +01:00
regbankcombiner-clamp-minmax-const.mir
…
regbankcombiner-fmed3-minmax-const.mir
…
regbankcombiner-redundant-and.mir
AMDGPU/GlobalISel: Run redundant_and combine in RegBankCombiner (#112353)
2024-10-16 09:43:16 +02:00
regbankcombiner-smed3.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankcombiner-umed3.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-abs.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-add.s16.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-add.s32.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-add.v2s16.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn-exp-compr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn-exp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn-s-buffer-load.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ballot.i64.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.class.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.cvt.pkrtz.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.div.fmas.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.div.scale.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.ds.append.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.bpermute.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.ds.consume.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.gws.init.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.gws.sema.v.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.ordered.add.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.ordered.swap.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.permute.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.ds.swizzle.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.else.32.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.else.64.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.fcmp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.fmul.legacy.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.groupstaticsize.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.icmp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.image.load.1d.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
regbankselect-amdgcn.image.sample.1d.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
regbankselect-amdgcn.interp.mov.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p1.f16.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p1.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p2.f16.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p2.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.kernarg.segment.ptr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.kill.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.lds.direct.load.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.lds.param.load.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.live.mask.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.mfma.gfx90a.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.mfma.gfx942.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
regbankselect-amdgcn.mfma.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.ps.live.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.raw.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.raw.ptr.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.readfirstlane.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.readlane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.s.buffer.load.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
regbankselect-amdgcn.s.buffer.load.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.getpc.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.getreg.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.memrealtime.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.memtime.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.sendmsg.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.s.sendmsghalt.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.struct.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.struct.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.struct.ptr.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.struct.ptr.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.update.dpp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.wqm.demote.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.wqm.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.wqm.vote.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.writelane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.wwm.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgpu-ffbh-u32.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgpu-ffbl-b32.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgpu-wave-address.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-and-s1.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (#132383)
2025-05-26 12:10:54 +02:00
regbankselect-and.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (#132382)
2025-05-26 12:07:46 +02:00
regbankselect-anyext.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (#132383)
2025-05-26 12:10:54 +02:00
regbankselect-ashr.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
regbankselect-assert-align.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-assert-zext.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomic-cmpxchg.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-add.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-and.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-fadd.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-max.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-min.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-or.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-sub.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-umax.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-umin.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-xchg.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-xor.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-bitcast.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-bitreverse.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-block-addr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-brcond.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-bswap.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-build-vector.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-concat-vector.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-constant.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-copy.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ctlz-zero-undef.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ctpop.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-cttz-zero-undef.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-default.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-dyn-stackalloc.mir
[AMDGPU] Support divergent sized dynamic alloca (#121148)
2025-01-06 12:28:24 +07:00
regbankselect-extract-vector-elt.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-extract.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fabs.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fadd.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fcanonicalize.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fceil.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fcmp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fexp2.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-flog2.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fma.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fmul.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fneg.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fpext.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fptosi.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fptoui.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fptrunc.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-frame-index.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-freeze.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fshr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fsqrt.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fsub.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-icmp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-icmp.s16.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-illegal-copy.mir
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
regbankselect-implicit-def.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-insert-vector-elt.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-insert.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-intrinsic-trunc.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-inttoptr.mir
[AMDGPU] New RegBankSelect: Add rules for G_PTRTOINT and G_INTTOPTR (#142604)
2025-06-19 10:21:17 +02:00
regbankselect-load.mir
AMDGPU/GlobalISel: RegBankLegalize rules for load (#112882)
2025-01-24 12:36:41 +01:00
regbankselect-lshr.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
regbankselect-mad_64_32.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-merge-values.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-mui-regbanklegalize.mir
MachineUniformityAnalysis: Improve isConstantOrUndefValuePhi (#112866)
2025-01-24 12:43:40 +01:00
regbankselect-mui-regbankselect.mir
AMDGPU/GlobalISel: Disable LCSSA pass (#124297)
2025-03-12 11:09:50 +01:00
regbankselect-mui-salu-float.ll
AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)
2025-01-24 12:12:45 +01:00
regbankselect-mui-salu-float.mir
AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)
2025-01-24 12:12:45 +01:00
regbankselect-mui.ll
[AMDGPU] Add identity_combines to RegBankCombiner (#131305)
2025-03-17 10:11:28 +01:00
regbankselect-mui.mir
AMDGPU/GlobalISel: Disable LCSSA pass (#124297)
2025-03-12 11:09:50 +01:00
regbankselect-mul.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-or.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (#132382)
2025-05-26 12:07:46 +02:00
regbankselect-phi-s1.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-phi.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-pseudo-scalar-transcendental.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-ptr-add.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ptrmask.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ptrtoint.mir
[AMDGPU] New RegBankSelect: Add rules for G_PTRTOINT and G_INTTOPTR (#142604)
2025-06-19 10:21:17 +02:00
regbankselect-reg-sequence.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-sadde.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-salu-float.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-sbfx.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)
2025-05-26 11:58:57 +02:00
regbankselect-select.mir
[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule (#142560)
2025-06-19 09:56:07 +02:00
regbankselect-sext-inreg.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
regbankselect-sext.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (#132383)
2025-05-26 12:10:54 +02:00
regbankselect-sextload.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-shl.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
regbankselect-sitofp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-smax.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-smin.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-smulh.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-split-scalar-load-metadata.mir
[GlobalISel] Catching inconsistencies in load memory, result, and range metadata type (#121247)
2025-01-28 20:54:34 +07:00
regbankselect-ssube.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-sub.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-trunc.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (#132383)
2025-05-26 12:10:54 +02:00
regbankselect-uadde.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-uaddo.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ubfx.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)
2025-05-26 11:58:57 +02:00
regbankselect-uitofp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-umax.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-umin.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-umulh.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-uniform-load-noclobber.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-unmerge-values.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-usube.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-usubo.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-waterfall-agpr.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-widen-scalar-loads.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-xor.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (#132382)
2025-05-26 12:07:46 +02:00
regbankselect-zext.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (#132383)
2025-05-26 12:10:54 +02:00
regbankselect-zextload.mir
AMDGPU/GlobalISel: RegBankLegalize rules for load (#112882)
2025-01-24 12:36:41 +01:00
regbankselect.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
saddsat.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
sbfx.ll
AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)
2025-05-26 11:58:57 +02:00
sdiv.i32.ll
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
sdiv.i64.ll
[AMDGPU] Add identity_combines to RegBankCombiner (#131305)
2025-03-17 10:11:28 +01:00
sdivrem.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
select-to-fmin-fmax.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
selected-inst-flags.mir
[GlobalISel] Fix silently dropped MIFlags on selected instructions (#138851)
2025-05-07 14:07:16 +02:00
sext_inreg.ll
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
shader-epilogs.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shl-ext-reduce.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
shl.ll
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
shlN_add.ll
AMDGPU: Replace undef with poison in tests using insertvalue (#130895)
2025-03-12 16:11:11 +07:00
shufflevector-pointer-crash.mir
[GlobalISel] support lowering of G_SHUFFLEVECTOR with pointer args (#141959)
2025-06-05 09:13:51 -07:00
shufflevector.ll
[GISel][AMDGPU] Expand ShuffleVector (#124527)
2025-04-09 17:51:24 -07:00
smed3.ll
[GlobalISel] Handle more commutable instructions in commute_constant_to_rhs
2024-04-16 02:36:12 -04:00
smrd.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
srem.i32.ll
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
srem.i64.ll
[AMDGPU] Add identity_combines to RegBankCombiner (#131305)
2025-03-17 10:11:28 +01:00
ssubsat.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
store-local.96.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
store-local.128.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
strict_fma.f16.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
strict_fma.f32.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
strict_fma.f64.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
sub.v2i16.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
subo.ll
[AMDGPU] Add identity_combines to RegBankCombiner (#131305)
2025-03-17 10:11:28 +01:00
trunc.ll
AMDGPU: Replace tests using undef in shufflevector with poison (#130899)
2025-03-12 20:45:02 +07:00
twoaddr-extract-dyn-v7f64.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
uaddsat.ll
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
ubfx.ll
AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)
2025-05-26 11:58:57 +02:00
udiv.i32.ll
[AMDGPU] Use correct number of bits needed for div/rem shrinking (#80622)
2024-02-06 21:32:28 +05:30
udiv.i64.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
udivrem.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
umed3.ll
[GlobalISel] Handle more commutable instructions in commute_constant_to_rhs
2024-04-16 02:36:12 -04:00
unsupported-load.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
unsupported-ptr-add.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
urem.i32.ll
[GlobalISel] Allow expansion of urem by constant in prelegalizer (#145914)
2025-07-02 13:46:36 +01:00
urem.i64.ll
[GlobalISel] Allow expansion of urem by constant in prelegalizer (#145914)
2025-07-02 13:46:36 +01:00
usubsat.ll
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
v_bfe_i32.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
vni8-across-blocks.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
widen-i8-i16-scalar-loads.ll
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
[AMDGPU][True16][CodeGen] add -real-true16 flag to a few gisel gfx12 test (#141503)
2025-05-27 09:58:27 -04:00
wmma-gfx12-w32-imm.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-iu-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-swmmac-index_key.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
[AMDGPU][True16][CodeGen] add -real-true16 flag to a few gisel gfx12 test (#141503)
2025-05-27 09:58:27 -04:00
wmma-gfx12-w64-imm.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-iu-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-swmmac-index_key.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
xnor.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
xor.ll
[GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (#138574)
2025-05-08 19:31:28 +02:00
zextload.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00