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llvm-project/llvm/lib/Target/RISCV
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Jim Lin 2a8c7d3c69
[RISCV] Add support for -mtune=andes-45-series (#142900) 
Enables the use of `-mtune=andes-45-series` to generate code optimized
with the Andes 45 series scheduling model and tuning features.
2025-06-06 11:34:19 +08:00
..
AsmParser
MCSymbol: Remove the default argument of getVariableValue
2025-05-27 20:34:18 -07:00
Disassembler
[RISCV] Add MC layer support for XSfmm*. (#133031)
2025-05-21 08:26:35 -07:00
GISel
[RISCV] Fix a warning
2025-05-30 10:27:57 -07:00
MCA
Prune a redundant include "RISCVISelDAGToDAG.h" (fixup for #128978)
2025-03-01 14:04:48 +09:00
MCTargetDesc
RISCVAsmBackend: Simplify relaxDwarfCFA
2025-06-05 09:13:37 -07:00
TargetInfo
…
CMakeLists.txt
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCV.h
Register assembly printer passes (#138348)
2025-05-06 18:01:17 -07:00
RISCV.td
[RISCV] Implement base scheduling model for andes 45 series processor. (#141008)
2025-06-04 16:11:43 +08:00
RISCVAsmPrinter.cpp
RISCV: Replace most Specifier constants with relocation types
2025-05-17 10:14:33 -07:00
RISCVCallingConv.cpp
[RISCV] Use t3 for static chain register when branch CFI is enabled (#142344)
2025-06-03 03:13:38 +08:00
RISCVCallingConv.h
…
RISCVCallingConv.td
[RISCV] Implement getIPRACSRegs hook (#125586)
2025-02-04 10:02:42 -03:00
RISCVCodeGenPrepare.cpp
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
RISCVCombine.td
…
RISCVConstantPoolValue.cpp
…
RISCVConstantPoolValue.h
…
RISCVDeadRegisterDefinitions.cpp
[RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0,x0 vsetvli. NFC (#141875)
2025-05-29 10:21:38 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[NFC][LLVM][RISCV] Cleanup pass initialization for RISCV (#134279)
2025-04-03 11:28:45 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Prevent using dummy_reg_pair_with_x0 in more places. (#141273)
2025-05-23 13:40:27 -07:00
RISCVFeatures.td
[RISCV] Add shlcofideleg extension (#141572)
2025-05-30 16:52:08 +08:00
RISCVFoldMemOffset.cpp
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
2025-04-22 19:24:29 -07:00
RISCVFrameLowering.cpp
[RISCV] Use llvm::is_contained (NFC) (#141372)
2025-05-24 14:46:55 -07:00
RISCVFrameLowering.h
…
RISCVGatherScatterLowering.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVGISel.td
[Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/64. NFC (#137428)
2025-04-28 09:26:34 -07:00
RISCVIndirectBranchTracking.cpp
[RISCV] Make RISCVIndirectBranchTracking visible in debug output (#141623)
2025-05-28 14:56:44 +08:00
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0,x0 vsetvli. NFC (#141875)
2025-05-29 10:21:38 -07:00
RISCVInsertWriteVXRM.cpp
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVInstrFormats.td
[SiFive][RISCV] Remove VMConstraint from XSfvqmaccqoq and XSfvfwmaccqqq instructions. (#142914)
2025-06-05 07:05:23 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (#129104)
2025-02-27 13:14:22 -08:00
RISCVInstrGISel.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfo.cpp
[RISCV] Add missing immediate operand type for verifyInstruction. NFC. (#143056)
2025-06-06 09:23:06 +08:00
RISCVInstrInfo.h
[RISCV] Add isel patterns for generating Xqcibi branch instructions (#139872)
2025-05-16 08:45:30 +05:30
RISCVInstrInfo.td
[RISCV] Add compress patterns for QC_E_J/JAL and QC_E_LI (#141561)
2025-05-28 10:29:36 +05:30
RISCVInstrInfoA.td
[RISCV] Remove AND mask generated by ( zext ( atomic_load ) ) by replacing the load with zextload for orderings not stronger then monotonic. (#136502)
2025-04-28 08:35:51 -07:00
RISCVInstrInfoC.td
[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)
2025-04-28 17:23:51 +08:00
RISCVInstrInfoD.td
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
RISCVInstrInfoF.td
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
RISCVInstrInfoM.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoQ.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVInstrInfoSFB.td
[RISCV] Fix the operand types for shift instructions in RISCVInstrInfoSFB.td. NFC
2025-03-30 22:38:26 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Fix the comment for VALUVINoVm (#132730)
2025-03-24 17:49:53 +01:00
RISCVInstrInfoVPseudos.td
[RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0,x0 vsetvli. NFC (#141875)
2025-05-29 10:21:38 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Handle more (add x, C) -> (sub x, -C) cases (#138705)
2025-05-13 09:12:24 +02:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Handle more (add x, C) -> (sub x, -C) cases (#138705)
2025-05-13 09:12:24 +02:00
RISCVInstrInfoXAndes.td
[RISCV] Support LLVM IR intrinsics for XAndesVDot (#140223)
2025-05-25 15:22:13 +08:00
RISCVInstrInfoXCV.td
[RISCV] Add Xqcibi Select_GPR_Using_CC_<Imm> Pseudos to isSelectPseudo (#140698)
2025-05-22 08:57:26 +05:30
RISCVInstrInfoXMips.td
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
RISCVInstrInfoXqccmp.td
[RISCV] Prefer RegList over Rlist in assembler. NFC
2025-04-04 09:37:52 -07:00
RISCVInstrInfoXqci.td
[RISCV] Add compress patterns for QC_E_J/JAL and QC_E_LI (#141561)
2025-05-28 10:29:36 +05:30
RISCVInstrInfoXRivos.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoXSf.td
[SiFive][RISCV] Remove VMConstraint from XSfvqmaccqoq and XSfvfwmaccqqq instructions. (#142914)
2025-06-05 07:05:23 -07:00
RISCVInstrInfoXSfmm.td
[RISCV] Add MC layer support for XSfmm*. (#133031)
2025-05-21 08:26:35 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Remove unneeded isel (sext_inreg $rs1, i32) isel pattern from RISCVInstrInfoXTHead.td. NFC
2025-05-13 09:06:04 -07:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
…
RISCVInstrInfoZa.td
[RISCV] Rename some DecoderNamespaces and cleanup debug messages. NFC (#131409)
2025-03-17 12:49:08 -07:00
RISCVInstrInfoZalasr.td
[TableGen][SelectionDAG][GISel][RISCV] Support IsNonExtLoad for IsAtomic PatFrags. (#137401)
2025-04-25 15:45:43 -07:00
RISCVInstrInfoZb.td
[RISCV] Implement codegen for XAndesPerf lea instructions (#137925)
2025-05-12 10:41:53 +08:00
RISCVInstrInfoZc.td
[RISCV] Rename Spimm to StackAdj in most places. NFC
2025-04-04 12:49:09 -07:00
RISCVInstrInfoZclsd.td
[RISCV] Reuse existing tablegen classes for Zilsd/Zclsd. NFC (#134946)
2025-04-08 17:53:39 -07:00
RISCVInstrInfoZcmop.td
…
RISCVInstrInfoZfa.td
[RISCV] Fix schedule info for FMVP_D_X. (#140766)
2025-05-22 08:39:57 -07:00
RISCVInstrInfoZfbfmin.td
…
RISCVInstrInfoZfh.td
[NFC][RISCV] Remove extra space in RISCVInstrInfoZfh.td
2025-05-13 13:53:38 +08:00
RISCVInstrInfoZicbo.td
[RISCV] Change type of Zicbop prefetch operand to GPRMem (#139888)
2025-05-15 11:18:22 +03:00
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZilsd.td
[RISCV] Lower i64 load/stores to ld/sd with Zilsd. (#139808)
2025-05-14 09:54:07 -07:00
RISCVInstrInfoZimop.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZk.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZvfbf.td
[RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (#129130)
2025-02-27 19:25:14 -08:00
RISCVInstrInfoZvk.td
[RISCV] Add vector hasAndNot to enable optimizations (#132438)
2025-03-26 10:40:00 +01:00
RISCVInstrInfoZvqdotq.td
[RISCV] Fix schedule info for Zqvdotq (#142717)
2025-06-05 12:22:43 +08:00
RISCVInstrPredicates.td
[RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0,x0 vsetvli. NFC (#141875)
2025-05-29 10:21:38 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Select unsigned bitfield insert for XAndesPerf (#142737)
2025-06-06 09:02:18 +08:00
RISCVISelDAGToDAG.h
[RISCV] Select unsigned bitfield insert for XAndesPerf (#142737)
2025-06-06 09:02:18 +08:00
RISCVISelLowering.cpp
[RISCV] Don't commute with shift if XAndesPerf is enabled (#142920)
2025-06-06 11:08:23 +08:00
RISCVISelLowering.h
[RISCV] Add BREV8 to SimplifyDemandedBitsForTargetNode. (#141898)
2025-05-29 08:56:48 -07:00
RISCVLandingPadSetup.cpp
…
RISCVLateBranchOpt.cpp
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
RISCVLoadStoreOptimizer.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVMachineFunctionInfo.cpp
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMachineFunctionInfo.h
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMacroFusion.td
…
RISCVMakeCompressible.cpp
[RISCV] Use RISCVTargetInstrInfo::copyPhysReg in RISCVMakeCompressible. NFC (#141296)
2025-05-27 08:03:26 -07:00
RISCVMergeBaseOffset.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVMoveMerger.cpp
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
RISCVOptWInstrs.cpp
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
RISCVPfmCounters.td
…
RISCVPostRAExpandPseudoInsts.cpp
…
RISCVProcessors.td
[RISCV] Add support for -mtune=andes-45-series (#142900)
2025-06-06 11:34:19 +08:00
RISCVProfiles.td
[RISCV][NFC] Add Zicsr to profiles explicitly (#136134)
2025-04-18 10:59:32 +08:00
RISCVPushPopOptimizer.cpp
[RISCV] Simplify how we find combinable cm.pop+ret. (#130204)
2025-03-06 21:55:47 -08:00
RISCVRedundantCopyElimination.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVRegisterInfo.cpp
[RISCV] Use QC_E_ADDI while eliminating the frameindex (#139515)
2025-05-16 05:47:04 +05:30
RISCVRegisterInfo.h
[RISCV][RegAlloc] Add getCSRFirstUseCost for RISC-V (#131349)
2025-03-20 15:20:04 -04:00
RISCVRegisterInfo.td
[RISCV] Add MC layer support for XSfmm*. (#133031)
2025-05-21 08:26:35 -07:00
RISCVSchedAndes45.td
[RISCV] Implement base scheduling model for andes 45 series processor. (#141008)
2025-06-04 16:11:43 +08:00
RISCVSchedGenericOOO.td
[RISCV][Scheduler] Add scheduling definitions for 128-bit Zfa instructions (#140003)
2025-05-16 11:39:05 +08:00
RISCVSchedMIPSP8700.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedRocket.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSiFive7.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSiFiveP400.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSiFiveP500.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSiFiveP600.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSiFiveP800.td
[RISCV] Fix missing WriteRes for Q extensions in SiFiveP800 scheudling model
2025-05-20 09:24:48 -07:00
RISCVSchedSpacemitX60.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSyntacoreSCR1.td
…
RISCVSchedSyntacoreSCR7.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSyntacoreSCR345.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedTTAscalonD8.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedule.td
[RISCV][Scheduler] Split UnsupportedSchedZfa by other fp extensions (#140186)
2025-05-16 15:30:01 +08:00
RISCVScheduleV.td
[RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicates.td (#137938)
2025-05-12 12:05:50 +08:00
RISCVScheduleXSf.td
…
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
…
RISCVSchedXiangShanNanHu.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSelectionDAGInfo.cpp
[RISCV] Add RISCVISD::VQDOT*_VL to RISCVSelectionDAGInfo::verifyTargetNode. (#142202)
2025-05-30 22:33:29 -07:00
RISCVSelectionDAGInfo.h
[RISCV] Add RISCVISD::VQDOT*_VL to RISCVSelectionDAGInfo::verifyTargetNode. (#142202)
2025-05-30 22:33:29 -07:00
RISCVSubtarget.cpp
[RISCV] Remove unused includes (NFC) (#141378)
2025-05-24 14:49:17 -07:00
RISCVSubtarget.h
[RISCV] Add MC layer support for XSfmm*. (#133031)
2025-05-21 08:26:35 -07:00
RISCVSystemOperands.td
[RISCV] Sort RISCVSystemOperands to match the RISC-V Privilege Specification. (#140967)
2025-05-22 08:46:48 -07:00
RISCVTargetMachine.cpp
[RISCV][NFC] Simplify the creation of Scheduler (#142553)
2025-06-03 17:55:11 +08:00
RISCVTargetMachine.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
RISCVTargetObjectFile.cpp
RISCV: Replace most Specifier constants with relocation types
2025-05-17 10:14:33 -07:00
RISCVTargetObjectFile.h
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
RISCVTargetTransformInfo.cpp
[RISCV][TTI] Discount slide cost if ri.vinsert/ri.vextract are available (#142036)
2025-05-30 11:06:28 -07:00
RISCVTargetTransformInfo.h
[RISCV][TTI] Implement getPartialReductionCost for the vqdotq cases (#140974)
2025-05-23 07:15:06 -07:00
RISCVVectorMaskDAGMutation.cpp
[RISCV] Remove unused includes (NFC) (#141378)
2025-05-24 14:49:17 -07:00
RISCVVectorPeephole.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVVLOptimizer.cpp
[llvm] Use *Set::insert_range (NFC) (#138237)
2025-06-02 19:48:13 -07:00
RISCVVMV0Elimination.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVZacasABIFix.cpp
…