Matt Arsenault 597f93d36b

AMDGPU: Check if immediate is legal for av_mov_b32_imm_pseudo (#160819) ...

This is primarily to avoid folding a frame index materialized
into an SGPR into the pseudo; this would end up looking like:
  %sreg = s_mov_b32 %stack.0
  %av_32 = av_mov_b32_imm_pseudo %sreg

Which is not useful.

Match the check used for the b64 case. This is limited to the
pseudo to avoid regression due to gfx908's special case - it
is expecting to pass here with v_accvgpr_write_b32 for illegal
cases, and stay in the intermediate state with an sgpr input.

This avoids regressions in a future patch.

2025-09-27 08:24:20 +09:00

..

AsmParser

[NFC][LLVM] Pass/return SMLoc by value instead of const reference (#160797)

2025-09-26 08:58:35 -07:00

Disassembler

[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)

2025-09-24 12:35:50 +01:00

MCA

[MCA] Use Bare Reference for InstrPostProcess (#160229)

2025-09-23 13:59:25 +00:00

MCTargetDesc

AMDGPU: Ensure both wavesize features are not set (#159234)

2025-09-25 09:46:34 +00:00

TargetInfo

[llvm] annotate interfaces in llvm/Target for DLL export (#143615)

2025-06-17 13:28:45 -07:00

Utils

[AMDGPU] Add GFX12 wave register names with WAVE_ prefix (#144352)

2025-09-25 18:13:08 +02:00

AMDGPU.h

[AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (#156971)

2025-09-05 00:07:47 -07:00

AMDGPU.td

AMDGPU: Ensure both wavesize features are not set (#159234)

2025-09-25 09:46:34 +00:00

AMDGPUAliasAnalysis.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUAliasAnalysis.h

…

AMDGPUAlwaysInlinePass.cpp

[NFC][AMDGPU] Replace direct arch comparison with isAMDGCN() (#131357)

2025-03-14 14:21:44 -04:00

AMDGPUAnnotateUniformValues.cpp

[AMDGPU] Preserve all analyses if nothing changed (#117994)

2024-11-28 14:33:05 +00:00

AMDGPUArgumentUsageInfo.cpp

[AMDGPU] Support lowering of cluster related instrinsics (#157978)

2025-09-12 21:11:17 -04:00

AMDGPUArgumentUsageInfo.h

[AMDGPU] Support lowering of cluster related instrinsics (#157978)

2025-09-12 21:11:17 -04:00

AMDGPUAsanInstrumentation.cpp

[IRBuilder] Add new overload for CreateIntrinsic (#131942)

2025-03-31 08:10:34 -07:00

AMDGPUAsanInstrumentation.h

…

AMDGPUAsmPrinter.cpp

Revert "[AMDGPU][gfx1250] Add cu-store subtarget feature (#150588)" (#157639)

2025-09-10 10:20:59 +02:00

AMDGPUAsmPrinter.h

AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)

2025-08-15 16:33:06 +01:00

AMDGPUAtomicOptimizer.cpp

[IRBuilder] Add new overload for CreateIntrinsic (#131942)

2025-03-31 08:10:34 -07:00

AMDGPUAttributes.def

[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)

2025-09-15 15:04:33 -04:00

AMDGPUAttributor.cpp

[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)

2025-09-15 15:04:33 -04:00

AMDGPUCallingConv.td

[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)

2025-03-08 09:28:20 -05:00

AMDGPUCallLowering.cpp

[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)

2025-09-16 15:37:01 -04:00

AMDGPUCallLowering.h

[AMDGPU] ISel & PEI for whole wave functions (#145858)

2025-07-21 10:39:09 +02:00

AMDGPUCodeGenPrepare.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

AMDGPUCombine.td

AMDGPU/GlobalISel: Import D16 load patterns and add combines for them (#153178)

2025-09-11 12:02:50 +02:00

AMDGPUCombinerHelper.cpp

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

AMDGPUCombinerHelper.h

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

AMDGPUCtorDtorLowering.cpp

…

AMDGPUCtorDtorLowering.h

…

AMDGPUExportClustering.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUExportClustering.h

…

AMDGPUExportKernelRuntimeHandles.cpp

AMDGPU: Move enqueued block handling into clang (#128519)

2025-03-10 19:54:04 +07:00

AMDGPUExportKernelRuntimeHandles.h

AMDGPU: Move enqueued block handling into clang (#128519)

2025-03-10 19:54:04 +07:00

AMDGPUFeatures.td

[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)

2025-08-14 12:52:00 -07:00

AMDGPUFrameLowering.cpp

…

AMDGPUFrameLowering.h

…

AMDGPUGenRegisterBankInfo.def

…

AMDGPUGISel.td

AMDGPU/GlobalISel: Import D16 load patterns and add combines for them (#153178)

2025-09-11 12:02:50 +02:00

AMDGPUGlobalISelDivergenceLowering.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUGlobalISelUtils.cpp

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

AMDGPUGlobalISelUtils.h

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

AMDGPUHSAMetadataStreamer.cpp

[AMDGPU] Add the support for .cluster_dims code object metadata (#158721)

2025-09-15 16:13:07 -04:00

AMDGPUHSAMetadataStreamer.h

[AMDGPU] Add the support for .cluster_dims code object metadata (#158721)

2025-09-15 16:13:07 -04:00

AMDGPUIGroupLP.cpp

Revert "[llvm][NFC] Use llvm::sort()" (#140668)

2025-05-20 11:27:03 +08:00

AMDGPUIGroupLP.h

…

AMDGPUImageIntrinsicOptimizer.cpp

[AMDGPU] Change placeholder from undef to poison (#130853)

2025-03-12 12:52:38 +00:00

AMDGPUInsertDelayAlu.cpp

AMDGPU: Treat WMMA XDL ops as TRANS in S_DELAY_ALU insertion for gfx1250 (#149208)

2025-07-16 17:07:48 -07:00

AMDGPUInstCombineIntrinsic.cpp

[AMDGPU] gfx1250 v_wmma_scale[16]_f32_16x16x128_f8f6f4 codegen (#152036)

2025-08-04 19:16:34 -07:00

AMDGPUInstrInfo.cpp

AMDGPU: Remove AMDGPUInstrInfo class (#144984)

2025-06-20 18:26:56 +09:00

AMDGPUInstrInfo.h

AMDGPU: Remove AMDGPUInstrInfo class (#144984)

2025-06-20 18:26:56 +09:00

AMDGPUInstrInfo.td

[AMDGPU] Tail call support for whole wave functions (#145860)

2025-09-04 10:34:43 +02:00

AMDGPUInstructions.td

[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)

2025-09-04 09:19:25 +00:00

AMDGPUInstructionSelector.cpp

[AMDGPU] Support cluster_load_async_to_lds instructions on gfx1250 (#156595)

2025-09-03 11:22:10 -07:00

AMDGPUInstructionSelector.h

[AMDGPU] Support cluster_load_async_to_lds instructions on gfx1250 (#156595)

2025-09-03 11:22:10 -07:00

AMDGPUISelDAGToDAG.cpp

[AMDGPU] Calc IsVALU correctly during UADDO/USUBO selection (#159814)

2025-09-25 13:08:30 -05:00

AMDGPUISelDAGToDAG.h

[AMDGPU] Support cluster_load_async_to_lds instructions on gfx1250 (#156595)

2025-09-03 11:22:10 -07:00

AMDGPUISelLowering.cpp

Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)

2025-09-23 17:36:02 +01:00

AMDGPUISelLowering.h

Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)

2025-09-23 17:36:02 +01:00

AMDGPULaneMaskUtils.h

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

AMDGPULateCodeGenPrepare.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

AMDGPULegalizerInfo.cpp

[AMDGPU] Add the support for 45-bit buffer resource (#159702)

2025-09-24 11:12:02 -04:00

AMDGPULegalizerInfo.h

[AMDGPU] Support lowering of cluster related instrinsics (#157978)

2025-09-12 21:11:17 -04:00

AMDGPULibCalls.cpp

[AMDGPU] Remove UnsafeFPMath uses (#151079)

2025-07-31 17:36:57 +08:00

AMDGPULibFunc.cpp

[AMDGPU] Provide default value in get intrinsic param type (#122448)

2025-01-10 15:29:42 +01:00

AMDGPULibFunc.h

AMDGPU: Verify function type matches when matching libcalls (#119043)

2024-12-16 15:01:48 +09:00

AMDGPULowerBufferFatPointers.cpp

[AMDGPU] Prevent re-visits in LowerBufferFatPointers (#159168)

2025-09-16 18:02:18 -07:00

AMDGPULowerIntrinsics.cpp

[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)

2025-09-16 14:49:48 -07:00

AMDGPULowerKernelArguments.cpp

[AMDGPU] Move kernarg preload logic to separate pass (#130434)

2025-05-11 21:18:11 -07:00

AMDGPULowerKernelAttributes.cpp

[AMDGPU] Add a new function getIntegerPairAttribute (#133271)

2025-03-27 15:38:54 -04:00

AMDGPULowerModuleLDSPass.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

AMDGPULowerVGPREncoding.cpp

[AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (#156971)

2025-09-05 00:07:47 -07:00

AMDGPULowerVGPREncoding.h

[AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (#156971)

2025-09-05 00:07:47 -07:00

AMDGPUMachineFunction.cpp

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUMachineFunction.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUMachineModuleInfo.cpp

[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)

2025-09-10 11:41:43 +02:00

AMDGPUMachineModuleInfo.h

[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)

2025-09-10 11:41:43 +02:00

AMDGPUMacroFusion.cpp

…

AMDGPUMacroFusion.h

[CodeGen] Move MISched target hooks into TargetMachine (#125700)

2025-02-05 11:41:37 +05:30

AMDGPUMarkLastScratchLoad.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUMCInstLower.cpp

[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)

2025-09-24 11:27:26 -04:00

AMDGPUMCInstLower.h

[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)

2025-09-24 11:27:26 -04:00

AMDGPUMCResourceInfo.cpp

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUMCResourceInfo.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUMemoryUtils.cpp

[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)

2025-09-16 14:49:48 -07:00

AMDGPUMemoryUtils.h

[AMDGPU] modify named barrier builtins and intrinsics (#114550)

2024-11-06 10:37:22 -08:00

AMDGPUMIRFormatter.cpp

[AMDGPU] Remove unused includes (NFC) (#116154)

2024-11-13 21:10:03 -08:00

AMDGPUMIRFormatter.h

…

AMDGPUPassRegistry.def

[AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (#156971)

2025-09-05 00:07:47 -07:00

AMDGPUPerfHintAnalysis.cpp

[llvm] Remove unused includes of SmallSet.h (NFC) (#154893)

2025-08-22 10:33:46 -07:00

AMDGPUPerfHintAnalysis.h

…

AMDGPUPostLegalizerCombiner.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

AMDGPUPredicateControl.td

…

AMDGPUPreLegalizerCombiner.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

AMDGPUPreloadKernArgProlog.cpp

[AMDGPU] Enable kernarg preload on gfx1250 (#153686)

2025-08-14 16:29:53 -07:00

AMDGPUPreloadKernArgProlog.h

[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)

2025-01-10 11:39:02 -08:00

AMDGPUPreloadKernelArguments.cpp

[AMDGPU] Fix uncaught changes made by AMDGPUPreloadKernelArgumentsPass (#154645)

2025-08-20 16:23:23 -07:00

AMDGPUPrepareAGPRAlloc.cpp

AMDGPU: Start using AV_MOV_B64_IMM_PSEUDO (#154500)

2025-08-22 13:59:36 +09:00

AMDGPUPrepareAGPRAlloc.h

AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)

2025-07-18 17:15:38 +09:00

AMDGPUPrintfRuntimeBinding.cpp

[AMDGPU] Support 'F' and 'A' conversion specifiers with ocl printf (#148784)

2025-07-15 13:24:08 +05:30

AMDGPUPromoteAlloca.cpp

[AMDGPUPromoteAlloca][NFC] Avoid unnecessary APInt/int64_t conversions (#157864)

2025-09-12 09:51:55 +02:00

AMDGPUPromoteKernelArguments.cpp

…

AMDGPUPTNote.h

…

AMDGPURegBankCombiner.cpp

AMDGPU/GlobalISel: Import D16 load patterns and add combines for them (#153178)

2025-09-11 12:02:50 +02:00

AMDGPURegBankLegalize.cpp

AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)

2025-07-23 16:44:53 +02:00

AMDGPURegBankLegalizeHelper.cpp

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

AMDGPURegBankLegalizeHelper.h

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

AMDGPURegBankLegalizeRules.cpp

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

AMDGPURegBankLegalizeRules.h

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

AMDGPURegBankSelect.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

AMDGPURegisterBankInfo.cpp

AMDGPU: Fixes for regbankselecting copies of i1 physregs to sgprs (#159283)

2025-09-17 19:48:39 +09:00

AMDGPURegisterBankInfo.h

…

AMDGPURegisterBanks.td

[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)

2025-02-25 17:09:34 -05:00

AMDGPURemoveIncompatibleFunctions.cpp

[AMDGPU] Remove wave64 functions (#153690)

2025-08-14 15:54:33 -07:00

AMDGPURemoveIncompatibleFunctions.h

[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)

2025-01-13 10:11:40 +05:30

AMDGPUReserveWWMRegs.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUReserveWWMRegs.h

[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM (#123722)

2025-03-10 17:36:35 +05:30

AMDGPUResourceUsageAnalysis.cpp

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUResourceUsageAnalysis.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPURewriteAGPRCopyMFMA.cpp

AMDGPU: Try to unspill VGPRs after rewriting MFMAs to AGPR form (#154323)

2025-09-17 00:11:32 +09:00

AMDGPURewriteOutArguments.cpp

[DebugInfo][RemoveDIs] Delete debug-info-format flag (#143746)

2025-06-12 11:51:58 +01:00

AMDGPURewriteUndefForPHI.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUSearchableTables.td

[AMDGPU] Mark cluster_workgroup_id_* intrinsics always uniform (#159439)

2025-09-17 14:07:52 -07:00

AMDGPUSelectionDAGInfo.cpp

[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)

2024-12-21 05:29:51 +03:00

AMDGPUSelectionDAGInfo.h

[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)

2024-12-21 05:29:51 +03:00

AMDGPUSetWavePriority.cpp

[llvm] Replace SmallSet with SmallPtrSet (NFC) (#154068)

2025-08-18 07:01:29 -07:00

AMDGPUSplitModule.cpp

[AMDGPU][SplitModule] Do not create empty modules (#135761)

2025-04-25 09:36:41 +02:00

AMDGPUSplitModule.h

…

AMDGPUSubtarget.cpp

[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)

2025-09-17 10:09:06 -04:00

AMDGPUSubtarget.h

[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)

2025-09-17 10:09:06 -04:00

AMDGPUSwLowerLDS.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUTargetMachine.cpp

[llvm] Move data layout string computation to TargetParser (#157612)

2025-09-11 11:05:29 -07:00

AMDGPUTargetMachine.h

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

AMDGPUTargetObjectFile.cpp

…

AMDGPUTargetObjectFile.h

…

AMDGPUTargetTransformInfo.cpp

[AMDGPU] Fix vector legalization for bf16 valu ops (#158439)

2025-09-25 10:07:11 +01:00

AMDGPUTargetTransformInfo.h

[AMDGPU] Enable vectorization of i8 values. (#134934)

2025-06-26 19:15:31 -04:00

AMDGPUUnifyDivergentExitNodes.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUUnifyDivergentExitNodes.h

…

AMDGPUWaitSGPRHazards.cpp

[llvm] Use llvm::any_of (NFC) (#141444)

2025-05-26 09:13:21 -07:00

AMDGPUWaitSGPRHazards.h

[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)

2025-01-30 11:21:11 +09:00

AMDKernelCodeT.h

…

BUFInstructions.td

CodeGen: Add RegisterClass by HwMode (#158269)

2025-09-19 20:08:51 +09:00

CaymanInstructions.td

…

CMakeLists.txt

[AMDGPU] High VGPR lowering on gfx1250 (#156965)

2025-09-04 16:20:47 -07:00

DSDIRInstructions.td

AMDGPU: Remove LDS-direct(param)-loads and VINTERP ops from gfx1250 support (#145631)

2025-06-24 22:44:35 -07:00

DSInstructions.td

AMDGPU: Add agpr versions of global return atomics (#156890)

2025-09-05 08:47:51 +09:00

EvergreenInstructions.td

Remove an unused field (follow up to cc5e8967)

2025-08-30 07:55:56 +03:00

EXPInstructions.td

AMDGPU: Remove export and related instructions from gfx1250 support (#145624)

2025-06-24 19:59:26 -07:00

FLATInstructions.td

[AMDGPU] Fix sub-dword atomic flat saddr store with no D16. NFCI (#160253)

2025-09-23 09:44:46 -07:00

GCNCreateVOPD.cpp

[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)

2025-07-10 14:15:01 -07:00

GCNDPPCombine.cpp

AMDGPU: Avoid directly using MCOperandInfo RegClass field (#156641)

2025-09-03 10:50:07 +00:00

GCNDPPCombine.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

GCNHazardRecognizer.cpp

[AMDGPU] Refine GCNHazardRecognizer hasHazard() (#138841)

2025-09-24 18:42:11 +09:00

GCNHazardRecognizer.h

[AMDGPU] w/a for s_setreg_b32 gfx1250 hazard with MODE register (#153879)

2025-08-15 16:08:13 -07:00

GCNILPSched.cpp

…

GCNIterativeScheduler.cpp

[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)

2025-06-24 11:09:36 +02:00

GCNIterativeScheduler.h

[AMDGPU] Teach iterative schedulers about IGLP (#134953)

2025-04-11 15:34:49 -07:00

GCNMinRegStrategy.cpp

…

GCNNSAReassign.cpp

[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)

2025-06-24 11:09:36 +02:00

GCNNSAReassign.h

[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager (#125034)

2025-02-18 11:13:31 +05:30

GCNPreRALongBranchReg.cpp

[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)

2025-02-05 18:46:27 +05:30

GCNPreRALongBranchReg.h

[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)

2025-02-05 18:46:27 +05:30

GCNPreRAOptimizations.cpp

[AMDGPU][True16][CodeGen] update test for buildbot failure (#131028)

2025-03-12 16:59:48 -04:00

GCNPreRAOptimizations.h

[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)

2025-02-11 11:09:38 +05:30

GCNProcessors.td

[AMDGPU] Add gfx1251 subtarget (#159430)

2025-09-17 13:02:02 -07:00

GCNRegPressure.cpp

[AMDGPU][Scheduler] Consistent occupancy calculation during rematerialization (#149224)

2025-08-08 14:26:04 +02:00

GCNRegPressure.h

[AMDGPU][Scheduler] Consistent occupancy calculation during rematerialization (#149224)

2025-08-08 14:26:04 +02:00

GCNRewritePartialRegUses.cpp

[AMDGPU] Simplify GCNRewritePartialRegUses pass. (#135199)

2025-04-11 15:45:24 +02:00

GCNRewritePartialRegUses.h

[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)

2025-02-12 11:21:40 +05:30

GCNSchedStrategy.cpp

[TII] Split isTrivialReMaterializable into two versions [nfc] (#160377)

2025-09-24 18:52:17 -07:00

GCNSchedStrategy.h

[TII] Split isTrivialReMaterializable into two versions [nfc] (#160377)

2025-09-24 18:52:17 -07:00

GCNSubtarget.cpp

[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)

2025-09-03 16:25:18 -07:00

GCNSubtarget.h

AMDGPU: Ensure both wavesize features are not set (#159234)

2025-09-25 09:46:34 +00:00

GCNVOPDUtils.cpp

[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)

2025-07-10 14:15:01 -07:00

GCNVOPDUtils.h

[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)

2025-07-10 14:15:01 -07:00

InstCombineTables.td

…

MIMGInstructions.td

AMDGPU: Use RegisterOperand for MIMG vaddr classes (#158087)

2025-09-12 08:57:22 +09:00

R600.h

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

R600.td

…

R600AsmPrinter.cpp

…

R600AsmPrinter.h

[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel

2025-03-29 11:08:13 -07:00

R600ClauseMergePass.cpp

…

R600ControlFlowFinalizer.cpp

…

R600Defines.h

…

R600EmitClauseMarkers.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

R600ExpandSpecialInstrs.cpp

[CodeGen] Remove FinalizeMachineBundles pass (#149806)

2025-07-23 11:36:49 +01:00

R600FrameLowering.cpp

…

R600FrameLowering.h

…

R600InstrFormats.td

…

R600InstrInfo.cpp

CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (#157337)

2025-09-08 12:12:19 +09:00

R600InstrInfo.h

[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)

2025-02-24 09:55:34 -08:00

R600InstrInfo.td

…

R600Instructions.td

[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)

2025-08-30 04:44:20 +00:00

R600ISelDAGToDAG.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

R600ISelLowering.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

R600ISelLowering.h

…

R600MachineCFGStructurizer.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

R600MachineFunctionInfo.cpp

…

R600MachineFunctionInfo.h

…

R600MachineScheduler.cpp

…

R600MachineScheduler.h

…

R600MCInstLower.cpp

[AMDGPU] Fix compilation errors.

2025-08-22 10:30:43 +01:00

R600OpenCLImageTypeLoweringPass.cpp

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R600OptimizeVectorRegisters.cpp

[AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)

2025-06-04 12:30:56 -07:00

R600Packetizer.cpp

[TableGen] Add mapping from processor ID to resource index for packetizer (#158182)

2025-09-17 09:12:37 +08:00

R600Processors.td

…

R600RegisterInfo.cpp

…

R600RegisterInfo.h

…

R600RegisterInfo.td

…

R600Schedule.td

…

R600Subtarget.cpp

[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)

2024-12-16 15:13:46 +03:00

R600Subtarget.h

[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)

2024-12-16 15:13:46 +03:00

R600TargetMachine.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

R600TargetMachine.h

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

R600TargetTransformInfo.cpp

[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)

2025-05-01 15:55:08 +01:00

R600TargetTransformInfo.h

[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)

2025-05-01 15:55:08 +01:00

R700Instructions.td

…

SIAnnotateControlFlow.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

SIDefines.h

[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)

2025-09-16 14:49:48 -07:00

SIFixSGPRCopies.cpp

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

SIFixSGPRCopies.h

…

SIFixVGPRCopies.cpp

[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)

2025-01-21 15:27:46 +05:30

SIFixVGPRCopies.h

[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)

2025-01-21 15:27:46 +05:30

SIFoldOperands.cpp

AMDGPU: Check if immediate is legal for av_mov_b32_imm_pseudo (#160819)

2025-09-27 08:24:20 +09:00

SIFoldOperands.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIFormMemoryClauses.cpp

[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)

2025-06-24 11:09:36 +02:00

SIFormMemoryClauses.h

[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)

2025-02-17 11:07:17 +05:30

SIFrameLowering.cpp

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

SIFrameLowering.h

Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)

2025-04-25 11:29:27 +02:00

SIInsertHardClauses.cpp

[AMDGPU] Adjust hard clause rules for gfx1250 (#152592)

2025-08-07 14:59:31 -07:00

SIInsertWaitcnts.cpp

[AMDGPU] Skip debug uses in SIInsertWaitcnts::shouldFlushVmCnt (#160818)

2025-09-26 08:39:11 +01:00

SIInstrFormats.td

CodeGen: Add RegisterClass by HwMode (#158269)

2025-09-19 20:08:51 +09:00

SIInstrInfo.cpp

[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)

2025-09-24 11:27:26 -04:00

SIInstrInfo.h

[CodeGen] Rename isReallyTriviallyReMaterializable [nfc]

2025-09-23 11:58:37 -07:00

SIInstrInfo.td

AMDGPU: Ensure both wavesize features are not set (#159234)

2025-09-25 09:46:34 +00:00

SIInstructions.td

[AMDGPU][True16][CodeGen] Avoid setting hi part in copysign (#160891)

2025-09-26 20:42:59 +02:00

SIISelLowering.cpp

[AMDGPU] Calc IsVALU correctly during UADDO/USUBO selection (#159814)

2025-09-25 13:08:30 -05:00

SIISelLowering.h

[SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD transforms (#146074)

2025-09-19 11:07:59 +02:00

SILateBranchLowering.cpp

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

SILoadStoreOptimizer.cpp

CodeGen: Remove MachineFunction argument from getRegClass (#158188)

2025-09-12 19:22:02 +09:00

SILoadStoreOptimizer.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerControlFlow.cpp

[AMDGPU] SILowerControlFlow: ensure EXEC/SCC interval recompute (#160459)

2025-09-24 18:30:40 +09:00

SILowerControlFlow.h

[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)

2025-01-16 11:06:38 +05:30

SILowerI1Copies.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerI1Copies.h

AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)

2025-03-12 12:09:37 +01:00

SILowerSGPRSpills.cpp

[MIR] Support save/restore points with independent sets of registers (#119358)

2025-09-23 11:54:52 +03:00

SILowerSGPRSpills.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerWWMCopies.cpp

[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)

2025-01-22 14:54:01 +05:30

SILowerWWMCopies.h

[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)

2025-01-22 14:54:01 +05:30

SIMachineFunctionInfo.cpp

[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)

2025-09-16 15:37:01 -04:00

SIMachineFunctionInfo.h

[AMDGPU] Support lowering of cluster related instrinsics (#157978)

2025-09-12 21:11:17 -04:00

SIMachineScheduler.cpp

[AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)

2025-06-04 12:30:56 -07:00

SIMachineScheduler.h

[AMDGPU] Replace unsigned with Register in SIMachineScheduler. NFC

2025-01-26 00:26:00 -08:00

SIMemoryLegalizer.cpp

[AMDGPU] Update comments in memory legalizer. NFC (#160453)

2025-09-24 10:04:06 -07:00

SIModeRegister.cpp

[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)

2025-03-04 10:51:03 +05:30

SIModeRegisterDefaults.cpp

…

SIModeRegisterDefaults.h

…

SIOptimizeExecMasking.cpp

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

SIOptimizeExecMasking.h

[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)

2025-01-20 16:34:01 +05:30

SIOptimizeExecMaskingPreRA.cpp

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

SIOptimizeExecMaskingPreRA.h

[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)

2025-02-20 17:35:56 +05:30

SIOptimizeVGPRLiveRange.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

SIOptimizeVGPRLiveRange.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIPeepholeSDWA.cpp

[AMDGPU] Skip debug uses in SIPeepholeSDWA (#160092)

2025-09-22 14:40:00 +01:00

SIPeepholeSDWA.h

…

SIPostRABundler.cpp

[AMDGPU] Avoid bundling a SCHED_BARRIER with memops (#153533)

2025-08-27 17:09:27 -05:00

SIPostRABundler.h

[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)

2025-02-21 16:05:58 +05:30

SIPreAllocateWWMRegs.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

SIPreAllocateWWMRegs.h

…

SIPreEmitPeephole.cpp

[AMDGPU]: Unpack packed instructions overlapped by MFMAs post-RA scheduling (#157968)

2025-09-19 09:41:02 -07:00

SIProgramInfo.cpp

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

SIProgramInfo.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

SIRegisterInfo.cpp

CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)

2025-09-12 09:18:50 +00:00

SIRegisterInfo.h

CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)

2025-09-12 09:18:50 +00:00

SIRegisterInfo.td

AMDGPU: Set RegTupleAlignUnits on _Lo256_Align2 class (#159383)

2025-09-18 07:27:47 +09:00

SISchedule.td

AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)

2025-07-21 10:09:42 -07:00

SIShrinkInstructions.cpp

[AMDGPU] Skip debug instructions in SIShrinkInstructions::matchSwap (#160123)

2025-09-23 09:36:09 +01:00

SIShrinkInstructions.h

…

SIWholeQuadMode.cpp

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

SIWholeQuadMode.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SMInstructions.td

[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)

2025-08-30 04:44:20 +00:00

SOPInstructions.td

[AMDGPU] Support lowering of cluster related instrinsics (#157978)

2025-09-12 21:11:17 -04:00

VIInstrFormats.td

…

VINTERPInstructions.td

[AMDGPU][True16][CodeGen] support for true16 for vinterp 16bit instructions (#116702)

2024-12-09 11:52:05 -05:00

VOP1Instructions.td

[AMDGPU] gfx1251 VOP1 dpp support (#159637)

2025-09-18 13:42:06 -07:00

VOP2Instructions.td

[AMDGPU] gfx1251 VOP2 dpp support (#159641)

2025-09-18 15:38:29 -07:00

VOP3Instructions.td

[AMDGPU] gfx1251 VOP3 dpp support (#159654)

2025-09-18 16:18:09 -07:00

VOP3PInstructions.td

[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)

2025-09-24 11:27:26 -04:00

VOPCInstructions.td

[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516)

2025-09-09 10:54:18 -04:00

VOPDInstructions.td

[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516)

2025-09-09 10:54:18 -04:00

VOPInstructions.td

[AMDGPU] gfx1251 VOP3 dpp support (#159654)

2025-09-18 16:18:09 -07:00