Simon Pilgrim 44eb037da0

[X86] Improve handling of i512 SRL(SIGN_BIT, Amt) (#185896) ...

Similar to what we already do for SHL(1, Amt) - just insert the (locally
shifted) bit into a zero vector in the correct element

After this I just need to handle SRA(SIGN_BIT, Amt) and SHL/SRL(-1, Amt)
mask creation patterns and I think that's it for #132601

2026-03-12 08:40:49 +00:00

..

AArch64

[AArch64][GlobalISel] Fix matchUseVectorTruncate to check element order before folding (#185834)

2026-03-11 15:33:09 +00:00

AMDGPU

AMDGPU: Add dereferenceable attribute to dispatch ptr intrinsic (#185955)

2026-03-12 07:28:39 +01:00

ARC

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ARM

[ARM] Add basic NPM support for LoadStoreOptimizer (#184139)

2026-03-08 19:28:27 +00:00

AVR

[AVR] Fix SETUGT during 128b -> 64b lowering (#182690)

2026-02-23 19:30:04 +01:00

BPF

[BPF] Fix CORE optimization bug in BPFMISimplifyPatchable (#183446)

2026-03-10 16:42:57 -07:00

CSKY

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DirectX

[DirectX] Specify element-aligned vectors (#180622)

2026-03-11 15:49:48 -07:00

Generic

[CodeGen] Add tests for ShadowStackGCLowering IR pass (#183167)

2026-02-25 16:18:49 -05:00

Hexagon

[Hexagon] Fix 64-bit funnel shift miscompilation with register shift amounts (#183669)

2026-03-10 09:16:46 -05:00

Inputs

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Lanai

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LoongArch

[LoongArch] Try to avoid casts around logical vector ops on lasx (#163523)

2026-03-11 16:49:11 +08:00

M68k

[M68k] Update llvm/test/CodeGen/M68k/pipeline.ll (#182809)

2026-02-23 17:50:43 +08:00

Mips

[MIPS] Fix duplicate RUN lines in tests (#182276)

2026-03-06 10:52:04 +00:00

MIR

MIPSr6: Fix COPY of reg:fgr64cc without fcmp in the same BB (#185820)

2026-03-12 07:55:16 +08:00

MIR2Vec

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MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Remove NoNaNsFPMath uses (#183447)

2026-03-05 20:50:05 +08:00

PowerPC

[MC] Rename PrivateGlobalPrefix to InternalSymbolPrefix. NFC (#185164)

2026-03-10 01:03:27 -07:00

RISCV

[RISCV]Lower one active interleaved load to normal segmented load (#185602)

2026-03-11 18:08:32 +08:00

SPARC

[SPARC] Set how many bytes load from or store to stack slot (#182674)

2026-02-22 20:20:54 +08:00

SPIRV

[NFC][SPIRV] New test for untested SPIRV backend case (#185686)

2026-03-11 19:19:46 +00:00

SystemZ

[SystemZ] Add missing REQUIRES: asserts

2026-03-11 10:03:01 +01:00

Thumb

[ARM] Explicitly mark certain instructions as having no side effects. (#182771)

2026-03-01 09:33:58 +00:00

Thumb2

[ARM] Use FPRegs for fastcc calling convention detection. (#184593)

2026-03-11 13:52:56 +00:00

VE

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WebAssembly

[WebAssembly][FastISel] Fold AND mask operations into ZExt load (#183743)

2026-03-11 11:30:48 +09:00

WinCFGuard

[win] Control Flow Guard: Don't set the GuardCF COFF feature if the checks are missing (#182205)

2026-02-19 10:21:53 -08:00

WinEH

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X86

[X86] Improve handling of i512 SRL(SIGN_BIT, Amt) (#185896)

2026-03-12 08:40:49 +00:00

XCore

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Xtensa

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