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llvm-project/llvm/test/CodeGen/RISCV
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Liao Chunyu 74f5dd5c34
[RISCV]Lower one active interleaved load to normal segmented load (#185602) 
There’s an optimization for deinterleave loads in
`RISCVTargetLowering::PerformDAGCombine`.

We can generate a normal segmented load and 
let DAGCombine optimize it into vlse.
2026-03-11 18:08:32 +08:00
..
GlobalISel
[RISCV] Sink instructions so AVL dominates in RISCVVLOptimizer (#184155)
2026-03-04 05:46:26 +00:00
intrinsics
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rvv
[RISCV]Lower one active interleaved load to normal segmented load (#185602)
2026-03-11 18:08:32 +08:00
abds-neg.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
abds.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
abdu-neg.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
abdu.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
add_sext_shl_constant.ll
[RISCV] Don't commute with shift if XAndesPerf is enabled (#142920)
2025-06-06 11:08:23 +08:00
add_shl_constant.ll
[RISCV] Don't commute with shift if XAndesPerf is enabled (#142920)
2025-06-06 11:08:23 +08:00
add-before-shl.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
add-imm64-to-sub.ll
[RISCV][NFC] Fix UBSan issue in ISel (#181422)
2026-02-13 14:26:24 -08:00
add-imm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
addc-adde-sube-subc.ll
…
addcarry.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
addimm-mulimm.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
addrspacecast.ll
…
aext-to-sext.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
aext.ll
…
align-loops.ll
…
align.ll
…
alloca.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
allow-check.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
alu8.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
alu16.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
alu32.ll
…
alu64.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
analyze-branch.ll
…
and-add-lsr.ll
…
and-negpow2-cmp.ll
[RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW during selectSETCC. (#162614)
2025-10-14 08:45:00 +08:00
and-shl.ll
[RISCV] Remove artificial restriction on ShAmt from (shl (and X, C2), C) -> (srli (slli X, C4), C4-C) isel. (#143010)
2025-06-05 17:48:35 -07:00
and.ll
…
arith-with-overflow.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
atomic-cmpxchg-branch-on-result.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomic-fence.ll
[RISCV][LLVM] Enable atomics for 'Zalrsc' (#163672)
2025-10-21 09:33:19 -07:00
atomic-load-store.ll
[RISCV]Remove experimental from Zalasr (#177120)
2026-01-22 17:30:38 +08:00
atomic-load-zext.ll
[RISCV]Remove experimental from Zalasr (#177120)
2026-01-22 17:30:38 +08:00
atomic-rmw-discard.ll
[RISCV] Enable select optimization by default (#178394)
2026-02-10 16:19:01 +08:00
atomic-rmw-minmax.ll
[RISCV] 'Zalrsc' may permit non-base instructions (#165042)
2025-10-28 12:51:11 -07:00
atomic-rmw-sub.ll
[RISCV][LLVM] Enable atomics for 'Zalrsc' (#163672)
2025-10-21 09:33:19 -07:00
atomic-rmw.ll
[RISCV][LLVM] Enable atomics for 'Zalrsc' (#163672)
2025-10-21 09:33:19 -07:00
atomic-signext.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
atomicrmw-cond-sub-clamp.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
atomicrmw-uinc-udec-wrap.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
attributes-andes.ll
[RISCV] Add MC layer support for Andes XAndesVSIntH extension. (#159514)
2025-09-23 06:03:30 +00:00
attributes-module-flag.ll
…
attributes-qc.ll
[RISCV] Combine Xqci Extensions in Arch Strings (#181033)
2026-02-12 13:50:57 -08:00
attributes-sifive.ll
[RISCV] Add Xsfmm32a shorthand extension. (#181957)
2026-02-17 21:18:52 -08:00
attributes-thead.ll
[RISCV] Split the attribute test for THead to attributes-thead.ll. NFC.
2025-09-01 13:14:27 +08:00
attributes.ll
[RISCV][MC] Add support of Zvzip extension (#185614)
2026-03-11 14:22:02 +08:00
avgceils.ll
…
avgceilu.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
avgfloors.ll
…
avgflooru.ll
[TargetLowering][RISCV] Disable the special illegal type expansion of ISD::AVGFLOORU on RV32 (#181073)
2026-02-25 23:26:16 -08:00
bf16-promote.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bfloat-arith.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
bfloat-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
bfloat-convert-half.ll
[RISCV] Add isel for bitcasting between bfloat and half types (#158828)
2025-09-17 12:10:47 -07:00
bfloat-convert.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
bfloat-fcmp.ll
…
bfloat-frem.ll
…
bfloat-imm.ll
[RISCV] Set riscv-fpimm-cost threshold to 3 by default (#159352)
2025-09-24 10:50:01 +01:00
bfloat-isnan.ll
…
bfloat-mem.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
bfloat-select-fcmp.ll
…
bfloat-select-icmp.ll
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bfloat.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bigendian-double-bitmanip.ll
[RISCV] Handle codegen for Big Endian (#172668)
2025-12-19 19:35:01 +01:00
bigendian-f64-call.ll
[RISCV] Handle codegen for Big Endian (#172668)
2025-12-19 19:35:01 +01:00
bigendian-load-store.ll
[RISCV] Handle codegen for Big Endian (#172668)
2025-12-19 19:35:01 +01:00
bitextract-mac.ll
[RISCV] Add TH_EXT(U) to hasAllNBitUsers in RISCVOptWInstrs. (#157544)
2025-09-09 08:47:39 -07:00
bitreverse-shift.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
bittest.ll
[RISCV] Add isel pattern (setlt (shl X, 32), 0) -> srliw. (#178765)
2026-01-29 21:26:40 -08:00
blockaddress.ll
…
branch_zero.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
branch-on-zero.ll
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" (#169219)
2025-11-24 09:27:25 +08:00
branch-opt.ll
[RISCV] Add (BSETI x0, 11) to isLoadImm for optimizeCondBranch (#180820)
2026-02-10 12:32:36 -08:00
branch-opt.mir
[RISCV] Fix a correctness issue in optimizeCondBranch. Prevent optimizing compare with x0. NFC (#145440)
2025-06-24 15:45:06 -07:00
branch-rel.mir
[BranchRelaxation] Fix invalid branch generation in branch-relaxation (#162065)
2025-10-15 19:31:50 +03:00
branch-relaxation-rv32.ll
[RISCV] Inserting indirect jumps with X7 for Zicfilp (#170683)
2025-12-05 11:54:40 +08:00
branch-relaxation-rv32e.ll
[RISCV] Use X9 instead of X27 in RISCVInstrInfo::insertIndirectBranch for RVE (#139214)
2025-05-09 08:41:14 -07:00
branch-relaxation-rv64.ll
[RISCV] Inserting indirect jumps with X7 for Zicfilp (#170683)
2025-12-05 11:54:40 +08:00
branch.ll
[CodeGen] Limit number of analyzed predecessors
2025-06-20 11:23:00 +02:00
bswap-bitreverse.ll
[RISCV] Support scalar bitreverse using P extension rev instruction. (#183245)
2026-02-25 12:42:59 -08:00
bswap-shift.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
byval.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
callee-saved-fpr32s.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
callee-saved-fpr64s.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
callee-saved-gprs.ll
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
calleetypeid-directcall-mismatched.ll
[llvm] Extract and propagate callee_type metadata
2025-07-30 14:56:39 -07:00
calling-conv-half.ll
[RISCV] Set riscv-fpimm-cost threshold to 3 by default (#159352)
2025-09-24 10:50:01 +01:00
calling-conv-ilp32-ilp32f-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-ilp32.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32d.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32e.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-ilp32f-ilp32d-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64-lp64f-common.ll
…
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
calling-conv-lp64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-p-ext-vector.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
calling-conv-preserve-most.ll
[RISCV] Support PreserveMost calling convention (#148214)
2025-07-30 16:30:48 +08:00
calling-conv-rv32f-ilp32.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-rv32f-ilp32e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-sext-zext.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-vector-float.ll
…
calling-conv-vector-on-stack.ll
…
calls.ll
[RISCV][GISel] Use the correct calling convention during call lowering (#142148)
2025-05-30 18:55:32 +02:00
callsite-emit-calleetypeid-tailcall.ll
[llvm] Extract and propagate callee_type metadata
2025-07-30 14:56:39 -07:00
callsite-emit-calleetypeid.ll
[llvm] Extract and propagate callee_type metadata
2025-07-30 14:56:39 -07:00
cfi-multiple-locations.mir
[CFIInstrInserter] Fix a test. (#176048)
2026-01-15 04:17:17 -08:00
clear-cache.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
clmul.ll
[TargetLowering][RISCV] Avoid ISD::MUL in expandCLMUL if hasBitTest or MUL requires a library call. (#182389)
2026-02-22 19:20:16 -08:00
clmulh.ll
[TargetLowering][RISCV] Avoid ISD::MUL in expandCLMUL if hasBitTest or MUL requires a library call. (#182389)
2026-02-22 19:20:16 -08:00
clmulr.ll
[TargetLowering][RISCV] Avoid ISD::MUL in expandCLMUL if hasBitTest or MUL requires a library call. (#182389)
2026-02-22 19:20:16 -08:00
cm_mvas_mvsa.ll
…
cm_mvas_mvsa.mir
…
cmov-branch-opt.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
cmp-bool.ll
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codemodel-lowering.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
combine-clmul.ll
[DAG] visitCLMUL - fold (clmul x, c_pow2) -> (shl x, log2(c_pow2)) (#184049)
2026-03-02 10:52:51 +00:00
combine-storetomstore.ll
[DAG] Combine store + vselect to masked_store (#145176)
2025-08-04 19:05:36 +05:30
compress-double.ll
…
compress-float.ll
…
compress-inline-asm.ll
…
compress-opt-branch.ll
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compress-opt-select.ll
[RISCV] Enable SelectCompressOpt with HasStdExtZca. (#179601)
2026-02-03 21:56:48 -08:00
compress.ll
…
condbinops.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
condops.ll
[RISCV] Remove srl from (srl (and X, (1 << C)), C) used as czero.eqz/nez condition. (#182598)
2026-02-20 18:00:07 -08:00
constpool-known-bits.ll
Re-commit "[RISCV] Properly support RISCVISD::LLA in getTargetConstantFromLoad. (#145112)"
2025-06-21 10:18:49 -07:00
convert-highly-predictable-select-to-branch.ll
…
copy-frameindex.mir
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
copyprop.ll
…
copysign-casts.ll
[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)
2026-03-02 20:06:10 -08:00
csr-first-use-cost.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
ctlz-cttz-ctpop.ll
[SelectionDAG] Support integer types with multiple registers in ComputePHILiveOutRegInfo. (#172081)
2025-12-13 13:24:41 -08:00
ctz_zero_return_test.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
debug-line.ll
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
di-assignment-tracking-vector.ll
[DebugInfo] Handle additional types of stores in assignment tracking (#129070)
2025-04-22 17:14:25 +01:00
disable-tail-calls.ll
…
disjoint.ll
…
div_minsize.ll
[CodeGen] Expand power-of-2 div/rem at IR level in ExpandIRInsts. (#180654)
2026-02-25 22:54:34 +01:00
div-by-constant.ll
[SelectionDAG] Optimize 32-bit udiv with 33-bit magic constants on 64-bit targets (#181288)
2026-03-06 15:18:34 -08:00
div-pow2.ll
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div.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
double_reduct.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
double-arith-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
double-arith.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
double-bitmanip-dagcombines.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
double-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
double-calling-conv.ll
[RISCV] Replace undef with poison, NFC (#157396)
2025-09-09 15:16:16 +08:00
double-convert-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
double-convert.ll
[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)
2026-03-02 20:06:10 -08:00
double-fcmp-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
double-fcmp.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
double-frem.ll
…
double-imm.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
double-intrinsics-strict.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
double-intrinsics.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
double-isnan.ll
…
double-maximum-minimum.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
double-mem.ll
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
double-previous-failure.ll
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
double-round-conv-sat.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
double-round-conv.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
double-select-fcmp.ll
[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)
2026-03-02 20:06:10 -08:00
double-select-icmp.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
double-stack-spill-restore.ll
[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)
2026-03-02 20:06:10 -08:00
double-zfa.ll
[SDAG] Remove most non-canonical libcall handing (#171288)
2025-12-10 11:45:26 +01:00
dso_local_equivalent.ll
AsmPrinter: Remove ELF's special lowerRelativeReference for unnamed_addr function; use lowerDSOLocalEquivalent in more cases
2025-04-08 10:11:20 -07:00
dwarf-eh.ll
[TargetLoweringObjectFile] Handle riscv BE (#155166)
2025-08-28 17:04:47 +02:00
early-clobber-tied-def-subreg-liveness.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
eh-dwarf-cfa.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
elf-preemption.ll
…
emit-x8-as-fp.ll
[RISCV][MC] Emit x8 as fp instead of s0 (#135500)
2025-04-14 14:48:47 +08:00
emutls.ll
…
exception-pointer-register.ll
…
fastcc-bf16.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-float.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-half.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-int.ll
…
fastcc-without-f-reg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
features-info.ll
[RISCV][MC] Add support of Zvzip extension (#185614)
2026-03-11 14:22:02 +08:00
fixed-csr.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
fixups-diff.ll
…
fli-licm.ll
…
float-arith-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
float-arith.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
float-bit-preserving-dagcombines.ll
[RISCV] Undo fneg (fmul x, y) -> fmul x, (fneg y) transform (#157388)
2025-09-09 01:30:33 +00:00
float-bitmanip-dagcombines.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
float-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
float-convert-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
float-convert.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
float-fcmp-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
float-fcmp.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
float-frem.ll
…
float-imm.ll
[RISCV] Simplify RUN lines in float-imm.ll and half-imm.ll. NFC.
2025-10-07 14:50:31 +08:00
float-intrinsics-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
float-intrinsics.ll
[RISCV] Add isel pattern (setlt (shl X, 32), 0) -> srliw. (#178765)
2026-01-29 21:26:40 -08:00
float-isnan.ll
…
float-maximum-minimum.ll
[SelectionDAG] Remove NoNaNsFPMath uses (#183448)
2026-03-10 14:06:42 +08:00
float-mem.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
float-round-conv-sat.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
float-round-conv.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
float-select-fcmp.ll
[RISCV] Move CascadeSelect test into float/half/double-select-fcmp.ll. NFC
2025-06-26 09:46:14 -07:00
float-select-icmp.ll
…
float-select-verify.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
float-zfa.ll
[SDAG] Remove most non-canonical libcall handing (#171288)
2025-12-10 11:45:26 +01:00
flt-rounds.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
fma-combine.ll
[SDAG] Check for nsz in DAG.canIgnoreSignBitOfZero() (#178905)
2026-02-01 15:58:38 +00:00
fmax-fmin.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
fold-addi-loadstore-zilsd.ll
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
fold-addi-loadstore.ll
[RISCV] Add support for QC.E.LI in RISCVMergeBaseOffset (#175310)
2026-01-12 06:30:39 +05:30
fold-binop-into-select-return-constant.ll
…
fold-binop-into-select.ll
…
fold-masked-merge.ll
Reland "[SelectionDAG] Make (a & x) | (~a & y) -> (a & (x ^ y)) ^ y available for all targets" (#143651)
2025-06-11 15:56:37 +08:00
fold-mem-offset-zilsd.ll
[RISCV] Add Zilsd to RISCVFoldMemOffset (#176544)
2026-01-19 11:19:30 +05:30
fold-mem-offset.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
fold-mem-offset.mir
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
2025-04-22 19:24:29 -07:00
forced-atomics.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
fp16-promote.ll
…
fp128.ll
[RISCV] Support scalar llvm.fmodf intrinsic. (#161743)
2025-10-03 08:05:24 -07:00
fp-fcanonicalize.ll
[RISCV] Fix fcanonicalize for Z*inx (#175984)
2026-01-15 23:03:38 -08:00
fpclamptosat.ll
Revert "[RISCV] Support RISCV BitInt larger than 128 (#175515)" (#178311)
2026-01-29 07:16:14 -08:00
fpenv-xlen.ll
[RISCV][FPEnv] Lowering of fpmode intrinsics (#148569)
2025-07-16 16:02:15 +07:00
fpenv.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
frame-info.ll
…
frame.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
frameaddr-returnaddr.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
frm-dependency.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
frm-write-in-loop.ll
[RISCV][FPEnv] Lowering of fpenv intrinsics (#141498)
2025-06-11 19:08:23 +07:00
get-register-invalid.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
get-register-noreserve.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
get-register-reserve.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
get-setcc-result-type.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
ghccc-nest.ll
…
ghccc-rv32.ll
…
ghccc-rv64.ll
…
ghccc-without-f-reg.ll
…
global-merge-minsize-smalldata-nonzero.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
global-merge-minsize-smalldata-zero.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
global-merge-minsize.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
global-merge-offset.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
global-merge.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
graalcc.ll
…
half-arith-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
half-arith.ll
fix llvm.fma.f16 double rounding issue when there is no native support (#171904)
2025-12-17 22:03:01 +01:00
half-bitmanip-dagcombines.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
half-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
half-convert-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
half-convert.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
half-fcmp-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
half-fcmp.ll
…
half-frem.ll
…
half-imm.ll
[RISCV] Simplify RUN lines in float-imm.ll and half-imm.ll. NFC.
2025-10-07 14:50:31 +08:00
half-intrinsics.ll
fix llvm.fma.f16 double rounding issue when there is no native support (#171904)
2025-12-17 22:03:01 +01:00
half-isnan.ll
…
half-maximum-minimum.ll
[SelectionDAG] Remove NoNaNsFPMath uses (#183448)
2026-03-10 14:06:42 +08:00
half-mem.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
half-round-conv-sat.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
half-round-conv.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
half-select-fcmp.ll
[RISCV] Set riscv-fpimm-cost threshold to 3 by default (#159352)
2025-09-24 10:50:01 +01:00
half-select-icmp.ll
…
half-zfa-fli.ll
[RISCV] Set riscv-fpimm-cost threshold to 3 by default (#159352)
2025-09-24 10:50:01 +01:00
half-zfa.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
hoist-global-addr-base.ll
[RISCV] Detect QC_E_ADDAI and fold in RISCVMergeBaseOffset (#175496)
2026-01-12 22:43:38 +05:30
hwasan-check-memaccess.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
i32-icmp.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
i64-icmp.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
iabs.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
icmp-non-byte-sized.ll
[RISCV] Support non-power-of-2 types when expanding memcmp
2025-06-18 16:11:18 +08:00
idiv_large.ll
[DAG] Fold (X +/- Y) & Y --> ~X & Y when Y is a power of 2 (or zero). (#181677)
2026-02-18 12:19:21 +00:00
imm-cse.ll
…
imm.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
indirectbr.ll
…
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-bf-constraint-f.ll
[RISCV] Support 'f' Inline Assembly Constraint for bfloat16 (#184566)
2026-03-05 20:21:22 -08:00
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-d-modifier-N.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-f-modifier-N.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-fixed-v-constraint.ll
[RISCV][llvm] Support fixed-length vector inline assembly constraints (#150724)
2025-08-18 03:36:12 +00:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
[RISCV] Check the VT for R and cR inline asm constraints is 2*xlen. (#137749)
2025-04-29 08:12:32 -07:00
inline-asm-mem-constraint-2.ll
…
inline-asm-mem-constraint.ll
[ARM,AArch64] Don't put BTI at asm goto branch targets (#141562)
2025-06-03 08:44:13 +01:00
inline-asm-s-constraint-error.ll
…
inline-asm-s-constraint.ll
…
inline-asm-v-constraint.ll
…
inline-asm-xsfvcp.ll
…
inline-asm-zdinx-constraint-r.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
inline-asm-zfh-constraint-f.ll
…
inline-asm-zfh-modifier-N.ll
…
inline-asm-zfinx-constraint-r.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-zhinx-constraint-r.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-option-directive.ll
…
instruction-count-remark.mir
Register assembly printer passes (#138348)
2025-05-06 18:01:17 -07:00
interrupt-attr-args-error.ll
[RISCV] Mark More Fatal Errors as Usage/Internal (#154876)
2025-08-22 11:57:17 -07:00
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
[RISCV] Mark More Fatal Errors as Usage/Internal (#154876)
2025-08-22 11:57:17 -07:00
interrupt-attr-nocall.ll
…
interrupt-attr-ret-error.ll
[RISCV] Mark More Fatal Errors as Usage/Internal (#154876)
2025-08-22 11:57:17 -07:00
interrupt-attr.ll
[RISCV][llvm] Handle vector callee saved register correctly (#149467)
2025-07-21 17:49:34 -07:00
ipra.ll
[RISCV] Implement getIPRACSRegs hook (#125586)
2025-02-04 10:02:42 -03:00
isel-optnone.ll
…
jumptable-swguarded.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
jumptable.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
kcfi-isel-mir.ll
…
kcfi-mir.ll
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
kcfi-patchable-function-prefix.ll
…
kcfi.ll
[RISCV,test] Replace -riscv-no-aliases with -M no-aliases
2025-04-08 19:42:43 -07:00
lack-of-signed-truncation-check.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
large-codemodel-sections.ll
[RISCV] Put Large Code Model Constant Pools in .text (#151393)
2026-03-02 13:17:06 -08:00
large-stack.ll
…
legalize-fneg.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
libcall-tail-calls.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
lit.local.cfg
…
live-sp.mir
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
llvm.exp10.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
llvm.frexp.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
load-narrow-shift-mask-combine.ll
[RISCV] Introduce new AND combine to expose additional load narrowing opportunities (#170483)
2025-12-21 07:14:09 +00:00
load-setcc-combine.ll
…
load-store-pair.ll
[RISCV] Generate MIPS load/store pair instructions (#124717)
2025-03-07 09:21:36 +01:00
local-stack-slot-allocation.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
loop-strength-reduce-add-cheaper-than-mul.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
loop-strength-reduce-loop-invar.ll
…
lpad.ll
[RISCV] Emit lpad for function with returns-twice attribute (#170520)
2025-12-04 13:25:57 +08:00
lrint-conv.ll
[SelectionDAG,GISel] Add f16 soft promotion for lrint, lround, llrint, and llround (#152684)
2026-01-08 12:40:10 +01:00
lsr-legaladdimm.ll
…
machine-combiner-mir.ll
[CodeGen] Drop disjoint flag when reassociating (#156218)
2025-08-31 11:23:15 -07:00
machine-combiner-strategies.ll
…
machine-combiner.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
machine-combiner.mir
…
machine-copyprop-noop-removal.mir
[MachineCopyPropagation] Remove logic to recognise and delete no-op moves produced after forwarded uses (#167336)
2025-11-11 15:44:54 +00:00
machine-copyprop-simplifyinstruction.mir
[MCP] Handle iterative simplification during forward copy prop (#140267)
2025-06-02 11:21:41 -07:00
machine-cp.mir
…
machine-cse.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
machine-outliner-and-machine-copy-propagation.ll
…
machine-outliner-call-reg-live-across.mir
[RISC-V] Fix outliner candidate analysis (#177126)
2026-01-26 19:47:18 +01:00
machine-outliner-call-x5-liveout.mir
[RISCV] [MachineOutliner] Analyze all candidates (#127659)
2025-02-21 12:53:13 +05:30
machine-outliner-call.ll
…
machine-outliner-cfi.mir
[RISCV] Support outlining of CFI instructions in the machine outliner (#166149)
2025-11-07 12:35:39 +05:30
machine-outliner-leaf-descendants.ll
…
machine-outliner-lpad.ll
[RISCV] Exclude LPAD in machine outliner (#157220)
2025-09-09 22:50:22 +08:00
machine-outliner-patchable.ll
…
machine-outliner-position.mir
…
machine-outliner-throw.ll
…
machine-pipeliner.ll
RISCV: Enable terminal rule (#165961)
2025-11-10 20:08:33 -08:00
machine-sink-load-immediate.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
machinelicm-address-pseudos.ll
[NFC] Move fusion- to start of Fusion Feature Name (#185146)
2026-03-06 21:57:48 -08:00
machinelicm-constant-phys-reg.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
…
machineoutliner-x5.mir
…
machineoutliner.mir
…
MachineSink-implicit-x0.mir
[CodeGen][NewPM] Port MachineSink to NPM (#115434)
2025-03-03 15:49:37 +05:30
macho-relocs.ll
[RISC-V][Mach-O] Add codegen support for Mach-O object format. (#178263)
2026-02-02 14:11:27 -08:00
macro-fusion-add-mem.mir
[RISCV] Add macro fusion support for spacemit-x100 (#178594)
2026-02-04 14:25:52 +08:00
macro-fusion-logic-imm-reg.mir
[RISCV] Add macro fusion support for spacemit-x100 (#178594)
2026-02-04 14:25:52 +08:00
macro-fusion-logic-reg-imm.mir
[RISCV] Add macro fusion support for spacemit-x100 (#178594)
2026-02-04 14:25:52 +08:00
macro-fusion-logic-reg-reg.mir
[RISCV] Add macro fusion support for spacemit-x100 (#178594)
2026-02-04 14:25:52 +08:00
macro-fusion-lui-addi.ll
[NFC] Move fusion- to start of Fusion Feature Name (#185146)
2026-03-06 21:57:48 -08:00
macro-fusion-mul-add.mir
[RISCV] Add macro fusion support for spacemit-x100 (#178594)
2026-02-04 14:25:52 +08:00
macro-fusion-shift-bit-extract.mir
[RISCV] Add macro fusion support for spacemit-x100 (#178594)
2026-02-04 14:25:52 +08:00
macro-fusions.mir
[NFC] Move fusion- to start of Fusion Feature Name (#185146)
2026-03-06 21:57:48 -08:00
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
…
make-compressible-xqci.mir
[RISCV] Adjust base cost for Xqcilo loads/stores in RISCVMakeCompressible (#175572)
2026-01-13 06:34:18 +05:30
make-compressible-zbc-zhinx.mir
…
make-compressible-zbc.mir
…
make-compressible-zfinx.mir
…
make-compressible-zilsd.mir
[RISCV] Use PADD_DW instead of ADDD for GPRPair copy on RV32 with P extension (#181316)
2026-02-13 09:41:08 -08:00
make-compressible.mir
…
mask-variable-shift.ll
[RISCV] Implement shouldFoldMaskToVariableShiftPair (#166159)
2025-11-05 10:22:11 +05:30
mem64.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
mem.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
memcmp-optsize.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
memcmp.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
memcpy-inline.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
memcpy.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
memmove.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
memset-inline.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
memset-pattern.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
min-max.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
mir-target-flags.ll
…
misched-load-clustering.ll
[RISCV] add load/store misched/PostRA subtarget features (#149409)
2025-08-06 09:08:25 -07:00
misched-mem-clustering.mir
[RISCV] add load/store misched/PostRA subtarget features (#149409)
2025-08-06 09:08:25 -07:00
misched-postra-direction.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
misched-store-clustering.ll
[RISCV] add load/store misched/PostRA subtarget features (#149409)
2025-08-06 09:08:25 -07:00
miss-sp-restore-eh.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
module-elf-flags.ll
…
module-target-abi2.ll
…
module-target-abi3.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
module-target-abi.ll
…
mul-expand.ll
[RISCV] Expand constant multiplication for targets without M extension (#137195)
2025-05-16 09:40:11 +08:00
mul.ll
[DAGCombiner] Don't peek through bitcast when checking isMulAddWithConstProfitable (#171056)
2025-12-08 22:09:12 +08:00
musttail-call.ll
[RISCV] improve musttail support (#170547)
2026-02-11 17:27:51 +01:00
musttail.ll
[RISCV] improve musttail support (#170547)
2026-02-11 17:27:51 +01:00
naked-fn-with-frame-pointer.ll
…
narrow-shl-cst.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
neg-abs.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
nest-register.ll
[RISCV] Guard the alternative static chain register use on ILP32E/LP64E (#142715)
2025-06-12 02:24:10 +08:00
nomerge.ll
…
nontemporal-scalable.ll
…
nontemporal.ll
…
note-gnu-property-zicfiss.ll
[RISCV] Improvements to .note.gnu.property section. (#151436)
2025-08-04 09:20:25 -07:00
O0-pipeline.ll
[NFC][CodeGen] Rename CallBrPrepare pass to InlineAsmPrepare (#181547)
2026-02-17 15:37:35 -08:00
O3-pipeline.ll
[NFC][CodeGen] Rename CallBrPrepare pass to InlineAsmPrepare (#181547)
2026-02-17 15:37:35 -08:00
opt-w-instrs-p-ext.mir
[RISCV] Add MERGE, MVM, and MVMN to isSignExtendedW in RISCVOptWInstrs. (#183433)
2026-02-25 21:26:13 -08:00
opt-w-instrs.mir
[RISCV][NFC] Prepare for Short Forward Branch of branches with immediates (#182456)
2026-03-03 12:38:00 +05:30
option-exact-inlineasm.ll
[RISCV] Support .option {no}exact (#122483)
2025-03-26 11:14:16 -07:00
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax-relocation.ll
[RISCV] Mark More Relocs as Relaxable (#151422)
2026-01-08 09:28:29 -08:00
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
or-is-add.ll
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
2025-02-25 10:04:57 -08:00
orc-b-patterns.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
out-of-reach-emergency-slot.mir
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
overflow-intrinsic-optimizations.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
overflow-intrinsics.ll
[CodeGenPrepare] sinkCmpExpression - don't sink larger than legal integer comparisons (#166778)
2025-11-10 14:39:43 +00:00
patchable-function-entry.ll
[RISCV,test] Replace -riscv-no-aliases with -M no-aliases
2025-04-08 19:42:43 -07:00
pei-crash.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
pic-models.ll
…
pipeline-options.ll
[RISCV] Add an option to enable CFIInstrInserter. (#164477)
2025-11-18 02:46:43 -05:00
poison-legalization.ll
Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison value in the IR." (#135056)
2025-04-10 11:29:14 -04:00
postra-copy-expand.mir
[RISCV] Attach an implicit source operand on vector copies (#126155)
2025-02-08 16:25:27 -08:00
pr40333.ll
…
pr51206.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr53662.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
pr55201.ll
…
pr56110.ll
…
pr56457.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
pr58025.ll
…
pr58286.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr58511.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr63365.ll
…
pr63816.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr64503.ll
…
pr64645.ll
…
pr64772.ll
…
pr64935.ll
…
pr65025.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
pr66603.ll
…
pr68855.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr69586.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
pr80052.mir
…
pr84200.ll
…
pr84653_pr85190.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
pr88365.ll
…
pr90652.ll
…
pr90730.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr92193.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
pr94145.ll
…
pr94265.ll
…
pr95271.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr95284.ll
…
pr96366.ll
…
pr97304.ll
…
pr101786.ll
[CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (#102731)
2025-04-23 08:54:10 +03:00
pr135206.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
pr142004.ll
[DAGCombiner] Teach SearchForAndLoads to handle an AND with 2 constant operands. (#142062)
2025-05-30 16:00:43 -07:00
pr145360.ll
[RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB (#166757)
2025-11-13 18:11:53 +01:00
pr145363.ll
[SelectionDAG] Combine range metadata when loads are CSEd. (#146026)
2025-06-27 08:58:06 -07:00
pr148084.ll
[RISCV][llvm] Rename zvqdotq to zvdot4a8i (#179393)
2026-02-24 04:44:07 +00:00
pr153598.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
pr158121.ll
[RISCV] Check the types are the same for folding (sub 0, (setcc x, 0, setlt)) to (sra x, xlen - 1) (#158179)
2025-09-15 09:30:08 +08:00
pr176001.ll
[RISCV] Print MIR comments for AVL and VEC_RM operands (#179542)
2026-02-03 22:11:22 +00:00
prefer-w-inst.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
prefer-w-inst.mir
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
prefetch.ll
[RISCV] Relax codegen predicates for HINT-based instructions (#179872)
2026-03-02 17:24:22 +08:00
print-pipeline-passes.ll
[RISCV] Add -print-pipeline-passes test as follow up to #156798. NFC (#157011)
2025-09-05 08:07:39 -07:00
prolog-epilogue.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
push-pop-opt-crash.ll
[RISCV] Update unrelated bad code from test case
2025-03-19 11:09:49 -07:00
push-pop-popret.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
qci-interrupt-attr-fpr.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
qci-interrupt-attr.ll
[RISCV] Mark Xqccmp as not experimental (#175066)
2026-01-10 07:50:29 -08:00
rda-entry-bb-is-a-loop.mir
[ReachingDefAnalysis] Fix printing of RDA results. (#176474)
2026-01-19 12:03:51 -08:00
rda-liveins.mir
[ReachingDefAnalysis] Print basic blocks. (#175568)
2026-01-14 06:29:31 -08:00
rda-stack.mir
[ReachingDefAnalysis] Print basic blocks. (#175568)
2026-01-14 06:29:31 -08:00
readcyclecounter.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
readsteadycounter.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
reassoc-shl-addi-add.ll
[RISCV] Simplify and remove unrelated testcases in reassoc-shl-addi-add.ll. NFC.
2025-06-10 19:10:48 +08:00
reduce-unnecessary-extension.ll
…
reduction-formation.ll
…
redundant-copy-elim.ll
[RISCV] Add support for Zibi experimental extension in RISCVRedundantCopyElimination (#174920)
2026-01-09 14:00:53 +08:00
redundant-copy-from-tail-duplicate.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
regalloc-last-chance-recoloring-failure.ll
[RISCV] Sink instructions so AVL dominates in RISCVVLOptimizer (#184155)
2026-03-04 05:46:26 +00:00
relative-reloc.ll
AsmPrinter: Remove ELF's special lowerRelativeReference for unnamed_addr function; use lowerDSOLocalEquivalent in more cases
2025-04-08 10:11:20 -07:00
relax-per-target-feature.ll
…
rem.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
remat.ll
[RISCV] Enable rematerialization for scalar loads (#166774)
2025-11-24 18:14:19 +08:00
renamable-copy.mir
…
repeated-fp-divisors.ll
[RISCV] Set riscv-fpimm-cost threshold to 3 by default (#159352)
2025-09-24 10:50:01 +01:00
replace-with-veclib-sleef-scalable.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegen-prepare-atp.ll
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riscv-codegenprepare-asm.ll
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
riscv-codegenprepare.ll
[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)
2025-11-19 06:51:18 +00:00
riscv-func-target-feature.ll
…
riscv-macho.ll
[RISCV] Add basic Mach-O triple support. (#141682)
2026-01-05 23:18:48 +00:00
riscv-promote-constant.ll
[RISCV] Introduce pass to promote double constants to a global array (#160536)
2025-11-05 14:31:17 +00:00
riscv-scavenge-crash-2nd-pass-rv32.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
riscv-scavenge-crash-2nd-pass-rv64.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
riscv-tail-dup-size.ll
…
riscv-zihintpause.ll
[RISCV] Relax codegen predicates for HINT-based instructions (#179872)
2026-03-02 17:24:22 +08:00
rnmi-interrupt-attr-error.ll
[RISCV] Support resumable non-maskable interrupt handlers (#148134)
2025-08-04 10:54:50 +02:00
rnmi-interrupt-attr.ll
[RISCV] Support resumable non-maskable interrupt handlers (#148134)
2025-08-04 10:54:50 +02:00
rotl-rotr.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32-fuchsia.ll
…
rv32-inline-asm-pairs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32-merge-non-arg-reg.mir
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
rv32-move-merge.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll
[RISCV] Remove the TODO for lowering f32 libcall on RV64 with lp64 abi. (NFC)
2025-03-07 10:52:04 +08:00
rv32i-rv64i-half.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv32p.ll
[RISCV][P-ext] Custom legalize i64 SHL to WSLL(I)/WSLA(I) (#185079)
2026-03-06 15:27:57 -08:00
rv32xandesperf.ll
[RISCV] Implement Clang Builtins for XAndesPerf Extension (#147018)
2025-12-17 08:43:37 +00:00
rv32xtheadba.ll
[RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB (#166757)
2025-11-13 18:11:53 +01:00
rv32xtheadbb.ll
[SelectionDAG] Support integer types with multiple registers in ComputePHILiveOutRegInfo. (#172081)
2025-12-13 13:24:41 -08:00
rv32xtheadbs.ll
…
rv32zba.ll
[RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB (#166757)
2025-11-13 18:11:53 +01:00
rv32zbb-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zbb-zbkb.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zbb.ll
[SelectionDAG] Support integer types with multiple registers in ComputePHILiveOutRegInfo. (#172081)
2025-12-13 13:24:41 -08:00
rv32zbc-intrinsic.ll
[RISCV] Replace RISCVISD::CLMUL* with ISD::CLMUL*. (#177386)
2026-01-22 09:39:44 -08:00
rv32zbc-zbkc-intrinsic.ll
[RISCV] Replace riscv.clmul intrinsic with llvm.clmul (#178092)
2026-01-26 21:12:48 -08:00
rv32zbkb-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zbkb.ll
[RISCV] Select (and (shl X, 8), 0xff00) -> (packh zero, X) (#170654)
2025-12-04 20:25:16 +01:00
rv32zbkx-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zbs.ll
[RISCV] Add ISEL pattern to convert add (shl -1, X), Y to sub Y, (bset zero, X) (#178601)
2026-01-29 15:11:21 +05:30
rv32zimop-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zknd-intrinsic-autoupgrade.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zknd-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zkne-intrinsic-autoupgrade.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zkne-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zknh-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zksed-intrinsic-autoupgrade.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zksed-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv32zksh-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-double-convert-strict.ll
…
rv64-double-convert.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-float-convert-strict.ll
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rv64-float-convert.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-half-convert-strict.ll
…
rv64-half-convert.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-inline-asm-pairs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-large-stack.ll
…
rv64-patchpoint.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-stackmap-args.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-stackmap-fp.ll
[RISCV] Mark FLH as canFoldAsLoad. (#165974)
2025-11-03 12:35:06 -08:00
rv64-stackmap-frame-setup.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-stackmap-nops.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-stackmap.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-statepoint-call-lowering-x1.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-statepoint-call-lowering-x2.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-statepoint-call-lowering.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-trampoline-cfi.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-trampoline.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64-typepromotion.ll
…
rv64d-double-convert-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64d-double-convert.ll
…
rv64e.ll
…
rv64f-float-convert-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64f-float-convert.ll
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rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv64i-double-softfloat.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64i-exhaustive-w-insts.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv64i-shift-sext.ll
[RISCV] Add computeKnownBitsForTargetNode for RISCVISD::SRAW. (#156191)
2025-08-30 18:27:18 -07:00
rv64i-single-softfloat.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
…
rv64p.ll
[LegalizeTypes] Emit FSHL/FSHR from ExpandShiftByConstant when Legal. (#180888)
2026-03-10 15:04:37 -07:00
rv64xandesperf.ll
[RISCV] Implement Clang Builtins for XAndesPerf Extension (#147018)
2025-12-17 08:43:37 +00:00
rv64xtheadba.ll
[RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB (#166757)
2025-11-13 18:11:53 +01:00
rv64xtheadbb.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64xtheadbs.ll
…
rv64zba.ll
[RISCV] Fold Zba-expanded (mul (shr exact X, C1), C2) (#168019)
2025-11-17 18:32:32 +01:00
rv64zbb-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zbb-zbkb.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zbb.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zbc-intrinsic.ll
[RISCV] Add signext attribute to llvm.clmul test caes in rv64zbc(-zbkc)-intrinsic.ll. NFC (#178236)
2026-01-27 14:39:21 -08:00
rv64zbc-zbkc-intrinsic.ll
[RISCV] Add signext attribute to llvm.clmul test caes in rv64zbc(-zbkc)-intrinsic.ll. NFC (#178236)
2026-01-27 14:39:21 -08:00
rv64zbkb-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zbkb.ll
[RISCV] Select (and (shl X, 8), 0xff00) -> (packh zero, X) (#170654)
2025-12-04 20:25:16 +01:00
rv64zbkx-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zbs.ll
[RISCV] Add ISEL pattern to convert add (shl -1, X), Y to sub Y, (bset zero, X) (#178601)
2026-01-29 15:11:21 +05:30
rv64zfh-half-convert-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zfh-half-convert.ll
…
rv64zfh-half-intrinsics.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zfhmin-half-convert-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zfhmin-half-convert.ll
…
rv64zfhmin-half-intrinsics.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zimop-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zknd-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zknd-zkne-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zkne-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zknh-intrinsic-autoupgrade.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zknh-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zksed-intrinsic-autoupgrade2.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zksed-intrinsic-autoupgrade.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zksed-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zksh-intrinsic-autoupgrade.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rv64zksh-intrinsic.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
rvp-ext-rv32.ll
[RISCV][P-ext] Only support sshlsat for splat immediate shift amounts. (#184886)
2026-03-06 12:24:14 -08:00
rvp-ext-rv64.ll
[RISCV][P-ext] Only support sshlsat for splat immediate shift amounts. (#184886)
2026-03-06 12:24:14 -08:00
rvp-unaligned-load-store.ll
[RISCV] Partial support for using PPAIRE.B/H to optimize unaligned load sequences. (#183423)
2026-02-25 21:25:23 -08:00
sadd_sat_plus.ll
[RISCV] Custom legalize i32 saddo/ssubo on RV64 to return a sign extended value for the data result. (#172112)
2025-12-14 22:33:01 -08:00
sadd_sat.ll
[RISCV] Custom legalize i32 saddo/ssubo on RV64 to return a sign extended value for the data result. (#172112)
2025-12-14 22:33:01 -08:00
saverestore-scs.ll
…
saverestore.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
scmp.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
sdata-sections.ll
…
sdiv-pow2-cmov.ll
…
select-and.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-bare.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
select-binop-identity.ll
[RISCV] Add a conditional-cmv-fusion RUN line to select-binop-identity.ll. NFC (#155950)
2025-08-28 19:35:58 -07:00
select-cc.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
select-cond.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
select-const.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
select-constant-xor.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
select-optimize-multiple.ll
[RISCV] Move CascadeSelect test into float/half/double-select-fcmp.ll. NFC
2025-06-26 09:46:14 -07:00
select-optimize-multiple.mir
…
select-or.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-pseudo-merge-with-stack-adj.ll
[RISCV] Don't merge pseudo selects with stack adjustment instrs in between (#160105)
2025-09-24 11:46:18 +03:00
select-to-and-zext.ll
[RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW during selectSETCC. (#162614)
2025-10-14 08:45:00 +08:00
select-zbb.ll
[RISCV] Support umin/umax in tryFoldSelectIntoOp (#157548)
2025-09-12 10:02:00 -07:00
select.ll
[RISCV] Remove srl from (srl (and X, (1 << C)), C) used as czero.eqz/nez condition. (#182598)
2026-02-20 18:00:07 -08:00
selectcc-to-shiftand.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
selectopt.ll
[RISCV] Enable select optimization by default (#178394)
2026-02-10 16:19:01 +08:00
setcc-logic.ll
[RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW during selectSETCC. (#162614)
2025-10-14 08:45:00 +08:00
sext-zext-trunc.ll
[RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW during selectSETCC. (#162614)
2025-10-14 08:45:00 +08:00
sextw-removal-debug.mir
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
sextw-removal.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
shadowcallstack.ll
[RISCV] Loosen the requirement of shadow stack codegen to Zimop (#152251)
2025-09-09 12:18:06 +08:00
shift-amount-mod.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
shift-and.ll
…
shift-masked-shamt.ll
…
shifts.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
shl-cttz.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
shl-demanded.ll
…
shlimm-addimm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
short-forward-branch-load-imm.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
short-forward-branch-opt-load-atomic-acquire-seq_cst.ll
[RISCV] Add short forward branch support for lb, lbu, lh, lhu, lw, lwu and ld (#170829)
2025-12-17 08:57:20 +05:30
short-forward-branch-opt-load.ll
[RISCV] Add short forward branch support for lb, lbu, lh, lhu, lw, lwu and ld (#170829)
2025-12-17 08:57:20 +05:30
short-forward-branch-opt-min-max.ll
[RISCV] Rename SFB Base Feature (#169607)
2025-12-01 09:18:02 -08:00
short-forward-branch-opt-mul.ll
[RISCV] Rename SFB Base Feature (#169607)
2025-12-01 09:18:02 -08:00
short-forward-branch-opt-qcloads.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
short-forward-branch-opt.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
shrinkwrap-jump-table.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
shrinkwrap.ll
…
sifive7-enable-intervals.mir
[RISCV][NFC] Simplify the vector pipe names in SiFive7 sched model (#181268)
2026-02-13 00:13:53 +00:00
sifive-interrupt-attr-err.ll
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
sifive-interrupt-attr.ll
[RISCV] Fix Defs/Uses for SiFive CLIC Support (#137724)
2025-04-28 19:35:11 -07:00
signbit-test.ll
…
signed-truncation-check.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
simplify-condbr.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
sincos-expansion.ll
[RISCV][test] Add sincos-expansion.ll test case
2025-11-19 13:40:09 +00:00
sink-and-fold-crash.mir
…
sink-icmp.ll
…
spacemitx60-sched-copy.mir
[RISCV] Print MIR comments for AVL and VEC_RM operands (#179542)
2026-02-03 22:11:22 +00:00
spill-fill-fold.ll
…
spill-fpr-scalar.ll
…
spir-kernel-cc.ll
…
split-offsets.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
split-sp-adjust.ll
…
split-store.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
split-udiv-by-constant.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
split-urem-by-constant.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
sra-xor-sra.ll
[DAGCombiner] Add sra-xor-sra pattern fold (#166777)
2025-11-10 19:03:34 -08:00
srem-lkk.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
srem-seteq-illegal-types.ll
[RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB (#166757)
2025-11-13 18:11:53 +01:00
srem-vector-lkk.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
srem.ll
[DAG] Fold rem(rem(A, BCst), Op1Cst) -> rem(A, Op1Cst) (#159517)
2025-09-22 09:30:10 +00:00
srodata.ll
[RISCV] Set riscv-fpimm-cost threshold to 3 by default (#159352)
2025-09-24 10:50:01 +01:00
ssub_sat_plus.ll
[RISCV] Custom legalize i32 saddo/ssubo on RV64 to return a sign extended value for the data result. (#172112)
2025-12-14 22:33:01 -08:00
ssub_sat.ll
[RISCV] Custom legalize i32 saddo/ssubo on RV64 to return a sign extended value for the data result. (#172112)
2025-12-14 22:33:01 -08:00
stack-clash-prologue-nounwind.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-clash-prologue.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-folding.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
stack-guard-global.ll
…
stack-guard-tls.ll
…
stack-inst-compress.mir
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-offset.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
stack-probing-frame-setup.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
stack-protector-target.ll
RuntimeLibcalls: Add some tests for OpenBSD stack protectors (#147888)
2025-07-15 15:50:54 +09:00
stack-realignment-with-variable-sized-objects.ll
…
stack-realignment.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-slot-coloring.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
stack-slot-size.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
stack-store-check.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
subtarget-features-std-ext.ll
…
switch-width.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
tagged-globals.ll
…
tail-calls.ll
[RISCV] improve musttail support (#170547)
2026-02-11 17:27:51 +01:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
tls-models.ll
[llvm][RISCV] precommit test update via UTC (#179508)
2026-02-03 11:11:42 -08:00
tlsdesc-symbol.ll
…
trunc-free.ll
…
trunc-nsw-nuw.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
twoaddr-tied.mir
[TwoAddressInstruction] Iterate through tied regs when analyzing revcopy (#179940)
2026-02-16 11:54:26 +03:00
typepromotion-overflow.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
uadd_sat_plus.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
uadd_sat.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
ucmp.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
udiv-const-optimization.ll
[SelectionDAG] Optimize 32-bit udiv with 33-bit magic constants on 64-bit targets (#181288)
2026-03-06 15:18:34 -08:00
umulo-128-legalisation-lowering.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
unaligned-load-store.ll
[RISCV] Add a high half PACKW+PACK pattern for RV64. (#152760)
2025-08-11 07:37:55 -05:00
unfold-masked-merge-scalar-variablemask.ll
Reland "[SelectionDAG] Make (a & x) | (~a & y) -> (a & (x ^ y)) ^ y available for all targets" (#143651)
2025-06-11 15:56:37 +08:00
unroll-loop-cse.ll
…
urem-lkk.ll
[SelectionDAG] Optimize 32-bit udiv with 33-bit magic constants on 64-bit targets (#181288)
2026-03-06 15:18:34 -08:00
urem-seteq-illegal-types.ll
DAG: Use poison when widening build_vector (#167631)
2025-11-12 20:17:41 +00:00
urem-vector-lkk.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
urem.ll
[DAG] Fold rem(rem(A, BCst), Op1Cst) -> rem(A, Op1Cst) (#159517)
2025-09-22 09:30:10 +00:00
usub_sat_plus.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
usub_sat.ll
[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) (#170076)
2025-12-18 14:31:53 +00:00
vararg-ilp32e.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
vararg.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
varargs-with-fp-and-second-adj.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
vector-abi.ll
…
vector-tuple-zeroinitializer.ll
…
verify-instr.mir
…
vlenb.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
vmadd-reassociate.ll
[RISCV] Incorporate scalar addends to extend vector multiply accumulate chains (#168660)
2025-11-21 09:49:15 -08:00
vscale-demanded-bits.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
wide-mem.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
wide-scalar-shift-legalization.ll
[DAG] visitFREEZE - limit freezing of multiple operands (#149797)
2025-07-22 15:40:55 +01:00
xaluo.ll
[RISCV] Remove redundant czero in multi-word comparisons (#180485)
2026-02-09 21:48:14 -08:00
xandesbfhcvt.ll
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
xandesperf-redundant-copy-elim.ll
[RISCV] Add support for XAndesPerf branch on immediate in RISCVRedundantCopyElimination (#174706)
2026-01-08 08:38:34 +08:00
xcvalu.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
xcvbi.ll
[PHIElimination] Revert #131837 #146320 #146337 (#146850)
2025-07-03 07:48:08 -04:00
xcvbitmanip.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
xcvelw.ll
[RISCV] Intrinsic Support for XCVelw (#129168)
2025-11-29 19:07:19 +11:00
xcvmac.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
xcvmem-heuristic.ll
…
xcvmem.ll
[RISCV] Replace undef with poison, NFC (#157396)
2025-09-09 15:16:16 +08:00
xmips-cbop.ll
[RISCV] Handled the uimm9 offset while FrameIndex folding. (#149303)
2025-07-30 17:43:10 +02:00
xmips-exectl.ll
RISC-V: builtins support for MIPS RV64 P8700 execution control .
2025-09-19 15:10:28 +05:30
xqccmp_mvas_mvsa.mir
[RISCV] Mark Xqccmp as not experimental (#175066)
2026-01-10 07:50:29 -08:00
xqccmp-additional-stack.ll
[RISCV] Mark Xqccmp as not experimental (#175066)
2026-01-10 07:50:29 -08:00
xqccmp-callee-saved-gprs.ll
[RISCV] Mark Xqccmp as not experimental (#175066)
2026-01-10 07:50:29 -08:00
xqccmp-cm-popretz.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
xqccmp-cm-push-pop.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
xqccmp-push-pop-popret.ll
[RISCV] Mark Xqccmp as not experimental (#175066)
2026-01-10 07:50:29 -08:00
xqccmp-with-float.ll
[RISCV] Mark Xqccmp as not experimental (#175066)
2026-01-10 07:50:29 -08:00
xqcia.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
xqciac.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
xqcibi-redundant-copy-elim.ll
[RISCV] Simplify testcases in xqcibi-redundant-copy-elim.ll. NFC. (#174695)
2026-01-08 08:38:17 +08:00
xqcibi.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
xqcibm-cto-clo-brev.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
xqcibm-extract.ll
[RISCV] Add regalloc hints for QC_EXTU (#173953)
2025-12-30 11:27:52 +05:30
xqcibm-insbi.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
xqcibm-insert.ll
[RISCV] Run combineOrToBitfieldInsert after DAG legalize (#177830)
2026-01-26 15:43:00 +05:30
xqcibm-regalloc-hints.ll
[RISCV] Add regalloc hints for BSETI/BEXTI (#173964)
2025-12-30 17:49:18 +05:30
xqcicli.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
xqcicm.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
xqcics.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
xqcilia.ll
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
2025-12-24 07:10:47 +05:30
xqcilo.ll
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
xqcilsm-lwmi-swmi-multiple.mir
[RISCV] Generate Xqcilsm multi-word load/store instructions for three or more words (#174789)
2026-01-08 12:53:33 +05:30
xqcilsm-lwmi-swmi.mir
[RISCV] Improve load/store pairing for Xqcilsm instructions in RISCVLoadStoreOptimizer (#174612)
2026-01-07 07:01:58 +05:30
xqcilsm-memset.ll
[RISCV] Generate Xqcilsm multi-word load/store instructions for three or more words (#174789)
2026-01-08 12:53:33 +05:30
xqcisls-merge-base-offset-shladd.ll
[RISCV] Fold shladd into Xqcisls scaled load/store in RISCVMergeBaseOffset (#182221)
2026-02-21 15:36:36 +05:30
xqcisls.ll
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
xray-attribute-instrumentation.ll
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xtheadfmemidx.ll
[RISCV] Improves to xtheadmemidx.ll and xtheadfmemidx.ll. NFC
2025-07-22 12:46:03 -07:00
xtheadmac.ll
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xtheadmemidx.ll
[RISCV] Add profitability checks to SelectAddrRegRegScale. (#150135)
2025-07-22 21:10:52 -07:00
xtheadmempair.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
zalasr-offset-folding.ll
[RISCV]Remove experimental from Zalasr (#177120)
2026-01-22 17:30:38 +08:00
zbb-cmp-combine.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
zbb-logic-neg-imm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
zcb-regalloc-hints.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
zcmp-additional-stack.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
zcmp-cm-popretz.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
zcmp-cm-push-pop.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
zcmp-prolog-epilog-crash.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
zcmp-with-float.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
zdinx-asm-constraint.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
zdinx-boundary-check.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
zdinx-large-spill.mir
[RISCV] Tweak zdinx-large-spill.mir so it tests what it was intended to. NFC
2025-05-14 12:35:49 -07:00
zdinx-memoperand.ll
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
zdinx-spill.ll
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
zext-with-load-is-free.ll
[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)
2025-09-09 09:25:36 -07:00
zfh-half-intrinsics-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
zfh-half-intrinsics.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
zfhmin-half-intrinsics-strict.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
zfhmin-half-intrinsics.ll
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
zfhmin-imm.ll
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zibi.ll
[RISCV] Add support for Zibi experimental extension in RISCVRedundantCopyElimination (#174920)
2026-01-09 14:00:53 +08:00
zicfilp-indirect-branch.ll
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zicond-fp-select-zfinx.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
zicond-opts.ll
[RISCV] Optimize (and (icmp x, 0, neq), (icmp y, 0, neq)) utilizing zicond extension
2025-11-06 22:48:33 -08:00
zilsd-ldst-opt-postra.mir
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
zilsd-ldst-opt-prera.mir
[llvm][RISCV] Make X0 register pair legal in pre-ra pass (#169164)
2026-01-21 14:13:44 +08:00
zilsd-regalloc-hints.mir
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
zilsd-spill.ll
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
zilsd.ll
[llvm][RISCV] Make X0 register pair legal in pre-ra pass (#169164)
2026-01-21 14:13:44 +08:00
zmmul.ll
…