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llvm-project/llvm/lib/Target/RISCV
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Philip Reames db746c65b1
[RISCV] Allow constants in tryFoldSelectIntoOp (#157376) 
For simm12 constants this allows the use of e.g. addi/xori, and for
non-simm12 constants seems to still produce better code than the default
lowering.
2025-09-08 13:11:34 -07:00
..
AsmParser
[RISCV] Implement MC support for Zvfbfa extension (#151106)
2025-08-28 01:36:10 +00:00
Disassembler
[RISCV] Remove post-decoding instruction adjustments (#156360)
2025-09-04 16:02:34 +00:00
GISel
[RISCV][GISel] Lower G_ABDS and G_ABDU (#155888)
2025-09-05 21:16:35 +08:00
MCA
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
MCTargetDesc
[llvm] Support building with c++23 (#154372)
2025-08-29 12:52:07 +00:00
TargetInfo
[RISCV] Add initial assembler/MC layer support for big-endian (#146534)
2025-08-22 09:21:10 +02:00
CMakeLists.txt
Recommit "[RISCV] Don't run loop-idiom-vectorize pass in the O0 pipeline. (#156798)"
2025-09-04 09:50:12 -07:00
RISCV.h
…
RISCV.td
[RISCV] Implement base scheduling model for andes 45 series processor. (#141008)
2025-06-04 16:11:43 +08:00
RISCVAsmPrinter.cpp
[RISCV] Simplify interface of RISCVAsmPrinter::lowerToMCInst [nfc] (#156482)
2025-09-02 14:56:26 -07:00
RISCVCallingConv.cpp
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.h
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.td
[RISCV] Support PreserveMost calling convention (#148214)
2025-07-30 16:30:48 +08:00
RISCVCodeGenPrepare.cpp
…
RISCVCombine.td
…
RISCVConstantPoolValue.cpp
…
RISCVConstantPoolValue.h
…
RISCVDeadRegisterDefinitions.cpp
[RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0,x0 vsetvli. NFC (#141875)
2025-05-29 10:21:38 -07:00
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Add nds.bfos and nds.bfoz for the short forward branch optimization. (#145836)
2025-06-27 10:54:41 +08:00
RISCVFeatures.td
[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (#155747)
2025-09-01 10:40:28 +02:00
RISCVFoldMemOffset.cpp
…
RISCVFrameLowering.cpp
[llvm] Use a range-based for loop instead of {std,llvm}::for_each (NFC) (#150841)
2025-07-27 10:43:52 -07:00
RISCVFrameLowering.h
[RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531)
2025-07-15 08:09:18 -07:00
RISCVGatherScatterLowering.cpp
[RISCV] Use non-vp select in RISCVGatherScatterLowering. NFCish (#157071)
2025-09-06 11:46:02 +08:00
RISCVGISel.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVIndirectBranchTracking.cpp
[RISCV][NFC] Fix typo in RISCVIndirectBranchTracking.cpp (#157221)
2025-09-08 15:02:48 +08:00
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Don't increase vslide or splat vl if +vl-dependent-latency is present (#147089)
2025-07-09 16:25:22 +08:00
RISCVInsertWriteVXRM.cpp
…
RISCVInstrFormats.td
[Target] Remove SoftFail field on targets that don't use it (NFC) (#154659)
2025-08-21 05:21:42 +03:00
RISCVInstrFormatsC.td
[RISCV] Remove post-decoding instruction adjustments (#156360)
2025-09-04 16:02:34 +00:00
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
…
RISCVInstrInfo.cpp
CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (#157337)
2025-09-08 12:12:19 +09:00
RISCVInstrInfo.h
CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (#157337)
2025-09-08 12:12:19 +09:00
RISCVInstrInfo.td
[RISCV] Fold (X & (7 << 29)) == 0 -> (srliw X, 29) == 0 for RV64. (#156769)
2025-09-03 22:16:05 -07:00
RISCVInstrInfoA.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoC.td
[RISCV] Remove post-decoding instruction adjustments (#156360)
2025-09-04 16:02:34 +00:00
RISCVInstrInfoD.td
…
RISCVInstrInfoF.td
…
RISCVInstrInfoM.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoP.td
[RISCV] Correct the OperandType for simm8_unsigned and simm10_unsigned. (#154667)
2025-08-21 12:01:07 -07:00
RISCVInstrInfoQ.td
…
RISCVInstrInfoSFB.td
[RISCV] Reduce duplication in RISCVInstrInfoSFB.td by using classes. NFC (#157185)
2025-09-05 21:59:49 -07:00
RISCVInstrInfoV.td
[RISCV] Rename VALUrVV/VALUrVX/VALUrVF tablegen clases. NFC (#154989)
2025-08-22 16:36:11 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove unused vector pseudo class. NFC (#151327)
2025-07-31 10:14:36 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Use (i64 GPR:$rs1) instead of i64:$rs1 in isel patterns.
2025-08-01 09:44:09 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Remove remaining vmerge_vl mask patterns. NFC (#156566)
2025-09-03 15:05:53 +08:00
RISCVInstrInfoXAndes.td
[RISCV] Remove non-existent operand of nds.vfwcvt/nds.vfncvt instructions (#153865)
2025-08-16 00:46:19 +03:00
RISCVInstrInfoXCV.td
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVInstrInfoXMips.td
[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (#155747)
2025-09-01 10:40:28 +02:00
RISCVInstrInfoXqccmp.td
…
RISCVInstrInfoXqci.td
[RISCV] Use QC_E_LI to materialise addresses (#155819)
2025-09-05 12:58:28 +05:30
RISCVInstrInfoXRivos.td
[RISCV] Add TSFlag for reading past VL behaviour. NFCI (#149704)
2025-08-15 01:19:03 +00:00
RISCVInstrInfoXSf.td
[RISCV] Add TSFlag for reading past VL behaviour. NFCI (#149704)
2025-08-15 01:19:03 +00:00
RISCVInstrInfoXSfmm.td
[RISCV] Add TSFlag for reading past VL behaviour. NFCI (#149704)
2025-08-15 01:19:03 +00:00
RISCVInstrInfoXSpacemiT.td
[RISCV] Fold argstr into class for XSMTVDot instructions. NFC.
2025-08-21 13:12:46 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Use (i64 GPR:$rs1) instead of i64:$rs1 in isel patterns.
2025-08-01 09:44:09 -07:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
[RISCV] Remove post-decoding instruction adjustments (#156360)
2025-09-04 16:02:34 +00:00
RISCVInstrInfoZa.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoZalasr.td
…
RISCVInstrInfoZb.td
[RISCV] Add missing 'OrP' to comment in RISCVInstrInfoZb.td. NFC
2025-08-20 15:27:03 -07:00
RISCVInstrInfoZc.td
[RISCV] Remove extra operands from Zcb compression patterns. NFC (#150541)
2025-07-24 18:03:30 -07:00
RISCVInstrInfoZclsd.td
…
RISCVInstrInfoZcmop.td
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVInstrInfoZfa.td
…
RISCVInstrInfoZfbfmin.td
…
RISCVInstrInfoZfh.td
…
RISCVInstrInfoZicbo.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZilsd.td
…
RISCVInstrInfoZimop.td
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVInstrInfoZk.td
…
RISCVInstrInfoZvfbf.td
…
RISCVInstrInfoZvk.td
[RISCV] Remove duplicate vsha2ch/vsha2cl/vsha2ms i32 patterns. NFC (#151835)
2025-08-02 21:53:58 -07:00
RISCVInstrInfoZvqdotq.td
[RISCV] Support ZVqdot Codegen and C intrinsics (#154915)
2025-09-05 11:38:58 +08:00
RISCVInstrPredicates.td
[RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions (#145147)
2025-07-03 12:47:53 +08:00
RISCVInterleavedAccess.cpp
[IA][RISCV] Recognize interleaving stores that could lower to strided segmented stores (#154647)
2025-08-26 13:22:42 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Add th.ext(u) to RISCVDAGToDAGISel::hasAllNBitUsers. (#157133)
2025-09-05 11:57:26 -07:00
RISCVISelDAGToDAG.h
[RISCV] Add changes to have better coverage for qc.insb and qc.insbi (#154135)
2025-09-03 12:35:38 +05:30
RISCVISelLowering.cpp
[RISCV] Allow constants in tryFoldSelectIntoOp (#157376)
2025-09-08 13:11:34 -07:00
RISCVISelLowering.h
[IA][RISCV] Recognize interleaving stores that could lower to strided segmented stores (#154647)
2025-08-26 13:22:42 -07:00
RISCVLandingPadSetup.cpp
…
RISCVLateBranchOpt.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVLoadStoreOptimizer.cpp
…
RISCVMachineFunctionInfo.cpp
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RISCVMachineFunctionInfo.h
…
RISCVMacroFusion.td
[RISCV] add more generic macrofusions (#151140)
2025-08-06 14:46:34 -04:00
RISCVMakeCompressible.cpp
[RISCV][NFC] Remove hasStdExtCOrZca (#145139)
2025-06-23 10:49:47 -07:00
RISCVMergeBaseOffset.cpp
…
RISCVMoveMerger.cpp
[RISCV] Minor refactor of RISCVMoveMerge::mergePairedInsns. (#154467)
2025-08-20 09:07:58 -07:00
RISCVOptWInstrs.cpp
[RISCV] Add PseudoCCANDN/ORN/XNOR to isSignExtendedW.
2025-09-05 13:06:35 -07:00
RISCVPfmCounters.td
…
RISCVPostRAExpandPseudoInsts.cpp
…
RISCVProcessors.td
[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (#155747)
2025-09-01 10:40:28 +02:00
RISCVProfiles.td
…
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVRegisterInfo.cpp
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
RISCVRegisterInfo.h
[RISCV] Optimize the spill/reload of segment registers (#153184)
2025-08-21 16:38:53 +08:00
RISCVRegisterInfo.td
[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructions. (#150710)
2025-07-25 20:55:15 -07:00
RISCVSchedAndes45.td
[RISCV] Fix typo in comment Interger->Integer. NFC
2025-08-13 11:19:49 -07:00
RISCVSchedGenericOOO.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedMIPSP8700.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedRocket.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFive7.td
[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)
2025-07-09 09:38:44 -07:00
RISCVSchedSiFiveP400.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP500.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP600.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP800.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSpacemitX60.td
[RISCV] Update SpacemiT-X60 vector fixed-point arithmetic latencies (#150517)
2025-08-08 11:57:35 -03:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedTTAscalonD8.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedule.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVScheduleV.td
…
RISCVScheduleXSf.td
[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)
2025-07-09 09:38:44 -07:00
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
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RISCVSchedXiangShanNanHu.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSelectionDAGInfo.cpp
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555)
2025-08-04 12:51:14 +05:30
RISCVSelectionDAGInfo.h
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555)
2025-08-04 12:51:14 +05:30
RISCVSubtarget.cpp
[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy (#149297)
2025-07-22 15:55:12 +08:00
RISCVSubtarget.h
[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy (#149297)
2025-07-22 15:55:12 +08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
Recommit "[RISCV] Don't run loop-idiom-vectorize pass in the O0 pipeline. (#156798)"
2025-09-04 09:50:12 -07:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetObjectFile.h
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetTransformInfo.cpp
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
2025-09-02 11:43:27 +08:00
RISCVTargetTransformInfo.h
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
2025-09-02 11:43:27 +08:00
RISCVVectorMaskDAGMutation.cpp
Reland "[RISCV] AddEdge between mask producer and user of V0 (#146855)" (#148566)
2025-07-18 10:56:07 +08:00
RISCVVectorPeephole.cpp
[RISCV] Use MRI from MachineFunction in isVLKnownLE. NFC
2025-09-05 14:44:56 +08:00
RISCVVLOptimizer.cpp
[RISCV] Remove unneeded plumbing of MRI in VLOptimizer. NFC
2025-09-05 14:49:32 +08:00
RISCVVMV0Elimination.cpp
…
RISCVZacasABIFix.cpp
…