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llvm-project/llvm/test/CodeGen/RISCV
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Luke Lau c87eb63abf [RISCV] Move test to RVV directory. NFC 
Just a nit, moving the test so that it gets picked up by
check-codegen-riscv-rvv since it contains vector code
2023-12-12 17:31:59 +09:00
..
GlobalISel
[RISCV][GISel] Re-generate legalize-vastart-rv32.mir and legalize-vastart-rv64.mir to fix buildbot failure. NFC
2023-12-08 13:08:46 -08:00
intrinsics
…
rv64-legal-i32
[RISCV] Add more Zbs patterns for -riscv-experimental-rv64-legal-i32.
2023-11-21 23:24:00 -08:00
rvv
[RISCV] Move test to RVV directory. NFC
2023-12-12 17:31:59 +09:00
add-before-shl.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
add-imm.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
addrspacecast.ll
…
aext-to-sext.ll
[DAGCombiner][RISCV] Prefer to sext i32 non-negative values (#65984)
2023-09-12 19:02:35 +08:00
aext.ll
Add RV64 constraint to SRLIW (#69416)
2023-10-18 15:01:17 +08:00
align-loops.ll
[RISCV] Add searchable table for tune information (#66193)
2023-09-26 12:26:35 +08:00
align.ll
[RISCV] Add searchable table for tune information (#66193)
2023-09-26 12:26:35 +08:00
alloca.ll
…
alu8.ll
…
alu16.ll
…
alu32.ll
…
alu64.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
analyze-branch.ll
…
and-add-lsr.ll
[DAGCombine] Canonicalize operands for visitANDLike
2023-07-24 16:52:04 +08:00
and.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
arith-with-overflow.ll
…
atomic-cmpxchg-branch-on-result.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-cmpxchg-flag.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-cmpxchg.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
atomic-fence.ll
[RISCV] Implement a proposed mapping for Ztso
2023-02-09 12:00:05 -08:00
atomic-load-store.ll
[RISC-V] Add proposed mapping for Ztso
2023-08-10 15:59:06 +01:00
atomic-rmw-discard.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
atomic-rmw-sub.ll
[SDAG][RISCV] Avoid neg instructions when lowering atomic_load_sub with a constant rhs
2023-09-16 17:09:41 +08:00
atomic-rmw.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
atomic-signext.ll
[RISCV] Add IsSignExtendingOpW to AMO*_W instructions. (#72349)
2023-11-15 09:39:31 -08:00
atomicrmw-uinc-udec-wrap.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
attributes.ll
[RISCV][MC] MC layer support for xcvmem and xcvelw extensions
2023-11-16 09:46:11 +08:00
bf16-promote.ll
[RISCV] Expand load extension / truncate store for bf16
2023-08-01 11:10:41 +08:00
bfloat-arith.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-br-fcmp.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-convert.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
bfloat-fcmp.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-frem.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-imm.ll
[RISCV] Add bf16 to isFPImmLegal.
2023-08-03 08:27:38 -07:00
bfloat-isnan.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-mem.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-select-fcmp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
bfloat-select-icmp.ll
[RISCV] Add bf16 to isFPImmLegal.
2023-08-03 08:27:38 -07:00
bfloat.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
bitextract-mac.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
bitreverse-shift.ll
…
bittest.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
blockaddress.ll
…
branch_zero.ll
…
branch-on-zero.ll
[LSR][TTI][RISCV] Enable terminator folding for RISC-V
2023-11-29 12:04:06 -08:00
branch-opt.ll
[RISCV] CSE by swapping conditional branches (#71111)
2023-11-03 09:03:52 -07:00
branch-relaxation.ll
BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads
2023-10-24 20:27:39 -07:00
branch.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
bswap-bitreverse.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
bswap-shift.ll
…
byval.ll
…
callee-saved-fpr32s.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
callee-saved-fpr64s.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
callee-saved-gprs.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
calling-conv-half.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
calling-conv-ilp32-ilp32f-common.ll
…
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV] Support FrameIndex operands in getMemOperandsWithOffsetWidth / getMemOperandWithOffsetWidth (#73802)
2023-12-05 21:26:56 +00:00
calling-conv-ilp32.ll
…
calling-conv-ilp32d.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-lp64-lp64f-common.ll
…
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Support FrameIndex operands in getMemOperandsWithOffsetWidth / getMemOperandWithOffsetWidth (#73802)
2023-12-05 21:26:56 +00:00
calling-conv-lp64.ll
…
calling-conv-rv32f-ilp32.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-vector-on-stack.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
calls.ll
…
cm_mvas_mvsa.ll
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
cmp-bool.ll
…
codemodel-lowering.ll
[RISCV] Fix the float value to test constantpool lowering under differe… (#67297)
2023-09-26 09:06:49 +08:00
compress-double.ll
[RISCV] Split double out of compress-float.ll. Add Zcf and Zcd RUN lines.
2023-06-27 09:44:51 -07:00
compress-float.ll
[RISCV] Add Zce extension.
2023-07-13 12:22:06 -07:00
compress-inline-asm.ll
…
compress-opt-branch.ll
…
compress-opt-select.ll
…
compress.ll
…
condbinops.ll
[RISCV] Generalize 'tryFoldSelectIntOp` to other operations.
2023-08-01 11:27:10 -04:00
condops.ll
[RISCV] Refine pattern (select_cc seteq (and x, C), 0, 0, A) with Zbs. (#73746)
2023-11-29 13:09:47 +08:00
copy-frameindex.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
copyprop.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
copysign-casts.ll
[RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X))
2023-07-05 19:35:13 -07:00
ctlz-cttz-ctpop.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
ctz_zero_return_test.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
disable-tail-calls.ll
…
disjoint.ll
…
div_minsize.ll
…
div-by-constant.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
div-pow2.ll
…
div.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
double_reduct.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
double-arith-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-arith.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-br-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-calling-conv.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
double-convert.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
double-fcmp-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-frem.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-imm.ll
[RISCV] Fix lowering of negative zero with Zdinx 32-bit (#71869)
2023-11-13 07:38:14 +01:00
double-intrinsics-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-intrinsics.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-isnan.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-maximum-minimum.ll
[RISCV] Correct copyPhysReg for GPRPF64. (#70419)
2023-10-26 23:54:46 -07:00
double-mem.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
double-previous-failure.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-round-conv-sat.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
double-round-conv.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-select-fcmp.ll
[RISCV] Correct copyPhysReg for GPRPF64. (#70419)
2023-10-26 23:54:46 -07:00
double-select-icmp.ll
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
2023-06-17 10:10:20 +08:00
double-stack-spill-restore.ll
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
double-zfa.ll
[RISCV] Use FLI + FNEG to materialize some negative FP constants (#70825)
2023-10-31 17:52:50 -07:00
dso_local_equivalent.ll
[MC][CodeGen] Define R_RISCV_PLT32 and lower dso_local_equivalent to it
2023-02-23 01:26:27 +00:00
dwarf-eh.ll
[test] Change llc -march= to -mtriple= & llvm-mc -arch= to -triple=
2023-09-11 15:11:01 -07:00
early-clobber-tied-def-subreg-liveness.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
eh-dwarf-cfa.ll
…
elf-preemption.ll
…
emutls.ll
[RISCV] Support emulated TLS
2023-03-29 20:55:51 +01:00
exception-pointer-register.ll
…
fastcc-float.ll
…
fastcc-int.ll
…
fastcc-without-f-reg.ll
[RISCV] Correct Zhinx load/store patterns to use AddrRegImm.
2023-09-26 11:54:59 -07:00
fixups-diff.ll
[RISCV] Allow delayed decision for ADD/SUB relocations
2023-07-21 08:37:58 -07:00
fli-licm.ll
[RISCV] Mark the Zfa extension as non-experimental (#68113)
2023-10-03 18:16:13 +01:00
float-arith-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-arith.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-bit-preserving-dagcombines.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-br-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
float-convert.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
float-fcmp-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-frem.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-imm.ll
[RISCV] Merge fp-imm.ll and zfh-imm.ll into float/double/half-imm.ll. NFC
2023-08-02 20:16:50 -07:00
float-intrinsics-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-intrinsics.ll
[RISCV] Update computeKnownBitsForTargetNode for FPCLASS.
2023-06-29 14:13:01 +08:00
float-isnan.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-maximum-minimum.ll
[RISCV] Add no NaN support to lowerFMAXIMUM_FMINIMUM.
2023-08-01 09:51:24 -07:00
float-mem.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
float-round-conv-sat.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
float-round-conv.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-select-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-select-icmp.ll
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
2023-06-17 10:10:20 +08:00
float-select-verify.ll
[RISCV] Don't use constantpool for floating-point value if the value can be easily constructed by integer sequence and a floating-point move.
2023-02-03 22:42:08 -08:00
float-zfa.ll
[RISCV] Use FLI + FNEG to materialize some negative FP constants (#70825)
2023-10-31 17:52:50 -07:00
flt-rounds.ll
…
fmax-fmin.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fold-addi-loadstore.ll
[RISCV] Add sink-and-fold support for RISC-V. (#67602)
2023-10-07 10:38:35 -07:00
fold-binop-into-select.ll
Reapply [RISCV] Fold binary op into select if profitable.
2023-07-14 15:30:54 -04:00
forced-atomics.ll
[RISCV] Strengthen atomic ordering for sequentially consistent stores
2023-06-22 15:42:17 +00:00
fp16-promote.ll
[RISCV] Custom lower FP_TO_FP16 and FP16_TO_FP to correct ABI of of libcall
2023-06-30 16:41:49 +01:00
fp128.ll
…
fpclamptosat.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fpenv.ll
…
frame-info.ll
…
frame.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
frameaddr-returnaddr.ll
…
frm-dependency.ll
…
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
…
ghccc-nest.ll
…
ghccc-rv32.ll
…
ghccc-rv64.ll
…
ghccc-without-f-reg.ll
[RISCV] Support register allocation for GHC when f/d is not specified in the architecture
2023-07-23 22:40:10 -07:00
global-merge-offset.ll
…
global-merge.ll
…
graalcc.ll
[IR] Add GraalVM calling conventions
2023-11-17 16:30:09 +00:00
half-arith-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-arith.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-bitmanip-dagcombines.ll
[RISCV] Correct Zhinx load/store patterns to use AddrRegImm.
2023-09-26 11:54:59 -07:00
half-br-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-convert-strict.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
half-convert.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
half-fcmp-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-frem.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-imm.ll
[RISCV] Merge fp-imm.ll and zfh-imm.ll into float/double/half-imm.ll. NFC
2023-08-02 20:16:50 -07:00
half-intrinsics.ll
[RISCV] Correct Zhinx load/store patterns to use AddrRegImm.
2023-09-26 11:54:59 -07:00
half-isnan.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-maximum-minimum.ll
[RISCV] Add no NaN support to lowerFMAXIMUM_FMINIMUM.
2023-08-01 09:51:24 -07:00
half-mem.ll
[RISCV] Correct Zhinx load/store patterns to use AddrRegImm.
2023-09-26 11:54:59 -07:00
half-round-conv-sat.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
half-round-conv.ll
Ignore load/store until stack address computation
2023-06-26 13:50:36 -07:00
half-select-fcmp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
half-select-icmp.ll
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
2023-06-17 10:10:20 +08:00
half-zfa-fli.ll
[RISCV] Use FLI + FNEG to materialize some negative FP constants (#70825)
2023-10-31 17:52:50 -07:00
half-zfa.ll
[RISCV] Mark the Zfa extension as non-experimental (#68113)
2023-10-03 18:16:13 +01:00
hoist-global-addr-base.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
hwasan-check-memaccess.ll
…
i32-icmp.ll
…
i64-icmp.ll
…
iabs.ll
[RISCV][CodeGenPrepare] Remove duplicated transform for zext. NFC. (#72053)
2023-11-13 22:45:33 +08:00
idiv_large.ll
[CodeGen] Always expand division larger than i128
2023-03-01 15:33:45 +01:00
imm-cse.ll
…
imm.ll
[RISCV] Remove old FIXMEs from test. NFC
2023-11-29 21:53:32 -08:00
indirectbr.ll
…
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
…
inline-asm-mem-constraint.ll
[RISCV] Add tests for memory constraint A
2023-09-19 19:51:04 +08:00
inline-asm-S-constraint.ll
…
inline-asm-zfh-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm.ll
[RISCV][NFC] Move tests of inline asm memory constraints to separate file
2023-08-21 18:59:52 +08:00
inline-option-directive.ll
[RISCV] Support '.option arch' directive
2023-05-26 18:39:41 +08:00
interrupt-attr-args-error.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
interrupt-attr-ret-error.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
interrupt-attr.ll
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
intrinsic-cttz-elts-vscale.ll
[RISCV] Use Align(8) for the stack temporary created for SPLAT_VECTOR_SPLIT_I64_VL.
2023-11-09 20:43:22 -08:00
intrinsic-cttz-elts.ll
[AArch64] Add intrinsic to count trailing zero elements
2023-10-31 10:48:08 +00:00
isel-optnone.ll
…
jumptable.ll
[RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
2023-11-23 14:05:23 +08:00
kcfi-isel-mir.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
kcfi-mir.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
kcfi-patchable-function-prefix.ll
MachineFunction: -fsanitize={function,kcfi}: ensure 4-byte alignment
2023-06-30 09:13:19 -07:00
kcfi.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
lack-of-signed-truncation-check.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
large-stack.ll
…
legalize-fneg.ll
…
libcall-tail-calls.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
lit.local.cfg
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
live-sp.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
llvm.exp10.ll
IR: Add llvm.exp10 intrinsic
2023-09-01 19:45:03 -04:00
llvm.frexp.ll
Implement SoftPromoteHalf for FFREXP. (#74076)
2023-12-07 11:10:17 +00:00
local-stack-slot-allocation.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
loop-strength-reduce-add-cheaper-than-mul.ll
…
loop-strength-reduce-loop-invar.ll
…
lsr-legaladdimm.ll
…
machine-combiner-mir.ll
…
machine-combiner-strategies.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
machine-combiner.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
machine-combiner.mir
[RISCV] Clear kill flags when forming FMA instructions in MachineCombiner.
2023-07-12 08:03:45 -07:00
machine-cp.mir
Revert "[MCP] Enhance MCP copy Instruction removal for special case (#70778)"
2023-11-27 19:39:40 +01:00
machine-cse.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
machine-outliner-and-machine-copy-propagation.ll
[RISCV] Fix regression due to interaction of MachineOutliner and MachineCopyPropagation
2023-03-14 17:55:11 +00:00
machine-outliner-cfi.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
machine-outliner-patchable.ll
…
machine-outliner-position.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
machine-outliner-throw.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
machinelicm-address-pseudos.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
machineoutliner-jumptable.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
machineoutliner-pcrel-lo.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
machineoutliner.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
MachineSink-implicit-x0.mir
…
macro-fusion-lui-addi.ll
[RISCV] Replace PostRAScheduler with PostMachineScheduler (#68696)
2023-10-19 13:30:41 +08:00
macro-fusions-veyron-v1.mir
[RISCV] Macro-fusion support for veyron-v1 CPU. (#70012)
2023-12-11 16:34:13 -05:00
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
…
make-compressible.mir
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
mem64.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
mem.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
memcpy-inline.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
memcpy.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
memset-inline.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
min-max.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
mir-target-flags.ll
…
misched-load-clustering.ll
[RISCV] Support load clustering in the MachineScheduler (off by default) (#73754)
2023-11-29 10:01:55 +00:00
miss-sp-restore-eh.ll
…
module-target-abi2.ll
…
module-target-abi3.ll
…
module-target-abi.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
mul.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
musttail-call.ll
…
narrow-shl-cst.ll
…
neg-abs.ll
…
nest-register.ll
…
nomerge.ll
[CodeGen] Fix nomerge attribute not working in tail calls.
2023-05-10 14:25:11 -04:00
nontemporal-scalable.ll
[RISCV] Remove experimental for zihintntl
2023-08-10 17:04:49 +08:00
nontemporal.ll
[RISCV] Remove experimental for zihintntl
2023-08-10 17:04:49 +08:00
O0-pipeline.ll
[RISCV] default enable splitting regalloc between RVV and other (#72950)
2023-11-30 21:12:46 -06:00
O3-pipeline.ll
[RISCV] default enable splitting regalloc between RVV and other (#72950)
2023-11-30 21:12:46 -06:00
opt-w-instrs.mir
[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633)
2023-10-19 14:55:33 -07:00
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
or-is-add.ll
…
out-of-reach-emergency-slot.mir
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
overflow-intrinsic-optimizations.ll
…
overflow-intrinsics.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
patchable-function-entry.ll
[AsmPrinter] Fix placement of function entry comments
2023-04-18 15:01:36 -07:00
pei-crash.ll
[RISCV] Fix crash in PEI with empty entry block with Zcmp (#72117)
2023-11-17 16:18:44 +01:00
pic-models.ll
…
pr40333.ll
…
pr51206.ll
[ShrinkWrap] Use underlying object to rule out stack access.
2023-05-03 09:28:07 +01:00
pr53662.mir
…
pr55201.ll
…
pr56110.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
pr56457.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
pr58025.ll
…
pr58286.ll
…
pr58511.ll
[DAGCombine] Make sure combined nodes are added back to the worklist in topological order.
2023-06-13 09:14:37 +00:00
pr63365.ll
[CodeGenPrepare][RISCV] Remove asserting VH references before erasing the dead GEP
2023-06-18 23:40:47 +08:00
pr63816.ll
[LegalizeDAG] Prevent LegalizeLoadOps from creating extloads that mix int and fp types.
2023-07-12 08:03:35 -07:00
pr64503.ll
[DAG] FoldSetCC - add missing icmp(X,undef) -> isTrueWhenEqual case (REAPPLIED)
2023-09-13 12:33:39 +01:00
pr64645.ll
[RISCV] Fix assertion when passing f64 vectors via integer registers
2023-08-15 12:11:08 +08:00
pr64772.ll
[DAGCombiner][RISCV] Return SDValue(N, 0) instead of SDValue() after 2 calls to CombineTo in visitSTORE.
2023-08-17 15:13:36 -07:00
pr64935.ll
[SDAG][RISCV] Avoid folding setcc (xor C1, -1), C2, cond into setcc (xor C2, -1), C1, cond
2023-08-24 04:18:17 +08:00
pr65025.ll
[RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.
2023-08-28 10:11:12 -07:00
pr66603.ll
[DAG] canCreateUndefOrPoison - remove AssertSext/AssertZext assumption that they never create undef/poison
2023-10-19 13:28:53 +01:00
pr68855.ll
[RISCV][SDAG] Fix constant narrowing when narrowing loads (#69015)
2023-10-14 06:38:17 +08:00
pr69586.ll
[RISCV] Add an experimental pseudoinstruction to represent a rematerializable constant materialization sequence. (#69983)
2023-10-25 17:20:32 -07:00
prefetch.ll
[RISCV] Match prefetch address with offset (#66072)
2023-10-20 14:22:48 +08:00
push-pop-opt-crash.ll
[RISCV] Add bounds check before use on returned iterator.
2023-08-14 16:06:09 -07:00
push-pop-popret.ll
[RISCV] Support FrameIndex operands in getMemOperandsWithOffsetWidth / getMemOperandWithOffsetWidth (#73802)
2023-12-05 21:26:56 +00:00
readcyclecounter.ll
…
reduce-unnecessary-extension.ll
[SDAG] Count call argument attributes to reduce unnecessary extension (#73501)
2023-12-05 09:55:52 +01:00
reduction-formation.ll
[RISCV] Don't try to form VECREDUCE without vector instructions
2023-10-04 10:29:27 -07:00
regalloc-last-chance-recoloring-failure.ll
[RISCV] postpone removal in initundef pass (#71661)
2023-11-20 11:44:27 +08:00
relax-per-target-feature.ll
[RISCV][MC] Pass MCSubtargetInfo down to shouldForceRelocation and evaluateTargetFixup. (#73721)
2023-12-07 13:17:58 -08:00
rem.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
remat.ll
…
repeated-fp-divisors.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
reserved-reg-errors.ll
…
reserved-regs.ll
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
riscv-codegenprepare-asm.ll
[SCEVExpander] Attempt to reinfer flags dropped due to CSE (#72431)
2023-12-07 13:20:36 -08:00
riscv-codegenprepare.ll
[RISCV][CodeGenPrepare] Remove duplicated transform for zext. NFC. (#72053)
2023-11-13 22:45:33 +08:00
riscv-func-target-feature.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
riscv-shifted-extend.ll
[Test] Pre-submit tests for #68972 (#69040)
2023-10-14 12:18:43 +08:00
rotl-rotr.ll
[DAG] SimplifyDemandedBits - call ComputeKnownBits for constant non-uniform ISD::SRL shift amounts
2023-07-21 14:52:57 +01:00
rv32-fuchsia.ll
[llvm] Prevent building for riscv32-unknown-fuchsia
2023-03-01 19:42:56 +00:00
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
…
rv32xtheadba.ll
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
2023-02-08 07:54:52 +01:00
rv32xtheadbb.ll
[RISCV] Select signed and unsigned bitfield extracts for XTHeadBb
2023-02-17 21:46:26 +01:00
rv32xtheadbs.ll
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
2023-02-13 16:28:26 +01:00
rv32zba.ll
[RISCV] Optimize multiplication with immediates
2023-04-15 17:29:06 +08:00
rv32zbb-intrinsic.ll
…
rv32zbb-zbkb.ll
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
rv32zbb.ll
[SDAG] Simplify is-power-of-2 codegen (#72275)
2023-11-15 22:26:34 +09:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
[RISCV] Add more packh patterns.
2023-11-11 19:31:23 -08:00
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
[RISCV] Use bset+addi for (not (sll -1, X)).
2023-11-16 11:14:53 -08:00
rv32zknd-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zknd-intrinsic.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zkne-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zkne-intrinsic.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zknh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv32zksed-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zksed-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv32zksh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64-large-stack.ll
…
rv64-patchpoint.ll
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
rv64-stackmap-frame-setup.ll
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
rv64-stackmap-nops.ll
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
rv64-stackmap.ll
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
…
rv64f-float-convert-strict.ll
…
rv64f-float-convert.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
rv64i-shift-sext.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
rv64m-exhaustive-w-insts.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
rv64m-w-insts-legalization.ll
…
rv64xtheadba.ll
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
2023-02-08 07:54:52 +01:00
rv64xtheadbb.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
rv64xtheadbs.ll
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
2023-02-13 16:28:26 +01:00
rv64zba.ll
[RISCV] Use add.uw for (or (and X, 0xFFFFFFFF), Y) if Y has zeroes in the lower 32 bits. (#65402)
2023-09-05 21:05:53 -07:00
rv64zbb-intrinsic.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
rv64zbb-zbkb.ll
…
rv64zbb.ll
[SDAG] Simplify is-power-of-2 codegen (#72275)
2023-11-15 22:26:34 +09:00
rv64zbc-intrinsic.ll
[RISCV] Improve type promotion for i32 clmulr/clmulh on RV64.
2023-07-18 10:39:25 -07:00
rv64zbc-zbkc-intrinsic.ll
[RISCV] Improve type promotion for i32 clmulr/clmulh on RV64.
2023-07-18 10:39:25 -07:00
rv64zbkb-intrinsic.ll
[RISCV] Support i32 brev8 intrinsic on RV64.
2023-07-06 17:24:53 -07:00
rv64zbkb.ll
[RISCV] Add more packh patterns.
2023-11-11 19:31:23 -08:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
[RISCV] Use bset+addi for (not (sll -1, X)).
2023-11-16 11:14:53 -08:00
rv64zfh-half-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
rv64zfh-half-convert.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfh-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfhmin-half-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
rv64zfhmin-half-convert.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfhmin-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zknh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksed-intrinsic-autoupgrade2.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksed-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv64zksed-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksh-intrinsic-autoupgrade.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rve.ll
[RISCV][MC] Add support for RV64E
2023-03-23 12:32:25 +00:00
sadd_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
sadd_sat.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
saverestore-scs.ll
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
saverestore.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
sdata-limit-0.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-limit-4.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-limit-8.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-local-sym.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdiv-pow2-cmov.ll
[RISCV][SDAG] Prefer ShortForwardBranch to lower sdiv by pow2 (#67364)
2023-11-10 21:38:47 +08:00
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll
[RISCV] Combine (and (select cond, x, -1), c) to (select cond, x, (and x, c)) with Zicond. (#69563)
2023-10-19 16:11:11 +08:00
select-cc.ll
…
select-const.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
select-constant-xor.ll
…
select-optimize-multiple.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
select-optimize-multiple.mir
…
select-or.ll
…
select-to-and-zext.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
select.ll
[TargetLowering][RISCV] Introduce shouldFoldSelectWithSingleBitTest and RISC-V implement. (#72978)
2023-11-22 08:22:14 +08:00
selectcc-to-shiftand.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
setcc-logic.ll
…
sext-zext-trunc.ll
[SDAG] Prefer forming sign_extend for zext nneg per target preference (#70725)
2023-10-30 15:29:57 -07:00
sextw-removal-debug.mir
[RISCV] Ignore debug instructions in hasAllNBitUsers in RISCVOptWInstrs.
2023-12-03 21:27:50 -08:00
sextw-removal.ll
[RISCV] Add vmv.x.s to RISCVOptWInstrs. (#74519)
2023-12-06 17:06:56 -08:00
shadowcallstack.ll
[RISCV] Make SCS prologue interrupt safe on RISC-V
2023-04-26 15:58:09 +00:00
shift-amount-mod.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shift-and.ll
…
shift-masked-shamt.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shifts.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
shl-demanded.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
shlimm-addimm.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
short-forward-branch-opt.ll
[RISCV] Use short forward branch for ISD::ABS.
2023-11-21 11:00:06 -08:00
shrinkwrap-jump-table.ll
BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads
2023-10-24 20:27:39 -07:00
shrinkwrap.ll
…
signbit-test.ll
…
signed-truncation-check.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
sink-icmp.ll
…
spill-fpr-scalar.ll
[RISCVInsertVSETVLI] Default to VL=1 for scalar extracts
2023-08-16 07:35:00 -07:00
spir-kernel-cc.ll
[OpenCL][RISCV] Support SPIR_KERNEL calling convention (#69282)
2023-10-19 11:00:39 +08:00
split-offsets.ll
[RISCV] Add sink-and-fold support for RISC-V. (#67602)
2023-10-07 10:38:35 -07:00
split-sp-adjust.ll
…
split-store.ll
…
split-udiv-by-constant.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
split-urem-by-constant.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
srem-lkk.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
srem-seteq-illegal-types.ll
[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
2023-11-17 12:02:58 -08:00
srem-vector-lkk.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
ssub_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
ssub_sat.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
stack-folding.ll
…
stack-inst-compress.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
stack-protector-target.ll
[RISCV] Clean up stack-protector-target test
2023-02-06 16:42:59 -08:00
stack-realignment-with-variable-sized-objects.ll
…
stack-realignment.ll
…
stack-slot-coloring.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
stack-slot-size.ll
…
stack-store-check.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
subtarget-features-std-ext.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
switch-width.ll
…
tagged-globals.ll
…
tail-calls.ll
[RISCV] Permit tail call to an externally-defined function with weak linkage
2023-02-03 09:38:46 +08:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
…
trunc-free.ll
…
uadd_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
uadd_sat.ll
…
umulo-128-legalisation-lowering.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
unaligned-load-store.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
unfold-masked-merge-scalar-variablemask.ll
…
unroll-loop-cse.ll
…
urem-lkk.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
urem-seteq-illegal-types.ll
[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
2023-11-17 12:02:58 -08:00
urem-vector-lkk.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
usub_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
usub_sat.ll
…
vararg.ll
[RISCV] Support FrameIndex operands in getMemOperandsWithOffsetWidth / getMemOperandWithOffsetWidth (#73802)
2023-12-05 21:26:56 +00:00
vector-abi.ll
…
verify-instr.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
vlenb.ll
…
vscale-demanded-bits.ll
SelectionDAG: Teach ComputeKnownBits about VSCALE
2023-05-26 10:48:49 -07:00
wide-mem.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
wide-scalar-shift-legalization.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
xaluo.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
xtheadfmemidx.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
xtheadmac.ll
[RISCV] xtheadmac: fix commutativity issue for the in/out register
2023-02-17 19:45:22 +01:00
xtheadmemidx.ll
[RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
2023-02-24 00:17:58 +01:00
xtheadmempair.ll
[RISCV] XTHeadMemPair: Fix invalid mempair combine for types other than i32/i64
2023-02-22 19:57:37 +01:00
zbb-cmp-combine.ll
[DAGCombiner][RISCV][AArch64][PowerPC] Restrict foldAndOrOfSETCC from using SMIN/SMAX where and OR/AND would do.
2023-08-23 20:26:23 -07:00
zcmp-prolog-epilog-crash.mir
[RISCV] Fix assertion failure when zcmp extension is enabled.
2023-08-29 22:06:30 -07:00
zcmp-with-float.ll
[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)
2023-09-25 12:05:05 +08:00
zdinx-asm-constraint.ll
[RISCV] Use correct register class for Z[df]inx inline asm (#71872)
2023-11-17 16:17:48 +01:00
zdinx-boundary-check.ll
[RISCV] Enable alias analysis by default
2023-08-10 10:48:43 +08:00
zext-with-load-is-free.ll
…
zfbfmin.ll
[RISCV] Add codegen for Zfbfmin instructions
2023-07-24 10:37:58 +08:00
zfh-half-intrinsics-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfh-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-half-intrinsics-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-imm.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zmmul.ll
…