Benjamin Maxwell 62cae9c3de
[AArch64] Don't use LowerToPredicatedOp to shufflevector -> SVE lowerings (#140713)
The use of `LowerToPredicatedOp` here seems like a mistake as
`LowerToPredicatedOp` turns the SDValue passed to it into the desired
predicated node by copying over operands (and adding a predicate). This
results in two odd things here, the BITCASTs created and passed to
`LowerToPredicatedOp` are not used, only the operands of those bitcasts
are taken. Secondly, when a shuffle vector node is passed directly to
`LowerToPredicatedOp` to create a `REVD_MERGE_PASSTHRU` node an invalid
REV node is created as REV only takes one vector operand, but both
operands from the shuffle vector are copied to the new REV node. This is
not an issue in practice as the extra operand is ignored.

These issues were found by the verification added in #140472.

Part of #140472.

Note: Test changes only result in the vxf64 lowering matching the vxi64
lowering.
2025-05-23 08:43:10 +01:00
..
2025-03-30 16:38:16 -07:00

++ SVE CodeGen Warnings ++

When the WARN check lines fail in the SVE codegen tests it most likely means you
have introduced a warning due to:
1. Adding an invalid call to VectorType::getNumElements() or EVT::getVectorNumElements()
   when the type is a scalable vector.
2. Relying upon an implicit cast conversion from TypeSize to uint64_t.

For generic code, please modify your code to work with ElementCount and TypeSize directly.
For target-specific code that only deals with fixed-width vectors, use the fixed-size interfaces.
Please refer to the code where those functions live for more details.