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llvm-project/llvm/test/CodeGen/PowerPC
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Matt Arsenault bb18e49edb
RegAlloc: Use DiagnosticInfo to report register allocation failures (#119492) 
Improve the non-fatal cases to use DiagnosticInfo, which will now
provide a location. The allocators attempt to report different errors
if it happens to see inline assembly is involved (this detection is
quite unreliable) using srcloc instead of dbgloc. For now, leave this
behavior unchanged. I think reporting the full location and context
function would be more useful.
2024-12-16 10:49:08 +09:00
..
GlobalISel
[PowerPC][GISel] Add initial GlobalISel support for vector functions.
2023-03-27 08:23:05 -05:00
2004-11-29-ShrCrash.ll
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2004-11-30-shift-crash.ll
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2004-11-30-shr-var-crash.ll
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2004-12-12-ZeroSizeCommon.ll
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2005-01-14-SetSelectCrash.ll
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2005-01-14-UndefLong.ll
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2005-08-12-rlwimi-crash.ll
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2005-09-02-LegalizeDuplicatesCalls.ll
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2005-10-08-ArithmeticRotate.ll
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2005-11-30-vastart-crash.ll
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2006-01-11-darwin-fp-argument.ll
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2006-01-20-ShiftPartsCrash.ll
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2006-04-01-FloatDoubleExtend.ll
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2006-04-05-splat-ish.ll
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2006-04-19-vmaddfp-crash.ll
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2006-05-12-rlwimi-crash.ll
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2006-07-07-ComputeMaskedBits.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
2006-07-19-stwbrx-crash.ll
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2006-08-11-RetVector.ll
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2006-08-15-SelectionCrash.ll
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2006-09-28-shift_64.ll
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2006-10-13-Miscompile.ll
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2006-10-17-brcc-miscompile.ll
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2006-10-17-ppc64-alloca.ll
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2006-11-10-DAGCombineMiscompile.ll
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2006-11-29-AltivecFPSplat.ll
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2006-12-07-LargeAlloca.ll
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2006-12-07-SelectCrash.ll
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2007-01-04-ArgExtension.ll
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2007-01-15-AsmDialect.ll
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2007-01-29-lbrx-asm.ll
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2007-01-31-InlineAsmAddrMode.ll
Reland "[PowerPC] Add error for incorrect use of memory operands (#114277)" (#115958)
2024-11-13 22:24:19 -05:00
2007-02-16-AlignPacked.ll
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2007-02-16-InlineAsmNConstraint.ll
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2007-02-23-lr-saved-twice.ll
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2007-03-24-cntlzd.ll
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2007-03-30-SpillerCrash.ll
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2007-04-24-InlineAsm-I-Modifier.ll
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2007-04-30-InlineAsmEarlyClobber.ll
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2007-05-03-InlineAsm-S-Constraint.ll
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2007-05-14-InlineAsmSelectCrash.ll
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2007-05-22-tailmerge-3.ll
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2007-05-30-dagcombine-miscomp.ll
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2007-06-28-BCCISelBug.ll
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2007-08-04-CoalescerAssert.ll
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2007-09-04-AltivecDST.ll
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2007-09-07-LoadStoreIdxForms.ll
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2007-09-08-unaligned.ll
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2007-09-11-RegCoalescerAssert.ll
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2007-09-12-LiveIntervalsAssert.ll
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2007-10-16-InlineAsmFrameOffset.ll
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2007-10-18-PtrArithmetic.ll
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2007-10-21-LocalRegAllocAssert2.ll
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2007-10-21-LocalRegAllocAssert.ll
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2007-11-04-CoalescerCrash.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
2007-11-16-landingpad-split.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
2007-11-19-VectorSplitting.ll
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2008-02-05-LiveIntervalsAssert.ll
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2008-02-09-LocalRegAllocAssert.ll
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2008-03-05-RegScavengerAssert.ll
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2008-03-17-RegScavengerCrash.ll
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2008-03-18-RegScavengerAssert.ll
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2008-03-24-AddressRegImm.ll
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2008-03-24-CoalescerBug.ll
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2008-03-26-CoalescerBug.ll
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2008-04-10-LiveIntervalCrash.ll
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2008-04-16-CoalescerBug.ll
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2008-04-23-CoalescerCrash.ll
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2008-05-01-ppc_fp128.ll
[IR] Remove support for icmp and fcmp constant expressions (#93038)
2024-06-04 08:31:03 +02:00
2008-06-19-LegalizerCrash.ll
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2008-06-21-F128LoadStore.ll
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2008-06-23-LiveVariablesCrash.ll
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2008-07-10-SplatMiscompile.ll
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2008-07-15-Bswap.ll
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2008-07-15-Fabs.ll
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2008-07-15-SignExtendInreg.ll
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2008-07-17-Fneg.ll
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2008-07-24-PPC64-CCBug.ll
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2008-09-12-CoalescerBug.ll
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2008-10-17-AsmMatchingOperands.ll
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2008-10-28-f128-i32.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
2008-10-28-UnprocessedNode.ll
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2008-12-02-LegalizeTypeAssert.ll
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2009-01-16-DeclareISelBug.ll
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2009-03-17-LSRBug.ll
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2009-05-28-LegalizeBRCC.ll
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2009-07-16-InlineAsm-M-Operand.ll
Reland "[PowerPC] Add error for incorrect use of memory operands (#114277)" (#115958)
2024-11-13 22:24:19 -05:00
2009-08-17-inline-asm-addr-mode-breakage.ll
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2009-09-18-carrybit.ll
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2009-11-15-ProcImpDefsBug.ll
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2009-11-25-ImpDefBug.ll
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2010-02-04-EmptyGlobal.ll
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2010-02-12-saveCR.ll
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2010-03-09-indirect-call.ll
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2010-04-01-MachineCSEBug.ll
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2010-05-03-retaddr1.ll
[PowerPC] return correct frame address for frameaddress intrinsic
2024-06-07 05:17:22 -04:00
2010-10-11-Fast-Varargs.ll
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2010-12-18-PPCStackRefs.ll
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2011-12-05-NoSpillDupCR.ll
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2011-12-06-SpillAndRestoreCR.ll
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2011-12-08-DemandedBitsMiscompile.ll
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2012-09-16-TOC-entry-check.ll
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2012-10-11-dynalloc.ll
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2012-10-12-bitcast.ll
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2012-11-16-mischedcall.ll
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2013-05-15-preinc-fold.ll
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2013-07-01-PHIElimBug.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
2016-01-07-BranchWeightCrash.ll
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2016-04-16-ADD8TLS.ll
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2016-04-17-combine.ll
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2016-04-28-setjmp.ll
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2018-09-19-sextinreg-vector-crash.ll
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a2-fp-basic.ll
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aa-tbaa.ll
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aantidep-def-ec.mir
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aantidep-inline-asm-use.ll
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absol-jump-table-enabled.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
add_cmp.ll
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add-fi.ll
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addc.ll
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adde_return_type.ll
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addegluecrash.ll
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addi-licm.ll
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addi-offset-fold.ll
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addi-reassoc.ll
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addisdtprelha-nonr3.mir
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addrfuncstr.ll
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addrspacecast.ll
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addze.ll
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aggressive-anti-dep-breaker-subreg.ll
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aix32-cc-abi-vaarg.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
aix32-crsave.mir
[PowerPC] Spill non-volatile registers required for traceback table (#71115)
2024-05-07 16:23:37 -04:00
aix32-p8-scalar_vector_conversions.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
aix32-vector-pair-cc-spills.ll
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aix32-vector-vararg-callee-split.ll
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aix32-vector-vararg-callee.ll
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aix32-vector-vararg-caller-split.ll
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aix32-vector-vararg-fixed-callee.ll
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aix64-cc-abi-vaarg.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
aix64-cc-byval.ll
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aix64-csr-alloc.mir
[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)
2024-11-04 12:57:26 -05:00
aix64-vector-pair-cc-spills.ll
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aix64-vector-vararg-callee.ll
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aix64-vector-vararg-fixed-callee.ll
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aix64-virtual-call-no-spills.ll
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aix64-xcoff-roptr.ll
[AIX][CodeGen] Renaming mroptr to xcoff-mroptr
2023-03-31 10:09:48 -04:00
aix_scalar_vector_permuted.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
aix-aggressive-merge-const.ll
[GlobalMerge] Aggressively merge constants to reduce TOC entries (#111756)
2024-10-24 10:16:39 -04:00
aix-alias-alignment-2.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-alias-alignment-3.ll
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aix-alias-alignment.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-alias-unsupported.ll
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aix-alias.ll
[AIX] In assembly file, create a dummy text renamed to an empty string (#73052)
2023-12-04 17:35:47 -06:00
aix-alloca-r31.ll
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aix-AppendingLinkage.ll
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aix-aux-header.ll
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aix-available-externally-linkage-fun.ll
[PowerPC] Function descriptor symbol may be omitted for external symbol. #97526
2024-07-08 03:47:33 -04:00
aix-available-externally-linkage.ll
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aix-base-pointer.ll
[PPC][AIX] Save/restore r31 when using base pointer (#100182)
2024-08-07 09:59:45 -04:00
aix-bytestring.ll
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aix-calleesavedregs.ll
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aix-cc-abi-mir.ll
[PowerPC] Add special handling for arguments that are smaller than pointer size. (#119003)
2024-12-12 09:43:53 -05:00
aix-cc-abi.ll
[PowerPC] Add special handling for arguments that are smaller than pointer size. (#119003)
2024-12-12 09:43:53 -05:00
aix-cc-altivec.ll
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aix-cc-byval-limitation3.ll
[PowerPC][AIX] Support ByVals with greater alignment then pointer size (#93341)
2024-06-05 12:19:16 -04:00
aix-cc-byval-mem.ll
[AIX] Lower some memory intrinsics to millicode functions on AIX
2023-02-20 22:25:49 -05:00
aix-cc-byval-split.ll
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aix-cc-byval.ll
Reland rGf35a09daebd0a90daa536432e62a2476f708150d and rG63854f91d3ee1056796a5ef27753648396cac6ec
2023-03-12 21:59:18 -04:00
aix-cc-ext-vec-abi.ll
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aix-codemodel-attr.ll
[AIX] Support per global code model. (#79202)
2024-03-15 12:52:04 -04:00
aix-command-line-metadata.ll
Implement -frecord-command-line for XCOFF integrated assembler path
2023-07-20 09:45:37 -04:00
aix-common.ll
[XCOFF][AIX] Issue an error when specifying an alias for a common symbol
2023-08-31 11:43:47 -04:00
aix-complex.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
aix-constant-align.ll
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aix-cpu-version-multifunction.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-cpu-version.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-crspill.ll
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aix-csr-alloc.mir
[PowerPC] Use MIR test so that it's not affected by instruction selection. NFC.
2023-11-20 09:51:12 +00:00
aix-csr-vector-extabi.ll
[PowerPC] Spill non-volatile registers required for traceback table (#71115)
2024-05-07 16:23:37 -04:00
aix-csr-vector.ll
[PowerPC] Spill non-volatile registers required for traceback table (#71115)
2024-05-07 16:23:37 -04:00
aix-csr.ll
[PowerPC] Spill non-volatile registers required for traceback table (#71115)
2024-05-07 16:23:37 -04:00
aix-dfltabi-rsrvd-reg.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
aix-dwarf.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
aix-ehinfo-sym.ll
[PowerPC] Move __ehinfo TOC entries to the end of the TOC section (#73586)
2023-12-08 15:03:11 -05:00
aix-emit-tracebacktable-clobber-register.ll
[PowerPC] Move __ehinfo TOC entries to the end of the TOC section (#73586)
2023-12-08 15:03:11 -05:00
aix-emit-tracebacktable-redzone-boundary.mir
[AIX] unset bit "IsBackChainStored" of traceback table for leaf functions with no stack frame
2023-03-16 15:26:12 -04:00
aix-emit-tracebacktable-ssp.ll
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aix-emit-tracebacktable-vectorinfo_hasvarg.ll
[AIX] unset bit "IsBackChainStored" of traceback table for leaf functions with no stack frame
2023-03-16 15:26:12 -04:00
aix-emit-tracebacktable-vectorinfo.ll
[AIX] unset bit "IsBackChainStored" of traceback table for leaf functions with no stack frame
2023-03-16 15:26:12 -04:00
aix-emit-tracebacktable.ll
[AIX] unset bit "IsBackChainStored" of traceback table for leaf functions with no stack frame
2023-03-16 15:26:12 -04:00
aix-exception.ll
[PowerPC] Move __ehinfo TOC entries to the end of the TOC section (#73586)
2023-12-08 15:03:11 -05:00
aix-extern-weak.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-extern.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-external-sym-sdnode-lowering.ll
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aix-filename-absolute-path.ll
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aix-filename-c.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-filename-cpp.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-filename-f.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-filename-relative-path.ll
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aix-filename-special-character-double-quotation.ll
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aix-filename-special-character-single-quotation.ll
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aix-fptoint.ll
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aix-framepointer-save-restore.ll
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aix-func-align.ll
[AIX] In assembly file, create a dummy text renamed to an empty string (#73052)
2023-12-04 17:35:47 -06:00
aix-func-dsc-gen.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-ignore-xcoff-visibility.ll
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aix-indirect-call.ll
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aix-inline-asm-clobber-warning.ll
[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)
2024-11-04 12:57:26 -05:00
aix-inlineasm-reserved-reg-dflt-warn.ll
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aix-insert-extract.ll
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aix-internal.ll
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aix-LinkOnceAnyLinkage.ll
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aix-LinkOnceODRLinkage.ll
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aix-llvm-intrinsic.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-lower-block-address.ll
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aix-lower-constant-pool-index.ll
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aix-lower-jump-table-mir.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-lower-jump-table.ll
BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads
2023-10-24 20:27:39 -07:00
aix-lr.ll
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aix-nest-param.ll
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aix-nonzero-zerofill.ll
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aix-overflow-toc-data.py
[AIX] Handle toc-data offset overflowing 16-bits (#80092)
2024-03-28 13:55:13 -04:00
aix-overflow-toc.py
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-p8vector-liveins.ll
[MIR] Fix tests for flags in register info (#112179)
2024-10-14 18:28:54 +05:30
aix-p9-insert-extract.ll
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aix-p9-xxinsertw-xxextractuw.ll
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aix-personality-alias.ll
[AIX] In assembly file, create a dummy text renamed to an empty string (#73052)
2023-12-04 17:35:47 -06:00
aix-prefixed-instruction-boundary.mir
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aix-print-pc.mir
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aix-readonly-with-relocation.ll
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aix-reference-func-addr-const.ll
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aix-relativeref.ll
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aix-relro-section.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-return55.ll
[XCOFF] Use RLDs to print branches even without -r (#74342)
2023-12-21 08:17:32 -06:00
aix-rodata-align.ll
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aix-shared-lib-tls-model-opt-small-local-dynamic-tls.ll
[PowerPC] Tune AIX shared library TLS model at function level (#84132)
2024-05-09 09:50:36 +08:00
aix-shared-lib-tls-model-opt.ll
[PowerPC] Tune AIX shared library TLS model at function level (#84132)
2024-05-09 09:50:36 +08:00
aix-small-local-dynamic-tls-largeaccess.ll
[PowerPC][AIX] Refactor existing logic to handle non-zero offsets for aix-small-local-dynamic-tls (#89182)
2024-05-08 18:37:51 +08:00
aix-small-local-dynamic-tls-types.ll
[PowerPC][AIX] Refactor existing logic to handle non-zero offsets for aix-small-local-dynamic-tls (#89182)
2024-05-08 18:37:51 +08:00
aix-small-local-exec-tls-char.ll
[AIX][TLS] Optimize the small local-exec access sequence for non-zero offsets (#71485)
2024-02-01 09:29:21 -05:00
aix-small-local-exec-tls-double.ll
[AIX][TLS] Optimize the small local-exec access sequence for non-zero offsets (#71485)
2024-02-01 09:29:21 -05:00
aix-small-local-exec-tls-float.ll
[AIX][TLS] Optimize the small local-exec access sequence for non-zero offsets (#71485)
2024-02-01 09:29:21 -05:00
aix-small-local-exec-tls-int.ll
[AIX][TLS] Optimize the small local-exec access sequence for non-zero offsets (#71485)
2024-02-01 09:29:21 -05:00
aix-small-local-exec-tls-largeaccess2.ll
Fix failing testcases (#80902)
2024-02-06 15:35:21 -05:00
aix-small-local-exec-tls-largeaccess.ll
GlobalsModRef, ValueTracking: Look through threadlocal.address intrinsic (#88418)
2024-04-19 10:01:42 -07:00
aix-small-local-exec-tls-longlong.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-small-local-exec-tls-short.ll
[AIX][TLS] Optimize the small local-exec access sequence for non-zero offsets (#71485)
2024-02-01 09:29:21 -05:00
aix-small-tls-globalvarattr-funcattr.ll
GlobalsModRef, ValueTracking: Look through threadlocal.address intrinsic (#88418)
2024-04-19 10:01:42 -07:00
aix-small-tls-globalvarattr-loadaddr.ll
[AIX][TLS] Produce a faster local-exec access sequence for the "aix-small-tls" global variable attribute (#83053)
2024-03-28 09:18:45 -04:00
aix-small-tls-globalvarattr-targetattr.ll
[AIX][TLS] Produce a faster local-exec access sequence for the "aix-small-tls" global variable attribute (#83053)
2024-03-28 09:18:45 -04:00
aix-space.ll
…
aix-spills-for-eh.ll
[PowerPC] Spill non-volatile registers required for traceback table (#71115)
2024-05-07 16:23:37 -04:00
aix-sret-param.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
aix-static-init-default-priority.ll
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aix-static-init-key-object.ll
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aix-static-init-no-unique-module-id.ll
[AIX] Add threadId and use nanosecond timestamp in sinit/sterm symbols
2023-09-07 17:46:41 +00:00
aix-static-init-non-default-priority.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
aix-text-ref.ll
[PowerPC] Function descriptor symbol may be omitted for external symbol. #97526
2024-07-08 03:47:33 -04:00
aix-text.ll
[XCOFF] make related SD symbols as isFunction (#69553)
2023-11-26 11:59:09 +08:00
aix-tls-gd-double.ll
[PowerPC] Support local-dynamic TLS relocation on AIX (#66316)
2024-03-01 08:09:40 +08:00
aix-tls-gd-int.ll
[PowerPC] Support local-dynamic TLS relocation on AIX (#66316)
2024-03-01 08:09:40 +08:00
aix-tls-gd-longlong.ll
[PowerPC] Remove DAG matching in ADDIStocHA (#93905)
2024-06-04 10:00:43 +08:00
aix-tls-gd-target-flags.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
aix-tls-ie-ldst.ll
[PowerPC] Support initial-exec TLS relocation on AIX
2023-08-30 16:22:16 +08:00
aix-tls-ie-xcoff-reloc.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-tls-ld-xcoff-reloc-large.ll
[PowerPC] Support local-dynamic TLS relocation on AIX (#66316)
2024-03-01 08:09:40 +08:00
aix-tls-le-ldst-double.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-ldst-float.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-ldst-int.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-ldst-longlong.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-ldst-O0.ll
[AIX][TLS] Produce a faster local-exec access sequence with -maix-small-local-exec-tls (And optimize when load/store offsets are 0)
2023-09-07 20:05:29 -05:00
aix-tls-le-xcoff-reloc32.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-tls-le-xcoff-reloc-large32.ll
[PowerPC] Remove DAG matching in ADDIStocHA (#93905)
2024-06-04 10:00:43 +08:00
aix-tls-le-xcoff-reloc-large.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-tls-le-xcoff-reloc.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-tls-local-dynamic.ll
[PowerPC] Support local-dynamic TLS relocation on AIX (#66316)
2024-03-01 08:09:40 +08:00
aix-tls-variables-ppc32.ll
…
aix-tls-variables-ppc64.ll
…
aix-tls-xcoff-reloc-large.ll
[PowerPC] Remove DAG matching in ADDIStocHA (#93905)
2024-06-04 10:00:43 +08:00
aix-tls-xcoff-reloc.ll
[PowerPC][NFC] Update aix-tls-xcoff-reloc.ll (#83764)
2024-03-05 14:07:47 +08:00
aix-tls-xcoff-variables.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-tocdata-fastisel.ll
[PowerPC] handle toc-data in load selection of fast-isel (#91916)
2024-05-24 11:09:37 +08:00
aix-tracetable-csr.ll
…
aix-trampoline.ll
…
aix-undef-func-call.ll
…
aix-user-defined-memcpy.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-vec_extract_p9_2.ll
…
aix-vec_extract_p9.ll
…
aix-vec_insert_elt.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
aix-vec-arg-spills-callee.ll
…
aix-vec-arg-spills-mir.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-vec-arg-spills.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-vector-byval-callee.ll
[PowerPC][AIX] Support ByVals with greater alignment then pointer size (#93341)
2024-06-05 12:19:16 -04:00
aix-vector-byval.ll
[PowerPC][AIX] Support ByVals with greater alignment then pointer size (#93341)
2024-06-05 12:19:16 -04:00
aix-vector-stack-caller.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-vector-stack.ll
…
aix-vector-vararg-caller.ll
…
aix-vector-vararg-fixed-caller.ll
…
aix-vsx-splatimm.ll
[PowerPC] improve P10 store forwarding on P7 scalar to vector (#102330)
2024-08-12 12:30:06 -04:00
aix-weak-reloc.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
aix-weak-undef-func-call.ll
…
aix-weak.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-WeakODRLinkage.ll
…
aix-xcoff-cold.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-xcoff-data-only-notoc.ll
…
aix-xcoff-data-sections.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-xcoff-data.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-xcoff-endian-error.ll
…
aix-xcoff-error-explicit-data-section.ll
…
aix-xcoff-exception-section-debug.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
aix-xcoff-exception-section.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
aix-xcoff-explicit-section.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-xcoff-externL.ll
…
aix-xcoff-funcsect-explicitsect.ll
[PowerPC][AIX] support explicit sections for -ffunction-sections (#85351)
2024-03-22 13:23:36 +08:00
aix-xcoff-funcsect.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-xcoff-huge-relocs.ll
…
aix-xcoff-lcomm.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-xcoff-lower-comm.ll
…
aix-xcoff-mergeable-const.ll
Enable aggressive constant merge in GlobalMerge for AIX (#113956)
2024-10-31 11:22:48 -04:00
aix-xcoff-mergeable-str.ll
[PPC] Remove missed cases of ppc-merge-string-pool (#117626)
2024-12-03 13:31:26 -05:00
aix-xcoff-reloc-large.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-xcoff-reloc-symb.mir
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-xcoff-reloc.ll
[PowerPC][AIX] Emit PowerPC version for XCOFF (#113214)
2024-12-10 11:11:50 -05:00
aix-xcoff-rodata.ll
[PPC] Remove missed cases of ppc-merge-string-pool (#117626)
2024-12-03 13:31:26 -05:00
aix-xcoff-roptr.ll
[AIX][CodeGen] Renaming mroptr to xcoff-mroptr
2023-03-31 10:09:48 -04:00
aix-xcoff-symbol-rename.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
aix-xcoff-textdisassembly.ll
…
aix-xcoff-tls-rename.ll
…
aix-xcoff-toc.ll
…
aix-xcoff-used-with-stringpool.ll
[PPC] Remove missed cases of ppc-merge-string-pool (#117626)
2024-12-03 13:31:26 -05:00
aix-xcoff-used.ll
…
aix-xcoff-visibility.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
alias.ll
…
align.ll
…
alignlongjumptest.mir
…
all-atomics.ll
Reapply "AtomicExpand: Allow incrementally legalizing atomicrmw" (#107307)
2024-09-06 18:37:34 +04:00
alloca-crspill.ll
…
alloca-oversized.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
allocate-r0.ll
…
altivec-ord.ll
…
and_add.ll
…
and_sext.ll
[PowerPC] Regenerate and_sext.ll with test checks
2024-05-14 11:58:48 +01:00
and_sra.ll
…
and-branch.ll
…
and-elim.ll
…
and-extend-combine.ll
[PowerPC] Use zext instead of anyext in custom and combine (#68784)
2023-10-12 09:32:17 +02:00
and-imm.ll
…
and-mask.ll
…
andc.ll
…
anon_aggr.ll
…
anyext_srl.ll
…
arg_promotion.ll
[IR] Change shufflevector undef mask to poison
2023-04-27 14:41:10 +01:00
arr-fp-arg-no-copy.ll
…
ashr-neg1.ll
…
asm-constraints.ll
…
asm-dialect.ll
…
asm-printer-topological-order.ll
…
asm-template-I.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
asm-Zy.ll
…
asym-regclass-copy.ll
…
atomic-1.ll
…
atomic-2.ll
…
atomic-float.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
atomic-minmax.ll
[PowerPC] Update incr after resetting the register in MI
2023-04-14 17:36:30 +08:00
atomicrmw-cond-sub-clamp.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
atomicrmw-uinc-udec-wrap.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
Atomics-64.ll
…
atomics-constant.ll
…
atomics-fences.ll
…
atomics-i8-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics-i16-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics-i32-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics-i64-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics-i128-ldst.ll
[CodeGen] Remove target SubRegLiveness flags (#95437)
2024-06-14 08:51:56 +01:00
atomics-i128.ll
[CodeGen] Remove target SubRegLiveness flags (#95437)
2024-06-14 08:51:56 +01:00
atomics-indexed.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
atomics-regression.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
available-externally.ll
…
basic-toc-data-def.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
basic-toc-data-extern.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
basic-toc-data-local-linkage.ll
[AIX] [XCOFF] Add support for common and local common symbols in the TOC (#79530)
2024-01-31 16:34:21 -05:00
basic-toc-data-private-linkage.ll
[AIX] [XCOFF] Add support for common and local common symbols in the TOC (#79530)
2024-01-31 16:34:21 -05:00
bcd-intrinsics.ll
…
bdzlr.ll
…
bfloat16-outer-product.ll
…
big-endian-actual-args.ll
…
big-endian-call-result.ll
…
big-endian-formal-args.ll
…
big-endian-store-forward.ll
CodeGen/test: improve a test, regen with UTC (#113338)
2024-11-04 11:29:25 +00:00
bitcast-peephole.mir
[CodeGen][NewPM] Port PeepholeOptimizer to NPM (#116326)
2024-11-18 11:02:01 +05:30
bitcasts-direct-move.ll
…
bitfieldinsert.ll
…
block-placement-1.mir
…
block-placement.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
blockaddress.ll
…
bool-math.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
BoolRetToIntTest-2.ll
…
BoolRetToIntTest.ll
…
botheightreduce.mir
…
bperm.ll
…
branch_coalesce.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
branch_coalescing.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
branch_selector.ll
…
branch-hint.ll
…
branch-on-store-cond.ll
[ShrinkWrap] Use underlying object to rule out stack access.
2023-05-03 09:28:07 +01:00
branch-opt.ll
…
brcond.ll
…
BreakableToken-reduced.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
bswap64.ll
…
bswap-load-store.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
build-vector-allones.ll
…
build-vector-from-load-and-zeros.ll
[PowerPC] special case small int constant for custom scalar_to_vector (#109850)
2024-10-21 12:19:07 -04:00
build-vector-tests.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
build-vector-to-ld-chain.ll
…
buildvec_canonicalize.ll
…
builtins-bcd-assist.ll
[PPC] Implement BCD assist builtins (#101390)
2024-08-07 13:38:48 -04:00
builtins-ppc-bcd-assist.ll
[PPC] Implement BCD assist builtins (#101390)
2024-08-07 13:38:48 -04:00
builtins-ppc-elf2-abi.ll
…
builtins-ppc-p8vector.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
builtins-ppc-p9-darn.ll
…
builtins-ppc-p9-f128.ll
…
builtins-ppc-p10permute.ll
…
builtins-ppc-p10vsx.ll
[PowerPC] Update InputOps of Power10 SchedModel
2023-07-07 22:46:22 +08:00
builtins-ppc-xlcompat-check-ldarx-opt.ll
…
builtins-ppc-xlcompat-cmpb-32.ll
…
builtins-ppc-xlcompat-cmpb-64.ll
…
builtins-ppc-xlcompat-compare-64bit-only.ll
…
builtins-ppc-xlcompat-compare.ll
…
builtins-ppc-xlcompat-conversionfunc.ll
…
builtins-ppc-xlcompat-fnabs.ll
…
builtins-ppc-xlcompat-fp.ll
…
builtins-ppc-xlcompat-load-store-reversed-64bit-only.ll
…
builtins-ppc-xlcompat-load-store-reversed.ll
…
builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
[PowerPC] Fix mask for __st[d/w/h/b]cx builtins (#104453)
2024-08-22 09:55:46 -04:00
builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
[PowerPC] Fix mask for __st[d/w/h/b]cx builtins (#104453)
2024-08-22 09:55:46 -04:00
builtins-ppc-xlcompat-math.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
builtins-ppc-xlcompat-maxmin.ll
…
builtins-ppc-xlcompat-mfspr-mtspr-64bit-only.ll
…
builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
…
builtins-ppc-xlcompat-move-tofrom-regs.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
builtins-ppc-xlcompat-msync.ll
…
builtins-ppc-xlcompat-multiply-64bit-only.ll
…
builtins-ppc-xlcompat-multiply.ll
…
builtins-ppc-xlcompat-popcnt.ll
…
builtins-ppc-xlcompat-prefetch.ll
…
builtins-ppc-xlcompat-pwr9-64bit.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
builtins-ppc-xlcompat-pwr9.ll
…
builtins-ppc-xlcompat-stfiw.ll
…
builtins-ppc-xlcompat-sync-32.ll
…
builtins-ppc-xlcompat-sync-64.ll
…
builtins-ppc-xlcompat-test.ll
…
builtins-ppc-xlcompat-trap-64bit-only.ll
…
builtins-ppc-xlcompat-trap-annotations-td.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
builtins-ppc-xlcompat-trap-annotations-tw.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
builtins-ppc-xlcompat-trap.ll
…
bv-pres-v8i1.ll
…
bv-widen-undef.ll
…
byval-agg-info.ll
…
byval-aliased.ll
…
byval-lhs.ll
Reland rGf35a09daebd0a90daa536432e62a2476f708150d and rG63854f91d3ee1056796a5ef27753648396cac6ec
2023-03-12 21:59:18 -04:00
byval.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
callbr-asm-outputs-indirect-isel.ll
[llvm][test] enable/disable -verify-machineinstrs where possible for callbr
2023-02-16 20:28:18 -08:00
calls.ll
…
can-lower-ret.ll
…
cannonicalize-vector-shifts.ll
…
canonical-merge-shuffles.ll
[PowerPC] special case small int constant for custom scalar_to_vector (#109850)
2024-10-21 12:19:07 -04:00
cc.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
cfence-double.ll
[llvm] Remove explicit -opaque-pointers flag from tests (NFC)
2023-07-12 14:35:55 +02:00
cfence-float.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
cfence-i128.ll
…
cgp-select.ll
…
change-no-infs.ll
…
check-aix-shared-lib-tls-model-opt-IRattribute.ll
[PowerPC] Tune AIX shared library TLS model at function level (#84132)
2024-05-09 09:50:36 +08:00
check-aix-shared-lib-tls-model-opt-Option.ll
[PowerPC] Tune AIX shared library TLS model at function level (#84132)
2024-05-09 09:50:36 +08:00
check-aix-small-local-exec-tls-opt-IRattribute.ll
[PowerPC][AIX] Enable aix-small-local-dynamic-tls target attribute (#86641)
2024-04-12 08:18:01 +08:00
check-aix-small-local-exec-tls-opt.ll
[PowerPC][AIX] Enable aix-small-local-dynamic-tls target attribute (#86641)
2024-04-12 08:18:01 +08:00
check-cpu.ll
[PowerPC] Add support for -mcpu=pwr11 / -mtune=pwr11 (#99511)
2024-07-23 09:49:41 -04:00
cmp_elimination.ll
[PPCMIPeephole] Fix incorrect compare elimination
2023-04-24 10:02:06 -07:00
cmp-cmp.ll
…
cmpb-ppc32.ll
…
cmpb.ll
…
coalesce-ext.ll
…
code-align.ll
…
codemodel.ll
…
coldcc2.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
coldcc.ll
…
collapse-rotates.mir
…
combine_ext_trunc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
combine-fneg.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
combine-setcc.ll
…
combine-sext-and-shl-after-isel.ll
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
combine-to-mulh-shift-amount.ll
…
combine-to-pre-index-store-crash.ll
…
common-chain-aix32.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
common-chain.ll
[LICM] Prevent fold and hoist of binary ops with over 2 uses (#102114)
2024-08-07 09:52:30 +01:00
compare-duplicate.ll
…
compare-simm.ll
…
CompareEliminationSpillIssue.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
complex-return.ll
…
compute-regpressure.ll
…
const-nonsplat-array-init.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
const-splat-array-init.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
const-stov.ll
[PowerPC] special case small int constant for custom scalar_to_vector (#109850)
2024-10-21 12:19:07 -04:00
constant-combines.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
constant-pool.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
constants-i64.ll
[PowerPC] Try to use less instructions to materialize 64-bit constant when High32=Low32.
2023-09-07 13:03:17 -04:00
constants.ll
…
convert-ri-addi-to-ri.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
convert-rr-to-ri-instr-add.mir
…
convert-rr-to-ri-instrs-kill-flag.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
convert-rr-to-ri-instrs-out-of-range.mir
Promote 32bit pseudo instr that infer extsw removal to 64bit in PPCMIPeephole (#85451)
2024-10-31 15:49:36 -04:00
convert-rr-to-ri-instrs-R0-special-handling.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
convert-rr-to-ri-instrs.mir
Promote 32bit pseudo instr that infer extsw removal to 64bit in PPCMIPeephole (#85451)
2024-10-31 15:49:36 -04:00
convert-rr-to-ri-p9-vector.mir
…
copysignl.ll
[PowerPC] copysignl.ll - regenerate to reduce the diff in #111269
2024-10-29 10:57:43 +00:00
cpu-supports.ll
[PowerPC][X86] Make cpu id builtins target independent and lower for PPC (#68919)
2024-01-26 11:24:50 -05:00
cr1eq-no-extra-moves.ll
…
cr1eq.ll
…
cr_spilling.ll
…
cr-spills.ll
…
crash.ll
…
crbit-asm-disabled.ll
…
crbit-asm.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
crbits.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
crsave.ll
[PowerPC] provide CFI for ELF32 to unwind cr2, cr3, cr4 (#83098)
2024-03-02 22:18:24 -05:00
crypto_bifs_be.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
crypto_bifs.ll
…
cse-despite-rounding-mode.ll
…
CSR-fit.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
csr-save-restore-order.ll
…
csr-split.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
ctr-cleanup.ll
…
ctr-loop-tls-const.ll
…
ctr-minmaxnum.ll
…
ctrloop-asm.ll
…
ctrloop-constrained-fp.ll
Emit constrained atan2 intrinsic for clang builtin (#113636)
2024-11-12 13:34:29 -08:00
ctrloop-cpsgn.ll
…
ctrloop-do-not-duplicate-mi.mir
…
ctrloop-fp64.ll
…
ctrloop-fp128.ll
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
2024-11-12 14:02:01 -05:00
ctrloop-i64.ll
…
ctrloop-i128.ll
…
ctrloop-intrin.ll
…
ctrloop-large-ec.ll
…
ctrloop-le.ll
[SCEV] Support ule/sle exit counts via widening (#92206)
2024-05-23 07:54:08 +02:00
ctrloop-lt.ll
…
ctrloop-ne.ll
…
ctrloop-reg.ll
…
ctrloop-s000.ll
…
ctrloop-sh.ll
[Codegen][LegalizeIntegerTypes] Improve shift through stack (#96151)
2024-09-23 11:45:43 +02:00
ctrloop-shortLoops.ll
…
ctrloop-sums.ll
…
ctrloop-udivti3.ll
…
ctrloops32.mir
…
ctrloops64.mir
…
ctrloops-hot-exit.ll
…
ctrloops-pseudo.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
ctrloops-softfloat.ll
…
ctrloops.ll
…
cttz.ll
…
custom-stov.ll
[PowerPC] fix legalization crash (#105563)
2024-08-28 11:22:23 -04:00
cvt_i64_to_fp.ll
…
cxx_tlscc64.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
darwin-labels.ll
…
data-align.ll
[PowerPC] Update data layout aligment of i128 to 16 (#118004)
2024-12-09 18:02:24 -05:00
dbg.ll
…
DbgValueOtherTargets.test
…
dcbf-p10.ll
…
dcbf.ll
…
dcbt-sched.ll
…
dcbt.ll
…
debug-label-fast-isel.ll
…
debuginfo-split-int.ll
…
debuginfo-stackarg.ll
…
delete-node.ll
…
dform-adjust.ll
…
dform-pair-load-store.ll
…
direct-move-profit.ll
…
disable-ctr-ppcf128.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
DisableHoistingDueToBlockHotnessNoProfileData.mir
[NewPM][CodeGen] Port MachineLICM to NPM (#107376)
2024-09-20 11:34:18 +05:30
DisableHoistingDueToBlockHotnessProfileData.mir
[NewPM][CodeGen] Port MachineLICM to NPM (#107376)
2024-09-20 11:34:18 +05:30
div-2.ll
…
div-e-32.ll
…
div-e-all.ll
…
dscr-set.ll
…
dsolocal-pic.ll
…
dsolocal-static.ll
…
dssall.ll
…
duplicate-returns-for-tailcall.ll
…
dyn-alloca-aligned.ll
…
dyn-alloca-offset.ll
…
e500-1.ll
…
early-ifcvt-no-isel.mir
[CodeGen][NewPM] Port EarlyIfConversion pass to NPM. (#108508)
2024-10-16 13:22:57 +05:30
early-ret2.ll
…
early-ret-verify.mir
…
early-ret.ll
…
early-ret.mir
…
ec-input.ll
…
eh-dwarf-cfa.ll
…
eieio.ll
…
elf64-byval-cc.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
elf-common.ll
…
eliminate-compare-of-copy.ll
…
empty-functions.ll
…
emptystruct.ll
…
emutls_generic.ll
…
eqv-andc-orc-nor.ll
…
exp10-libcall.ll
IR: Add llvm.exp10 intrinsic
2023-09-01 19:45:03 -04:00
expand-contiguous-isel.ll
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
2024-11-12 14:02:01 -05:00
expand-foldable-isel.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
expand-isel-to-branch.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
expand-isel.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
ext-bool-trunc-repl.ll
[IR] Remove zext and sext constant expressions (#71040)
2023-11-03 10:46:07 +01:00
extra-toc-reg-deps.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
extract-and-store.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
extsh.ll
…
extswsli.ll
…
f32-to-i64.ll
…
f128_ldst.ll
…
f128-aggregates.ll
[PowerPC] Respect endianness when bitcasting to fp128 (#95931)
2024-08-08 08:51:04 +08:00
f128-arith.ll
[SDAG] Limit sincos/frexp stack slot folding to stores chained to entry (#115906)
2024-11-12 20:48:41 +00:00
f128-bitcast.ll
[PowerPC] Fix assert exposed by PR 95931 in LowerBITCAST (#108062)
2024-09-10 14:14:01 -04:00
f128-branch-cond.ll
…
f128-compare.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-conv.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-fma.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
f128-passByValue.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
f128-rounding.ll
…
f128-truncateNconv.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-vecExtractNconv.ll
…
fabs.ll
DAG: Remove hasBitPreservingFPLogic
2023-02-14 10:25:24 -04:00
fast-isel-binary.ll
…
fast-isel-br-const.ll
…
fast-isel-branch.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
fast-isel-call.ll
…
fast-isel-cmp-imm.ll
…
fast-isel-const.ll
…
fast-isel-conversion-p5.ll
…
fast-isel-conversion.ll
…
fast-isel-crash.ll
…
fast-isel-ext.ll
…
fast-isel-fcmp-nan.ll
…
fast-isel-fold.ll
…
fast-isel-fpconv.ll
…
fast-isel-GEP-coalesce.ll
…
fast-isel-i64offset.ll
…
fast-isel-icmp-split.ll
…
fast-isel-indirectbr.ll
…
fast-isel-load-store-vsx.ll
…
fast-isel-load-store.ll
…
fast-isel-pcrel.ll
…
fast-isel-redefinition.ll
…
fast-isel-ret.ll
…
fast-isel-rsp.ll
…
fast-isel-shifter.ll
…
fastcc_stacksize.ll
…
fastisel-gep-promote-before-add.ll
…
fcpsgn.ll
…
fdiv-combine.ll
…
fdiv.ll
…
fence.ll
Require asserts for llvm/test/CodeGen/PowerPC/fence.ll
2024-01-15 17:25:49 +01:00
fixup-kill-dead-flag-crash.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
float-asmprint.ll
…
float-load-store-pair.ll
…
float-logic-ops.ll
…
float-to-int.ll
…
float-vector-gather.ll
…
floatPSA.ll
…
flt-preinc.ll
…
fma-aggr-FMF.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fma-assoc.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
fma-combine.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
fma-ext.ll
…
fma-mutate-duplicate-vreg.ll
…
fma-mutate-register-constraint.ll
…
fma-mutate.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
fma-negate.ll
[LegalizeVectorOps][PowerPC] Use xor to expand fneg. (#106595)
2024-08-29 15:00:23 -07:00
fma-precision.ll
…
fma.ll
…
fmaxnum.ll
…
fmf-propagation.ll
Restore "Implement convergence control in MIR using SelectionDAG (#71785)"
2024-03-06 12:19:32 +05:30
fminimum-fmaximum-f128.ll
[Legalizer] Expand fmaximum and fminimum (#67301)
2024-04-29 15:09:54 +08:00
fminimum-fmaximum.ll
DAG: Skip 0 sign handling in minimum/maximum lowering for _ieee case (#91326)
2024-05-09 14:41:13 +02:00
fminnum.ll
…
fnabs.ll
…
fneg.ll
…
fold_swtest_br.ll
…
fold-frame-offset-using-rr.mir
…
fold-li.ll
…
fold-remove-li.ll
…
fold-rlwinm-1.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fold-rlwinm.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
fold-rot-and-peephole.mir
Reland https://reviews.llvm.org/D159073.
2023-09-26 06:24:47 -04:00
fold-zero.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
fp2int2fp-ppcfp128.ll
…
fp64-to-int16.ll
…
fp128-bitcast-after-operation.ll
DAG: Call SimplifyDemandedBits on fcopysign sign value (#97151)
2024-07-01 12:19:17 +02:00
fp128-libcalls.ll
…
fp_to_uint.ll
…
fp-branch.ll
…
fp-classify.ll
DAG: Handle lowering unordered compare with inf (#100378)
2024-09-05 19:54:32 +04:00
fp-int128-fp-combine.ll
…
fp-int-conversions-direct-moves.ll
…
fp-int-fp.ll
…
fp-intrinsics-fptosi-legal.ll
…
fp-splat.ll
…
fp-strict-conv-f128.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fp-strict-conv-spe.ll
PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs
2023-06-21 10:24:40 +00:00
fp-strict-conv.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fp-strict-f128.ll
…
fp-strict-fcmp-noopt.ll
…
fp-strict-fcmp-spe.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
fp-strict-fcmp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fp-strict-minmax.ll
…
fp-strict-round.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
fp-strict.ll
[LegalizeVectorOps][PowerPC] Use xor to expand fneg. (#106595)
2024-08-29 15:00:23 -07:00
fp-to-int-ext.ll
…
fp-to-int-to-fp.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
fpcopy.ll
…
fpscr-intrinsics.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
fptoui-be-crash.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
frame_index_scavenging.mir
…
frame-size.ll
…
frameaddr-alloca.ll
[PowerPC] use r1 as the frame pointer when there is dynamic alloca
2024-06-20 22:26:52 -04:00
frameaddr.ll
[PowerPC] return correct frame address for frameaddress intrinsic
2024-06-07 05:17:22 -04:00
frameindex-negative-offset.ll
[PPC] Use getSignedConstant() for frame index offset
2024-11-28 10:49:45 +01:00
Frames-dyn-alloca-with-func-call.ll
…
Frames-dyn-alloca.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
Frames-large.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
Frames-leaf.ll
…
Frames-small.ll
…
Frames-stack-floor.ll
…
frem.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
frounds.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
fsel.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
fsl-e500mc.ll
…
fsl-e5500.ll
…
fsqrt.ll
…
fsub-fneg.ll
…
ftrunc-legalize.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
ftrunc-vec.ll
…
func-addr-consts.ll
…
func-addr.ll
…
func-alias.ll
[PowerPC] Convert more tests to opaque pointers (NFC)
2023-01-30 04:27:10 +03:00
funnel-shift-rot.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
funnel-shift.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
fusion-load-store.ll
…
future-check-features.ll
…
gcov_ctr_ref_init.ll
[NFC][Test] Fix PowerPC test gcov_ctr_ref_init.ll (#117577)
2024-11-26 12:09:49 -05:00
git_revision.ll
[AIX] Add git revision to .file string (#88164)
2024-04-30 20:37:35 -04:00
glob-comp-aa-crash.ll
…
global-address-non-got-indirect-access.ll
[SDAG] Don't transfer !range metadata without !noundef to SDAG (PR64589)
2023-08-14 09:04:27 +02:00
global-merge-aix-sections.ll
[AsmPrinter] Fix handling in emitGlobalConstantImpl for AIX (#116255)
2024-11-19 09:58:25 -05:00
gnu-attribute.ll
…
gpr-vsr-spill.ll
…
handle-f16-storage-type.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
hardware-loops-crash.ll
[HardwareLoops] NewPM support.
2023-02-13 09:46:31 +00:00
hello.ll
…
hidden-vis-2.ll
…
hidden-vis.ll
…
hoist-logic.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
htm-ttest.ll
…
htm.ll
…
huge-frame-call.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
huge-frame-size.ll
[LLVM] [MC] Update frame layout & CFI generation to handle frames larger than 2gb (#99263)
2024-07-23 09:43:30 -07:00
huge-frame-unsupported.ll
…
i1-ext-fold.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
i1-to-double.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
i32-to-float.ll
…
i64_fp_round.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
i64_fp.ll
…
i64-to-float.ll
…
i128-and-beyond.ll
…
ia-mem-r0.ll
…
ia-neg-const.ll
…
iabs.ll
…
idiv_large.ll
[CodeGen] Always expand division larger than i128
2023-03-01 15:33:45 +01:00
ifcvt_cr_field.ll
…
ifcvt-diamond-ret.mir
…
ifcvt-forked-bug-2016-08-08.ll
[IR] Remove support for icmp and fcmp constant expressions (#93038)
2024-06-04 08:31:03 +02:00
ifcvt.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
ifcvt.mir
…
ifunc.ll
…
illegal-element-type.ll
…
in-asm-f64-reg.ll
…
inc-of-add.ll
[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)
2024-11-04 12:57:26 -05:00
indexed-load.ll
…
indirect-hidden.ll
…
indirectbr.ll
…
inline-asm-clobber-warning.ll
[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)
2024-11-04 12:57:26 -05:00
inline-asm-dollarpc.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-label.ll
…
inline-asm-multilevel-gep.ll
…
inline-asm-physical-fpr-spe.ll
PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs
2023-06-21 10:24:40 +00:00
inline-asm-physical-fpr.ll
…
inline-asm-s-modifier.ll
…
inline-asm-scalar-to-vector-error.ll
…
inline-asm-vsx-clobbers.ll
…
inlineasm-copy.ll
…
inlineasm-extendedmne.ll
…
inlineasm-i64-reg.ll
…
inlineasm-output-template.ll
…
inlineasm-vsx-reg.ll
…
instr-properties.ll
…
instruction-mix-remarks-BCTRL_LWZinto_toc.ll
…
int128_ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
int-fp-conv-0.ll
…
int-fp-conv-1.ll
…
intrinsic-trap.ll
[PowerPC] Make verifier happy when lowering llvm.trap (#77266)
2024-01-10 09:23:30 +08:00
inverted-bool-compares.ll
…
is_fpclass.ll
DAG: Check if is_fpclass is custom, instead of isLegalOrCustom (#105577)
2024-08-29 14:05:43 +04:00
isel-rc-nox0.ll
…
isel.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
ispositive.ll
…
issue55983.ll
[llvm] Remove explicit -opaque-pointers flag from tests (NFC)
2023-07-12 14:35:55 +02:00
isync.ll
…
itofp128.ll
…
jaggedstructs.ll
…
jump-table.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
jump-tables-collapse-rotate-remove-SrcMI.mir
[Test] Fix YAML mapping keys duplication. NFC.
2023-02-09 12:59:50 +03:00
jump-tables-collapse-rotate.ll
BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads
2023-10-24 20:27:39 -07:00
kernel-fp-round.ll
…
kill_flag_verification.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
knowCRBitSpill.ll
…
LargeAbsoluteAddr.ll
…
larger-than-red-zone.ll
…
lbz-from-ld-shift.ll
…
lbzux.ll
…
ld-bswap64-no-ldbrx.ll
…
ld-st-upd.ll
…
ldexp-libcall.ll
[SDAG] Honor signed arguments in floating point libcalls (#109134)
2024-09-25 11:09:50 +04:00
ldexp.ll
[SDAG] Honor signed arguments in floating point libcalls (#109134)
2024-09-25 11:09:50 +04:00
ldst-16-byte-asm-aix.mir
[PowerPC] Change registers used in test due to ABI breakage. NFC. (#70758)
2023-11-03 07:08:33 +08:00
ldst-16-byte-asm.mir
[PowerPC] Change registers used in test due to ABI breakage. NFC. (#70758)
2023-11-03 07:08:33 +08:00
ldst-16-byte.mir
[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)
2024-11-04 12:57:26 -05:00
ldst-align.ll
…
ldtoc-inv.ll
…
legalize-invert-br_cc.ll
…
legalize-vaarg.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
lha.ll
…
licm-remat.ll
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
2024-11-12 14:02:01 -05:00
licm-tocReg.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
lit.local.cfg
[PowerPC][test] Catch any exception when retrieving git revision (#92004)
2024-05-14 10:32:30 -04:00
livephysregs.mir
…
livevars-crash1.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
livevars-crash2.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
llc_default_cpu.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
llrint-conv.ll
…
llround-conv.ll
…
llvm.frexp.ll
IR: Add llvm.frexp intrinsic
2023-06-28 14:50:16 -04:00
load-and-splat.ll
[PowerPC] special case small int constant for custom scalar_to_vector (#109850)
2024-10-21 12:19:07 -04:00
load-constant-addr.ll
…
load-rightmost-vector-elt.ll
…
load-shift-combine.ll
…
load-shuffle-and-shuffle-store.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
load-two-flts.ll
…
load-v4i8-improved.ll
…
logic-ops-on-compares.ll
…
long-compare.ll
…
longcall.ll
[PowerPC] Bail out of FISel when lowering long calls
2023-02-16 16:15:32 -05:00
longdbl-truncate.ll
…
longdouble-pack.ll
…
loop-align.ll
…
loop-comment.ll
…
loop-data-prefetch-inner.ll
…
loop-data-prefetch.ll
…
loop-hoist-toc-save.ll
…
loop-instr-form-non-inc.ll
[PowerPC] Adjust tests after e351b9b66da088.
2023-05-12 20:20:13 +01:00
loop-instr-form-prepare.ll
[SCEV] Special case sext in isKnownNonZero (#77834)
2024-01-12 07:45:28 -08:00
loop-instr-prep-non-const-increasement.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
loop-p10-pair-prepare.ll
…
loop-prep-all.ll
…
lower-globaladdr32-aix-asm.ll
…
lower-globaladdr32-aix.ll
RegisterCoalescer: Fix name of pass
2023-06-21 10:30:43 -04:00
lower-globaladdr64-aix-asm.ll
…
lower-globaladdr64-aix.ll
RegisterCoalescer: Fix name of pass
2023-06-21 10:30:43 -04:00
lower-intrinsics-afn-mass_notail.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
lower-intrinsics-afn-mass.ll
…
lower-intrinsics-fast-mass_notail.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
lower-intrinsics-fast-mass.ll
…
lower-intrinsics-nofast-mass.ll
…
lower-massv-attr.ll
…
lower-massv.ll
…
lower-scalar-mass-afn.ll
…
lower-scalar-mass-fast.ll
…
lower-scalar-mass-nofast.ll
…
LQ-STQ-32bit-offset.ll
…
LQ-STQ.ll
…
lrint-conv.ll
…
lround-conv.ll
…
lsa.ll
…
lsr-ctrloop.ll
…
lsr-insns-cost.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
lsr-postinc-pos.ll
[SCEVExpander] Always use scevgep as name
2023-03-17 14:27:03 +01:00
lsr-profitable-chain.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
lxv-aligned-stack-slots.ll
…
lxvw4x-bug.ll
…
machine-backward-cp.mir
…
machine-combiner.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
machine-cse-rm-pre.mir
[CodeGen][NewPM] Port MachineCSE pass to new pass manager. (#106605)
2024-09-04 18:54:07 +05:30
machine-pre.ll
…
machinelicm-cse-dead-flag.mir
[NewPM][CodeGen] Port MachineLICM to NPM (#107376)
2024-09-20 11:34:18 +05:30
macro-fusion.ll
…
macro-fusion.mir
…
maddld.ll
…
mask64.ll
…
mature-mc-support.ll
…
mc-instrlat.ll
…
mcm-1.ll
…
mcm-2.ll
…
mcm-3.ll
…
mcm-4.ll
…
mcm-5.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
mcm-6.ll
…
mcm-7.ll
…
mcm-8.ll
…
mcm-9.ll
…
mcm-10.ll
…
mcm-11.ll
…
mcm-12.ll
…
mcm-13.ll
…
mcm-default.ll
…
mcm-obj-2.ll
…
mcm-obj.ll
…
mcount-insertion.ll
…
mcp-elim-eviction-chain.mir
[MachineCopyPropagation] Eliminate spillage copies that might be caused by eviction chain
2023-02-08 03:34:25 +00:00
MCSE-caller-preserved-reg.ll
…
mem_update.ll
…
mem-rr-addr-mode.ll
…
memcmp-mergeexpand.ll
[CodeGen] Port ExpandMemCmp to new pass manager (#74050)
2023-12-13 16:18:24 +08:00
memcmp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
memcmpIR.ll
[PowerPC] Convert more tests to opaque pointers (NFC)
2023-01-30 04:27:10 +03:00
memCmpUsedInZeroEqualityComparison.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
memcpy_dereferenceable.ll
…
memcpy-vec.ll
…
memset-nc-le.ll
…
memset-tail.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
merge_stores_dereferenceable.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
merge-private.ll
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
2024-11-12 14:02:01 -05:00
merge-st-chain-op.ll
…
mergeable-string-pool-exceptions.ll
[PPC] Remove missed cases of ppc-merge-string-pool (#117626)
2024-12-03 13:31:26 -05:00
mergeable-string-pool-large.ll
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
2024-11-12 14:02:01 -05:00
mergeable-string-pool-pr92991.ll
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
2024-11-12 14:02:01 -05:00
mergeable-string-pool-tls.ll
[PPC] Remove missed cases of ppc-merge-string-pool (#117626)
2024-12-03 13:31:26 -05:00
mergeable-string-pool.ll
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
2024-11-12 14:02:01 -05:00
MergeConsecutiveStores.ll
…
mflr-store.mir
[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)
2024-11-04 12:57:26 -05:00
mftb.ll
…
mi-peephole-splat.ll
…
mi-peephole.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
mi-peepholes-trap-opt.mir
…
mi-scheduling-lhs.ll
…
mi-simplify-code.mir
…
misched-inorder-latency.ll
…
misched.ll
…
mma-acc-copy-hints.ll
…
mma-acc-memops.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
mma-acc-spill.ll
[PowerPC] Add support for -mcpu=pwr11 / -mtune=pwr11 (#99511)
2024-07-23 09:49:41 -04:00
mma-integer-based-outer-product.ll
…
mma-intrinsics.ll
[SeperateConstOffsetFromGEP] Handle or disjoint flags (#76997)
2024-01-26 09:56:06 -06:00
mma-outer-product.ll
[CodeGen] Remove target SubRegLiveness flags (#95437)
2024-06-14 08:51:56 +01:00
mma-phi-accs.ll
…
mmaplus-acc-spill.ll
…
mmaplus-intrinsics.ll
[PowerPC][Future] Enable __builtin_mma_xxm[t|f]acc
2023-07-14 13:38:40 -05:00
MMO-flags-assertion.ll
…
more-dq-form-prepare.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
mtvsrc-mfvscr-PPCVSXSwapRemoval.ll
…
mtvsrdd.ll
…
mul-const-i64.ll
…
mul-const-vector.ll
[PowerPC] remove XXSWAPD after load from CP which is a splat value
2023-02-16 19:21:35 -05:00
mul-const.ll
…
mul-high.ll
…
mul-with-overflow.ll
…
mulhs.ll
…
mulld.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
mulli.ll
…
mult-alt-generic-powerpc64.ll
…
mult-alt-generic-powerpc.ll
…
multi-return.ll
…
naked-fn-with-frame-pointer.ll
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
named-reg-alloc-r0.ll
[PowerPC] Expand global named register support (#113482)
2024-10-24 10:05:18 -04:00
named-reg-alloc-r1-64.ll
Revert "[PowerPC] Expand global named register support" (#113457)
2024-10-23 09:36:28 -04:00
named-reg-alloc-r1.ll
Revert "[PowerPC] Expand global named register support" (#113457)
2024-10-23 09:36:28 -04:00
named-reg-alloc-r2-64.ll
[PowerPC] Expand global named register support (#113482)
2024-10-24 10:05:18 -04:00
named-reg-alloc-r2.ll
[PowerPC] Expand global named register support (#113482)
2024-10-24 10:05:18 -04:00
named-reg-alloc-r13-64.ll
Revert "[PowerPC] Expand global named register support" (#113457)
2024-10-23 09:36:28 -04:00
named-reg-alloc-r13.ll
Revert "[PowerPC] Expand global named register support" (#113457)
2024-10-23 09:36:28 -04:00
named-reg-alloc.ll
[PowerPC] Expand global named register support (#113482)
2024-10-24 10:05:18 -04:00
neg-abs.ll
…
neg.ll
…
negate-i1.ll
…
negative-integer-fp-libcall.ll
[SDAG] Honor signed arguments in floating point libcalls (#109134)
2024-09-25 11:09:50 +04:00
negctr.ll
…
no-ctr-loop-if-exit-in-nested-loop.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
no-dead-strip.ll
…
no-dup-of-bdnz.ll
…
no-dup-spill-fp.ll
…
no-duplicate.ll
…
no-ext-with-count-zeros.ll
…
no-extra-fp-conv-ldst.ll
…
no-misaligned-tocl.ll
[PowerPC] Do not convert lwz to lwa if the offset is not a multiple of 4
2023-01-31 09:54:29 -06:00
no-pref-jumps.ll
…
no-rlwimi-trivial-commute.mir
…
NoCRFieldRedefWhenSpillingCRBIT.mir
…
nofpexcept.ll
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
nomerge.ll
[NFC] Update CodeGen/*/nomerge.ll tests with utils/update_llc_test_checks.py.
2023-04-03 19:52:39 -04:00
non-debug-mi-search-frspxsrsp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
non-simple-args-intrin.ll
…
noPermuteFormasking.ll
…
noredzone.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
not-fixed-frame-object.ll
…
novrsave.ll
…
O0-pipeline.ll
[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)
2024-08-29 17:53:32 +01:00
O3-pipeline.ll
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
2024-11-12 14:02:01 -05:00
opt-builtins-ppc-xlcompat-cas.ll
…
opt-cmp-inst-cr0-live.ll
…
opt-cmp-rec-postra.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
opt-li-add-to-addi.ll
…
opt-sub-inst-cr0-live.mir
…
optcmp.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
optimize-andiso.ll
…
optimize-vector.ll
[PowerPC] Improve code gen for vector add
2023-07-13 15:21:49 -04:00
optnone-crbits-i1-ret.ll
…
or-addressing-mode.ll
…
ori_imm32.ll
…
ori_imm64.ll
…
out-of-range-dform.ll
…
overflow-intrinsic-optimizations.ll
…
p8-isel-sched.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
p8-scalar_vector_conversions.ll
[PowerPC] Fix vector_shuffle combines when inputs are scalar_to_vector of differing types. (#80784)
2024-11-11 10:53:51 -05:00
p8altivec-shuffles-pred.ll
[PowerPC] Regenerate p8altivec-shuffles-pred.ll with update_llc_test_checks script
2024-06-19 16:55:33 +01:00
p9_copy_fp.ll
…
p9-dform-load-alignment.ll
…
p9-vbpermd.ll
…
p9-vector-compares-and-counts.ll
…
p9-vector-sign-extend.ll
…
p9-vinsert-vextract.ll
…
p9-xxinsertw-xxextractuw.ll
…
p10-bit-manip-ops.ll
…
p10-bswap.ll
…
p10-check-features.ll
…
p10-fi-elim.ll
[PowerPC] Convert more tests to opaque pointers (NFC)
2023-01-30 04:27:10 +03:00
p10-handle-split-promote-vec.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
p10-p11-constants.ll
[PowerPC] Add support for -mcpu=pwr11 / -mtune=pwr11 (#99511)
2024-07-23 09:49:41 -04:00
p10-setbc-ri.ll
…
p10-setbc-rr.ll
…
p10-setbcr-ri.ll
…
p10-setbcr-rr.ll
…
p10-setboolean-ext-fp.ll
…
p10-setnbc-ri.ll
…
p10-setnbc-rr.ll
…
p10-setnbcr-ri.ll
…
p10-setnbcr-rr.ll
…
p10-spill-creq.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
p10-spill-crgt.ll
BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads
2023-10-24 20:27:39 -07:00
p10-spill-crlt.ll
LICM: hoist BO assoc for and, or, xor (#111146)
2024-10-04 19:13:51 +01:00
p10-spill-crun.ll
…
p10-splatImm32-undef.ll
[PowerPC] special case small int constant for custom scalar_to_vector (#109850)
2024-10-21 12:19:07 -04:00
p10-splatImm32.ll
…
p10-splatImm-CPload-pcrel.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
p10-splatImm.ll
…
p10-string-ops.ll
…
p10-vector-divide.ll
…
p10-vector-mask-ops.ll
…
p10-vector-modulo.ll
…
p10-vector-multiply.ll
…
p10-vector-rotate.ll
…
p10-vector-shift.ll
…
p10-vector-sign-extend.ll
…
p10-vsx-pcv.ll
…
P10-stack-alignment.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
paired-vector-intrinsics.ll
…
patchable-function-entry.ll
[PowerPC] Support -fpatchable-function-entry (#92997)
2024-07-22 08:51:51 +08:00
pcrel_ldst.ll
…
pcrel-block-address.ll
…
pcrel-byte-loads.ll
…
pcrel-call-linkage-leaf.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
pcrel-call-linkage-simple.ll
…
pcrel-call-linkage-with-calls.ll
…
pcrel-got-indirect.ll
…
pcrel-indirect-call.ll
…
pcrel-jump-table.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
pcrel-linkeropt-option.ll
…
pcrel-linkeropt.ll
…
pcrel-local-caller-toc.ll
…
pcrel-relocation-plus-offset.ll
…
pcrel-tail-calls.ll
…
pcrel-tls_get_addr_clobbers.ll
[PowerPC] Add a set of extended mnemonics that are missing from Power 10. (#73003)
2023-12-07 13:40:00 -05:00
pcrel-tls-general-dynamic.ll
…
pcrel-tls-initial-exec.ll
…
pcrel-tls-local-dynamic.ll
[PowerPC] Add a set of extended mnemonics that are missing from Power 10. (#73003)
2023-12-07 13:40:00 -05:00
pcrel-tls-local-exec.ll
[PowerPC] Add a set of extended mnemonics that are missing from Power 10. (#73003)
2023-12-07 13:40:00 -05:00
pcrel.ll
…
peephole-align.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
peephole-cmp-eq.mir
…
peephole-combineRLWINM-liveness.mir
[PowerPC] Ensure MI peephole knows about instr modified by combineRLWINM() (#97134)
2024-07-16 11:46:37 -04:00
peephole-counter-perOp.mir
Fix failure after d46e37348ec3f8054b10bcbbe7c11149d7f61031
2024-05-28 15:23:13 +02:00
peephole-counter-XToI.mir
Fix failure after d46e37348ec3f8054b10bcbbe7c11149d7f61031
2024-05-28 15:23:13 +02:00
peephole-miscompile-extswsli.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
peephole-mma-phi-liveness.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
peephole-phi-acc.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
peephole-replaceInstr-after-eliminate-extsw.mir
[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)
2024-11-04 12:57:26 -05:00
peephole-subreg-def.mir
…
perfect-shuffle.ll
…
pgo-ref-directive.ll
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
2024-02-06 09:08:18 -06:00
phi-eliminate.mir
[CodeGen][NewPM] Port phi-node-elimination to new pass manager (#98867)
2024-07-17 11:26:56 +08:00
pie.ll
…
pip-inner.ll
…
popcnt-zext.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
popcnt.ll
…
popcount.ll
…
post-ra-ec.ll
…
pow_massv_075_025exp.ll
…
pow-025-075-intrinsic-scalar-mass-afn.ll
…
pow-025-075-intrinsic-scalar-mass-fast.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
pow-025-075-nointrinsic-scalar-mass-fast.ll
…
pow.75.ll
…
power9-moves-and-splats.ll
…
powf_massv_075_025exp.ll
…
ppc32-align-long-double-sf.ll
…
ppc32-constant-BE-ppcf128.ll
…
ppc32-cyclecounter.ll
…
ppc32-i1-stack-arguments-abi-bug.ll
…
ppc32-i1-vaarg.ll
…
ppc32-i64-to-float-conv.ll
…
ppc32-lshrti3.ll
…
ppc32-nest.ll
…
ppc32-pic-large.ll
[MC,ELF] .section: unconditionally print section flag 'G' after 'o'
2024-01-09 10:48:23 -08:00
ppc32-pic.ll
…
ppc32-secure-plt-tls2.ll
…
ppc32-secure-plt-tls.ll
…
ppc32-selectcc-i64.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
ppc32-skip-regs.ll
…
ppc32-vacopy.ll
…
ppc64-32bit-addic.ll
…
ppc64-abi-extend.ll
…
ppc64-acc-regalloc-bugfix.ll
…
ppc64-acc-regalloc.ll
[CodeGen] Remove target SubRegLiveness flags (#95437)
2024-06-14 08:51:56 +01:00
ppc64-align-long-double.ll
…
ppc64-altivec-abi.ll
…
ppc64-anyregcc-crash.ll
RegAlloc: Use DiagnosticInfo to report register allocation failures (#119492)
2024-12-16 10:49:08 +09:00
ppc64-anyregcc.ll
[PPC] Add DwarfRegAlias for VSRPair (#95837)
2024-06-20 11:30:58 -04:00
ppc64-blnop.ll
…
ppc64-byval-align.ll
…
ppc64-byval-larger-struct.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc64-byval-multi-store.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc64-calls.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
ppc64-crash.ll
…
ppc64-crsave.mir
[PowerPC] Spill non-volatile registers required for traceback table (#71115)
2024-05-07 16:23:37 -04:00
ppc64-cyclecounter.ll
…
ppc64-elf-abi.ll
[PowerPC] Correctly use ELFv2 ABI on all OS's that use the ELFv2 ABI
2023-02-20 18:11:24 -05:00
ppc64-fastcc-fast-isel.ll
…
ppc64-fastcc.ll
…
ppc64-func-desc-hoist.ll
…
ppc64-gep-opt.ll
[PowerPC] Convert more tests to opaque pointers (NFC)
2023-01-30 04:27:10 +03:00
ppc64-get-cache-line-size.ll
…
ppc64-i128-abi.ll
…
ppc64-icbt-pwr7.ll
[SelectionDAG][RISCV][PowerPC][X86] Use TargetConstant for immediates for ISD::PREFETCH. (#66601)
2023-09-18 08:58:50 -07:00
ppc64-icbt-pwr8.ll
…
ppc64-inlineasm-clobber.ll
…
ppc64-linux-func-size.ll
…
ppc64-nest.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
ppc64-nonfunc-calls.ll
[AIX][TLS] Produce a faster local-exec access sequence with -maix-small-local-exec-tls (And optimize when load/store offsets are 0)
2023-09-07 20:05:29 -05:00
ppc64-notoc-rm-relocation.ll
…
ppc64-P9-mod.ll
…
ppc64-P9-setb.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc64-P9-vabsd.ll
[DAG] Add support for neg(abd(x,y)) patterns.
2024-09-06 13:16:09 +01:00
ppc64-patchpoint.ll
…
ppc64-pre-inc-no-extra-phi.ll
…
ppc64-prefetch.ll
…
ppc64-r2-alloc.ll
…
ppc64-rop-protection-aix.ll
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
ppc64-rop-protection.ll
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
ppc64-sibcall-shrinkwrap.ll
[ShrinkWrap] Use underlying object to rule out stack access.
2023-05-03 09:28:07 +01:00
ppc64-sibcall.ll
…
ppc64-smallarg.ll
…
ppc64-stackmap-args.ll
[CodeGen] @llvm.experimental.stackmap make operands immediate (#117932)
2024-12-11 17:41:19 +08:00
ppc64-stackmap-nops.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
ppc64-stackmap.ll
Obsolete WebKit Calling Convention (#71567)
2023-11-09 09:08:41 -08:00
ppc64-toc.ll
…
ppc64-vaarg-int.ll
…
ppc64-varargs.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
ppc64-xxsplti32dx-pattern-check.ll
…
ppc64-zext.ll
…
ppc64le-aggregates.ll
[test] Remove redundant -march= when target triple is specified in IR
2024-12-15 12:42:17 -08:00
ppc64le-calls.ll
…
ppc64le-crsave.ll
…
ppc64le-localentry-large.ll
…
ppc64le-localentry.ll
…
ppc64le-smallarg.ll
…
ppc440-fp-basic.ll
…
ppc440-msync.ll
…
ppc_fp128-bcwriter.ll
…
ppc-32bit-build-vector.ll
[DAG] SimplifyMultipleUseDemandedBits - bypass ADD nodes if either operand is zero (#112588)
2024-11-05 17:20:41 +00:00
ppc-32bit-shift.ll
…
ppc-clear-before-return.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc-crbits-onoff.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
ppc-ctr-dead-code.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc-disable-non-volatile-cr.ll
…
ppc-empty-fs.ll
…
ppc-float-spill.ll
[PowerPC] Fix float materialization patterns.
2023-02-13 10:18:53 -05:00
ppc-label2.ll
…
ppc-label.ll
…
ppc-partword-atomic.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
ppc-passname-assert.ll
…
ppc-passname.ll
…
ppc-prologue.ll
…
ppc-redzone-alignment-bug.ll
…
ppc-rotate-clear.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc-shrink-wrapping.ll
[PowerPC] Spill non-volatile registers required for traceback table (#71115)
2024-05-07 16:23:37 -04:00
ppc-shufflevector-combine.ll
…
ppc-TOC-stats.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
ppc-vaarg-agg.ll
…
ppcf128-1-opt.ll
…
ppcf128-1.ll
…
ppcf128-2.ll
…
ppcf128-3.ll
…
ppcf128-4.ll
…
ppcf128-constrained-fp-intrinsics.ll
Emit constrained atan2 intrinsic for clang builtin (#113636)
2024-11-12 13:34:29 -08:00
ppcf128-endian.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
ppcf128-freeze.mir
Fix MIR failure after b922a362
2023-09-08 16:33:45 +08:00
ppcf128sf.ll
…
ppcsoftops.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
pr3711_widen_bit.ll
[IR] Remove support for icmp and fcmp constant expressions (#93038)
2024-06-04 08:31:03 +02:00
pr12757.ll
…
pr13641.ll
…
pr13891.ll
…
pr15031.ll
…
pr15359.ll
[DataLayout] Refactor the rest of parseSpecification (#104545)
2024-08-20 11:25:49 +03:00
pr15630.ll
…
pr15632.ll
…
pr16556-2.ll
[DataLayout] Refactor the rest of parseSpecification (#104545)
2024-08-20 11:25:49 +03:00
pr16556.ll
[DataLayout] Refactor the rest of parseSpecification (#104545)
2024-08-20 11:25:49 +03:00
pr16573.ll
…
pr17168.ll
…
pr17354.ll
…
pr18663-2.ll
…
pr18663.ll
…
pr20442.ll
…
pr22711.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
pr24216.ll
…
pr24546.ll
…
pr24636.ll
[IR] Remove support for icmp and fcmp constant expressions (#93038)
2024-06-04 08:31:03 +02:00
pr25080.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr25157-peephole.ll
…
pr25157.ll
…
pr26180.ll
…
pr26193.ll
…
pr26356.ll
…
pr26378.ll
…
pr26381.ll
…
pr26617.ll
…
pr26690.ll
…
pr27078.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr27350.ll
…
pr28130.ll
…
pr28630.ll
…
pr30451.ll
…
pr30640.ll
…
pr30663.ll
…
pr30715.ll
…
pr31144.ll
…
pr32063.ll
…
pr32140.ll
…
pr33093.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr33547.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr35402.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr35688.ll
…
pr36068.ll
…
pr36292.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr38087.ll
[DAG] SimplifyDemandedVectorElts - add handling for INT<->FP conversions (#117884)
2024-12-04 07:37:01 +00:00
pr38899-split-register-at-spill.mir
…
pr39478.ll
…
pr39815.ll
…
pr40922.ll
[NFC] Autogenerate CodeGen/PowerPC/pr40922.ll
2023-06-25 21:05:06 +00:00
pr41088.ll
…
pr41177.ll
…
pr42492.ll
…
pr43527.ll
…
pr43976.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
pr44183.ll
[DAG] Replace getValid*ShiftAmountConstant helpers with getValid*ShiftAmount helpers to support KnownBits analysis (#93182)
2024-06-01 16:48:26 +01:00
pr44239.ll
…
pr45186.ll
…
pr45297.ll
…
pr45301.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
pr45432.ll
…
pr45448.ll
Reapply [InstCombine] Simplify and/or of icmp eq with op replacement (#70335)
2023-11-03 10:16:15 +01:00
pr45628.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr45709.ll
[DAG] FoldSetCC - add missing icmp(X,undef) -> isTrueWhenEqual case (REAPPLIED)
2023-09-13 12:33:39 +01:00
pr46759.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr46923.ll
[IR] Remove support for icmp and fcmp constant expressions (#93038)
2024-06-04 08:31:03 +02:00
pr47155-47156.ll
[PowerPC] make LR/LR8 CTR/CTR8 aliased (#76926)
2024-01-08 09:37:40 +08:00
pr47373.ll
[PowerPC] Correctly use ELFv2 ABI on all OS's that use the ELFv2 ABI
2023-02-20 18:11:24 -05:00
pr47660.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
pr47707.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr47830.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr47891.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
pr47916.ll
…
pr48388.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr48519.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr48527.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr49092.ll
…
pr49509.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
pr52894-32bit.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr52894.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr55463.ll
PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs
2023-06-21 10:24:40 +00:00
pr55857.ll
…
pr55911.ll
…
pr56469.ll
…
pr59074.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
pr61315.ll
[PowerPC] Update pr61315.ll to address D146632 failure
2023-04-05 21:24:59 -05:00
pr61882.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
pr62372.ll
[PowerPC] option -msoft-float should not block the PC-relative address instruction (#92543)
2024-05-29 10:53:00 -04:00
pr70208.ll
[DAG] WidenVectorOperand - add basic handling for *_EXTEND_VECTOR_INREG nodes
2023-10-25 16:52:15 +01:00
pr74951.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
pr77748.ll
[PowerPC] Fix shuffle combine with undef elements (#77787)
2024-01-15 10:12:33 +01:00
pr85066.ll
[DAGCombine] Fix type mismatch in (shl X, cttz(Y)) -> (mul (Y & -Y), X) (#94008)
2024-06-01 19:04:55 +08:00
pr92233.ll
[PowerPC]perform bitcast lowering only at 64 bit
2024-05-20 03:17:21 -04:00
pr116071.ll
recalculate the live interval of the defined register of xvmaddmdp in the VSX FMA mutation pass. (#116071)
2024-12-10 11:21:15 -05:00
pr118695.ll
[PowerPC][Backend] using signed extend value instead of zero extend value for isIntS34Immediate() (#118703)
2024-12-05 09:08:18 -05:00
PR3488.ll
…
PR33636.ll
…
PR33671.ll
…
PR35812-neg-cmpxchg.ll
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
2024-11-12 14:02:01 -05:00
pre-inc-disable.ll
[PowerPC] Improve pwr7 codegen for v4i8 load (#104507)
2024-09-04 12:55:27 -04:00
prefer-dqform.ll
[PowerPC] Convert more tests to opaque pointers (NFC)
2023-01-30 05:19:24 +03:00
preinc-ld-sel-crash.ll
…
preincprep-i64-check.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
preincprep-invoke.ll
…
preincprep-nontrans-crash.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
private.ll
…
prolog_vec_spills.mir
…
pwr3-6x.ll
…
pwr7-gt-nop.ll
…
pzero-fp-xored.ll
…
quadint-return.ll
…
r31.ll
…
read-set-flm.ll
[PowerPC] Implement builtin for mffsl
2023-09-05 11:22:09 +08:00
recipest.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
reduce_cr.ll
BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads
2023-10-24 20:27:39 -07:00
reduce_scalarization02.ll
…
reduce_scalarization.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
redundant-copy-after-tail-dup.ll
…
reg_copy.mir
…
reg-coalesce-simple.ll
…
reg-names.ll
…
reg-scavenging.ll
…
regalloc-fast-debug-spill.ll
…
register-pressure-reduction.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
register-pressure.ll
[PowerPC/SPE] powerpcspe load and store instruction has
2023-07-23 13:24:35 +05:30
reloc-align.ll
…
remap-crash.ll
…
remat-imm.ll
…
rematerializable-instruction-machine-licm.ll
[Tests] Add disjoint flag to some tests (NFC)
2023-12-05 14:09:36 +01:00
remove-copy-crunsetcrbit.mir
[PowerPC][NFC] Rename ADDItocL to match the 64-bit naming convention (#85099)
2024-03-13 11:57:07 -04:00
remove-implicit-use.mir
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
remove-redundant-li-implicit-reg.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
remove-redundant-li-skip-imp-kill.mir
…
remove-redundant-load-imm.ll
…
remove-redundant-load-imm.mir
…
remove-redundant-moves.ll
…
remove-redundant-toc-saves.ll
…
remove-self-copies.mir
…
repeated-fp-divisors.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
resolvefi-basereg.ll
…
resolvefi-disp.ll
…
respect-rounding-mode.ll
…
restore-r30.ll
…
retaddr2.ll
…
retaddr_multi_levels.ll
…
retaddr.ll
…
return-val-i128.ll
…
rldimi.ll
[PowerPC] Implement 32-bit expansion for rldimi (#86783)
2024-04-09 16:43:49 +08:00
rlwimi2.ll
…
rlwimi3.ll
…
rlwimi-and-or-bits.ll
…
rlwimi-and.ll
…
rlwimi-commute.ll
…
rlwimi-dyn-and.ll
…
rlwimi-keep-rsh.ll
…
rlwimi.ll
[PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins (#85040)
2024-03-18 14:17:16 +08:00
rlwinm2.ll
…
rlwinm_rldicl_to_andi.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
rlwinm-zero-ext.ll
…
rlwinm.ll
[PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins (#85040)
2024-03-18 14:17:16 +08:00
rm-zext.ll
…
rotl-2.ll
…
rotl-64.ll
…
rotl-rotr-crash.ll
…
rotl.ll
…
rounding-ops.ll
…
rounding-rm-flag.ll
…
rs-undef-use.ll
…
s000-alias-misched.ll
…
saddo-ssubo.ll
[PPC] Custom lower ssubo for i64 (#118711)
2024-12-05 17:22:44 -05:00
sat-add.ll
[PPC] Add custom lowering for uaddo (#110137)
2024-10-21 11:13:16 -04:00
sat-register-clobber.ll
…
saturating-intrinsics.ll
…
save-bp.ll
…
save-cr-ppc32svr4.ll
…
save-crbp-ppc32svr4.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
save-reg-params.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
scalar_cmp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar_vector_test_1.ll
…
scalar_vector_test_2.ll
…
scalar_vector_test_3.ll
…
scalar_vector_test_4.ll
[PowerPC] Improve pwr7 codegen for v4i8 load (#104507)
2024-09-04 12:55:27 -04:00
scalar_vector_test_5.ll
[DAG] Extend extract_element(bitcast(scalar_to_vector(X))) -> trunc(srl(X,C)) (#117900)
2024-11-29 17:24:38 +00:00
scalar-double-ldst.ll
[PowerPC] Update chain uses when emitting lxsizx (#84892)
2024-03-18 22:31:05 +08:00
scalar-equal.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-float-ldst.ll
[PowerPC] Update chain uses when emitting lxsizx (#84892)
2024-03-18 22:31:05 +08:00
scalar-i8-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-i16-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-i32-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-i64-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-min-max-p10.ll
[PowerPC] Forbid f128 SELECT_CC optimized into fsel (#71497)
2023-11-15 12:20:06 +08:00
scalar-min-max.ll
…
scalar-rounding-ops.ll
[PowerPC] Add missing patterns for lround when i32 is returned. (#111863)
2024-10-16 10:25:09 -04:00
scalars-in-altivec-regs.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scavenging.mir
…
sched-addi.ll
[SeperateConstOffsetFromGEP] Handle or disjoint flags (#76997)
2024-01-26 09:56:06 -06:00
schedule-addi-load.mir
Fix MIR failure after b922a362
2023-09-08 16:33:45 +08:00
scheduling-mem-dependency.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scmp.ll
[SelectionDAG] Expand [US]CMP using arithmetic on boolean values instead of selects (#98774)
2024-07-16 20:56:18 +01:00
sdag-ppcf128.ll
…
sdiv-pow2.ll
…
sections.ll
…
select_const.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
select_lt0.ll
…
select-addrRegRegOnly.ll
…
select-cc-no-isel.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
select-cc.ll
…
select-constant-xor.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
select-i1-vs-i1.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
select-to-branch.mir
…
select.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
selectiondag-extload-computeknownbits.ll
…
selectiondag-sextload.ll
…
set0-v8i16.ll
…
setcc_no_zext.ll
…
setcc-logic.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
setcc-sub-flag.ll
…
setcc-to-sub.ll
Pre-commit some PowerPC test cases
2023-09-28 15:51:14 +08:00
setcc-vector.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
setcclike-or-comb.ll
…
setcr_bc2.mir
…
setcr_bc3.mir
…
setcr_bc.mir
…
seteq-0.ll
…
setrnd.ll
…
sext_elimination.mir
Promote 32bit pseudo instr that infer extsw removal to 64bit in PPCMIPeephole (#85451)
2024-10-31 15:49:36 -04:00
sext-vector-inreg.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
sh-overflow.mir
…
shift128.ll
…
shift_mask.ll
…
shift-cmp.ll
…
shl_elim.ll
…
shl_sext.ll
…
shrink-wrap.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
shrink-wrap.mir
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
sign_ext_inreg1.ll
…
sign-ext-atomics.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
signbit-shift.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
simplifyConstCmpToISEL.ll
…
simplifysetcc_narrow_load.ll
[SelectionDAG] Fix and improve TargetLowering::SimplifySetCC (#87646)
2024-04-12 16:18:12 +02:00
sink-down-more-instructions-1.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
sink-down-more-instructions-regpressure-high.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
sink-side-effect.ll
[CGP] Remove dead PHI nodes before elimination of mostly empty blocks
2023-08-29 04:35:06 +00:00
sj-ctr-loop.ll
…
sjlj_no0x.ll
…
sjlj.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
small-arguments.ll
…
sms-cpy-1.ll
Ignore load/store until stack address computation
2023-06-26 13:50:36 -07:00
sms-grp-order.ll
…
sms-iterator.ll
[CGP] Remove dead PHI nodes before elimination of mostly empty blocks
2023-08-29 04:35:06 +00:00
sms-large-stages.mir
…
sms-phi-1.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
sms-phi-2.ll
…
sms-phi-3.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
sms-phi-5.ll
[InstSimplify] Fix incorrect poison propagation when folding phi (#96631)
2024-11-07 14:09:45 +01:00
sms-phi.ll
…
sms-recmii.ll
[MachinePipeliner] Make Recurrence MII More Accurate (#105475)
2024-09-03 16:15:17 +09:00
sms-regpress.mir
Reapply "[CodeGen] Fix register pressure computation in MachinePipeli… (#87312)
2024-04-03 09:28:09 +09:00
sms-remark.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
sms-simple.ll
…
sms-store-dependence.ll
[MachinePipeliner] Fix store-store dependences (#72575)
2023-12-11 21:10:34 -06:00
smulfixsat.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
spe-fastmath.ll
…
spe-hwdouble.ll
…
spe.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
spill_p9_setb.ll
…
spill-nor0.ll
…
spill-nor0.mir
[NewPM][CodeGen] Port regallocfast to new pass manager (#94426)
2024-06-07 12:22:42 +08:00
spill-vec-pair.ll
…
splat-bug.ll
…
splat-larger-types-as-v16i8.ll
…
split-index-tc.ll
…
splitstore-check-volatile.ll
…
srem-lkk.ll
…
srem-seteq-illegal-types.ll
[DAG] visitAND - Fold (and (srl X, C), 1) -> (srl X, BW-1) for signbit extraction (#114992)
2024-11-05 14:42:15 +00:00
srem-vector-lkk.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
srl-mask.ll
…
ssubo-32.ll
[PowerPC] Add custom lowering for ssubo (#111748) (#115875)
2024-11-28 13:55:53 -05:00
stack_pointer_vec_spills.mir
…
stack-clash-dynamic-alloca.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
stack-clash-prologue-nounwind.ll
…
stack-clash-prologue.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
stack-coloring-vararg.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
stack-guard-global.ll
Fixed test case error which caused the default cpu is changed from generic to ppc64 for triple powerpc64 (#114828)
2024-11-04 11:37:35 -05:00
stack-guard-oob.ll
[IR] Make stack protector symbol dso_local according to -f[no-]direct-access-external-data
2023-05-23 09:49:57 -07:00
stack-guard-reassign.ll
…
stack-guard-tls.ll
Fixed test case error which caused the default cpu is changed from generic to ppc64 for triple powerpc64 (#114828)
2024-11-04 11:37:35 -05:00
stack-no-redzone.ll
…
stack-protector.ll
…
stack-realign.ll
…
stack-restore-with-setjmp.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
stackmap-frame-setup.ll
…
stacksize.ll
…
std-unal-fi.ll
…
stdux-constuse.ll
…
stfiwx-2.ll
…
stfiwx.ll
…
store_fptoi.ll
Reland "[PowerPC] Simplify fp-to-int store optimization"
2023-06-05 13:53:08 +08:00
store-combine.ll
…
store-constant.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
store-forward-be32.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
store-forward-be64.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
store-load-fwd.ll
…
store-rightmost-vector-elt.ll
…
store-update.ll
…
structsinmem.ll
…
structsinregs.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
stubs.ll
…
stwu8.ll
…
stwu-gta.ll
…
stwu-sched.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
stwux.ll
…
sub-bv-types.ll
…
sub-of-not.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
subc.ll
…
subreg-coalescer.mir
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
subreg-killed.mir
[CodeGen] Remove target SubRegLiveness flags (#95437)
2024-06-14 08:51:56 +01:00
subreg-lanemasks.mir
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
subreg-postra-2.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
subreg-postra.ll
[PowerPC] Retire PPCExpandISel pass (#84289)
2024-08-27 09:43:52 +08:00
subtract_from_imm.ll
…
svr4-redzone.ll
…
swap-reduction.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
swaps-le-1.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
swaps-le-2.ll
…
swaps-le-3.ll
…
swaps-le-4.ll
…
swaps-le-5.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
swaps-le-6.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
swaps-le-7.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
swaps-le-8.ll
…
tail-dup-analyzable-fallthrough.ll
…
tail-dup-branch-to-fallthrough.ll
…
tail-dup-break-cfg.ll
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
tail-dup-layout.ll
BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads
2023-10-24 20:27:39 -07:00
tailcall1-64.ll
…
tailcall1.ll
…
tailcall-speculatable-callee.ll
…
tailcall-string-rvo.ll
…
tailcallpic1.ll
…
test_call_aix.ll
…
test_func_desc.ll
[AIX] In assembly file, create a dummy text renamed to an empty string (#73052)
2023-12-04 17:35:47 -06:00
test-and-cmp-folding.ll
…
test-vector-insert.ll
[PowerPC] Improve pwr7 codegen for v4i8 load (#104507)
2024-09-04 12:55:27 -04:00
testBitReverse.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesi32gtu.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesi32leu.ll
…
testComparesi32ltu.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesieqsc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesieqsi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesieqsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesieqss.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiequc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiequi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiequll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiequs.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigesc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigesi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigess.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigeuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigeui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigeull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigeus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtsc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtsi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtss.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesilesc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesilesi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesilesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiless.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesileuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesileui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesileull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesileus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltsc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltsi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltss.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesinesc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesinesi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesinesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiness.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesineuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesineui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesineull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesineus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslleqsc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslleqsi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslleqsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslleqss.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllequc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllequi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllequll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllequs.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgesc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgesi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgess.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgeuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgeui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgeull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgeus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgtsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgtuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgtui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgtus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslllesc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslllesi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslllesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllless.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllleuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllleui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllleull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllleus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllltsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllltuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllltui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllltus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllnesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllneull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
thread-pointer.ll
…
tls_get_addr_clobbers.ll
…
tls_get_addr_fence1.mir
…
tls_get_addr_fence2.mir
…
tls_get_addr_stackframe.ll
…
tls-crash.mir
[PowerPC] redesign the target flags (#69695)
2023-12-07 12:47:25 +08:00
tls-cse.ll
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
tls-debug-aix.ll
…
tls-pic.ll
…
tls-pie-xform.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
tls-store2.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
tls.ll
…
toc-data-common.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
toc-data-const.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
toc-data-large-array2.ll
[AIX][TOC] Add -mtocdata/-mno-tocdata options on AIX (#67999)
2024-03-13 10:26:31 -04:00
toc-data-large-array.ll
[AIX][TOC] Add -mtocdata/-mno-tocdata options on AIX (#67999)
2024-03-13 10:26:31 -04:00
toc-data-no-data-sections.ll
[PowerPC] Fix assembler error with toc-data and data-sections (#91976)
2024-05-22 14:07:51 -04:00
toc-data-struct-array.ll
[AIX][TOC] Add -mtocdata/-mno-tocdata options on AIX (#67999)
2024-03-13 10:26:31 -04:00
toc-data.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
toc-float.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
toc-load-sched-bug.ll
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
2024-11-12 14:02:01 -05:00
tocdata-firm-alignment.ll
[PowerPC] Alignment of toc-data symbol should not be increased during optimizations (#94593)
2024-06-18 09:58:37 +08:00
tocdata-non-zero-addend.mir
[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)
2024-11-04 12:57:26 -05:00
tocSaveInPrologue.ll
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
topdepthreduce-postra.mir
…
trampoline.ll
…
trunc-srl-load.ll
…
two-address-crash.mir
[CodeGen][NewPM] Port phi-node-elimination to new pass manager (#98867)
2024-07-17 11:26:56 +08:00
uaddo-32.ll
[PPC] Add custom lowering for uaddo (#110137)
2024-10-21 11:13:16 -04:00
uaddo-64.ll
Fixed test case error which caused the default cpu is changed from generic to ppc64 for triple powerpc64 (#114828)
2024-11-04 11:37:35 -05:00
ucmp.ll
[SelectionDAG] Expand [US]CMP using arithmetic on boolean values instead of selects (#98774)
2024-07-16 20:56:18 +01:00
uint-to-fp-v4i32.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
uint-to-ppcfp128-crash.ll
…
umulfixsat.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
umulo-128-legalisation-lowering.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
unal4-std.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
unal-altivec2.ll
…
unal-altivec-wint.ll
…
unal-altivec.ll
…
unal-vec-ldst.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
unal-vec-negarith.ll
…
unaligned-addressing-mode.ll
…
unaligned-dqform-ld.ll
…
unaligned-floats.ll
…
unaligned.ll
…
unreachable-mbb-jtreference-elimination.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
unsafe-math.ll
…
unwind-dw2-g.ll
…
unwind-dw2.ll
…
urem-lkk.ll
…
urem-seteq-illegal-types.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
urem-vector-lkk.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
use-cr-result-of-dom-icmp-st.ll
…
uwtables.ll
…
v2i64_scalar_to_vector_shuffle.ll
[PowerPC] Fix vector_shuffle combines when inputs are scalar_to_vector of differing types. (#80784)
2024-11-11 10:53:51 -05:00
v4i32_scalar_to_vector_shuffle.ll
[PowerPC] Fix vector_shuffle combines when inputs are scalar_to_vector of differing types. (#80784)
2024-11-11 10:53:51 -05:00
v8i16_scalar_to_vector_shuffle.ll
[PowerPC] Fix vector_shuffle combines when inputs are scalar_to_vector of differing types. (#80784)
2024-11-11 10:53:51 -05:00
v16i8_scalar_to_vector_shuffle.ll
[PowerPC] Fix vector_shuffle combines when inputs are scalar_to_vector of differing types. (#80784)
2024-11-11 10:53:51 -05:00
vaddsplat.ll
…
varargs-struct-float.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
varargs.ll
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
2024-03-01 08:03:06 +08:00
variable_elem_vec_extracts.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
vavg.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vcmp-fold.ll
…
vcmp-setbc-quad.ll
[PowerPC] Use setbc for values from vector compare conditions (#114858)
2024-11-27 12:47:10 -05:00
vcmp-setbc.ll
[PowerPC] Use setbc for values from vector compare conditions (#114858)
2024-11-27 12:47:10 -05:00
vec_abs.ll
[LegalizeVectorOps] Enable ExpandFABS/COPYSIGN to use integer ops for fixed vectors in some cases. (#109232)
2024-09-30 11:44:49 -07:00
vec_absd.ll
…
vec_add_sub_doubleword.ll
…
vec_add_sub_quadword.ll
…
vec_auto_constant.ll
…
vec_br_cmp.ll
…
vec_buildvector_loadstore.ll
…
vec_call.ll
…
vec_clz.ll
…
vec_cmp.ll
…
vec_cmpd_p7.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vec_cmpd.ll
…
vec_cmpq.ll
…
vec_constants.ll
…
vec_conv_fp32_to_i8_elts.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vec_conv_fp32_to_i16_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_fp32_to_i64_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_fp64_to_i8_elts.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vec_conv_fp64_to_i16_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_fp64_to_i32_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_fp_to_i_4byte_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_fp_to_i_8byte_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_i8_to_fp32_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_i8_to_fp64_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_i16_to_fp32_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_i16_to_fp64_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_i32_to_fp64_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_i64_to_fp32_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_i_to_fp_4byte_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv_i_to_fp_8byte_elts.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec_conv.ll
…
vec_extload.ll
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vec_extract_p9_2.ll
…
vec_extract_p9.ll
…
vec_fmuladd.ll
…
vec_fneg.ll
[LegalizeVectorOps][PowerPC] Use xor to expand fneg. (#106595)
2024-08-29 15:00:23 -07:00
vec_insert_elt.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
vec_insert.ll
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vec_int_ext.ll
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vec_int_to_double_shuffle.ll
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vec_mergeow.ll
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vec_minmax.ll
…
vec_misaligned.ll
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vec_mul_even_odd.ll
…
vec_mul.ll
…
vec_perf_shuffle.ll
…
vec_popcnt.ll
…
vec_revb.ll
…
vec_rotate_shift.ll
…
vec_rounding.ll
…
vec_select.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_shift.ll
…
vec_shuffle_le.ll
…
vec_shuffle_p8vector_le.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_shuffle_p8vector.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vec_shuffle.ll
[InstCombine] Check for poison instead of undef in single shuffle fold
2024-05-21 16:03:20 +02:00
vec_sldwi.ll
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vec_splat_constant.ll
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vec_splat.ll
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vec_sqrt.ll
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vec_urem_const.ll
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vec_veqv_vnand_vorc.ll
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vec_vrsave.ll
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vec_xxpermdi.ll
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vec_zero.ll
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vec-abi-align.ll
…
vec-asm-disabled.ll
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vec-bswap.ll
…
vec-extract-itofp.ll
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vec-icmpeq-v2i64-p7.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vec-itofp.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
vec-min-max.ll
[PowerPC] vec-min-max.ll - regenerate with common check prefixes to reduce duplication. NFC.
2024-10-08 17:36:35 +01:00
vec-promote.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec-select.ll
…
vec-trunc2.ll
[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
2024-11-04 09:40:54 -05:00
vec-trunc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec-zext-abdu.ll
[DAG] Add legalization handling for ABDS/ABDU (#92576) (REAPPLIED)
2024-08-08 11:39:05 +01:00
vector-constrained-fp-intrinsics.ll
Emit constrained atan2 intrinsic for clang builtin (#113636)
2024-11-12 13:34:29 -08:00
vector-copysign.ll
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vector-extend-sign.ll
[PowerPC] remove XXSWAPD after load from CP which is a splat value
2023-02-16 19:21:35 -05:00
vector-identity-shuffle.ll
…
vector-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vector-llrint.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
vector-lrint.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
vector-merge-store-fp-constants.ll
…
vector-popcnt-128-ult-ugt.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vector-reduce-add.ll
[PowerPC] Update InputOps of Power10 SchedModel
2023-07-07 22:46:22 +08:00
vector-reduce-and.ll
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vector-reduce-fadd.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
vector-reduce-fmax.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
vector-reduce-fmin.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
vector-reduce-fmul.ll
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
2024-07-29 11:17:04 -04:00
vector-reduce-mul.ll
…
vector-reduce-or.ll
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vector-reduce-smax.ll
…
vector-reduce-smin.ll
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vector-reduce-umax.ll
…
vector-reduce-umin.ll
…
vector-reduce-xor.ll
…
vector-rotates.ll
…
vector-rounding-ops.ll
…
vector-sum-sat-bit-side-effect.ll
[PowerPC] remove side effect for some cases for saturate instructions
2023-03-13 21:37:56 -04:00
vector.ll
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vmladduhm.ll
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vperm-instcombine.ll
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vperm-lowering.ll
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vperm-swap.ll
[PowerPC] Optimize VPERM and fix code order for swapping vector operands on LE
2023-09-13 15:00:49 -05:00
vrsave-inline-asm.ll
…
vrspill.ll
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vsel-prom.ll
…
vselect-constants.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vsx_builtins.ll
…
vsx_insert_extract_le.ll
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vsx_scalar_ld_st.ll
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vsx_shuffle_le.ll
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vsx-args.ll
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VSX-DForm-Scalars.ll
…
vsx-div.ll
…
vsx-elementary-arith.ll
…
vsx-fma-m.ll
…
vsx-fma-mutate-trivial-copy.ll
…
vsx-fma-mutate-undef.ll
…
vsx-fma-sp.ll
…
vsx-infl-copy1.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
vsx-infl-copy2.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
vsx-ldst-builtin-le.ll
…
vsx-ldst.ll
…
vsx-minmax.ll
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vsx-p8.ll
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vsx-p9.ll
…
vsx-partword-int-loads-and-stores.ll
Reland "[PowerPC] Simplify fp-to-int store optimization"
2023-06-05 13:53:08 +08:00
vsx-recip-est.ll
…
vsx-self-copy.ll
…
vsx-shuffle-le-load.ll
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vsx-shuffle-le-multiple-uses.ll
…
vsx-spill-norwstore.ll
…
vsx-spill.ll
…
vsx-vec-spill.ll
…
vsx-word-splats.ll
…
VSX-XForm-Scalars.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vsx.ll
[PowerPC] improve P10 store forwarding on P7 scalar to vector (#102330)
2024-08-12 12:30:06 -04:00
vsxD-Form-spills.ll
…
vtable-reloc.ll
…
wa-asm-fpr.ll
…
weak_def_can_be_hidden.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
wide-scalar-shift-legalization.ll
[PowerPC] Add SDNPMemOperand to some nodes (#115580)
2024-11-15 20:36:56 +03:00
widen-vec-correctly-be.ll
[PowerPC] improve P10 store forwarding on P7 scalar to vector (#102330)
2024-08-12 12:30:06 -04:00
xray-attribute-instrumentation.ll
[XRay] Make xray_fn_idx entries PC-relative
2023-06-20 22:40:56 -07:00
xray-conditional-return.ll
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xray-ret-is-terminator.ll
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xray-tail-call-hidden.ll
[XRay][test] Make tests less sensitive to .Ltmp/Ltmp label changes
2023-06-18 13:32:40 -07:00
xray-tail-call-sled.ll
[XRay][test] Make tests less sensitive to .Ltmp/Ltmp label changes
2023-06-18 13:32:40 -07:00
xvcmpeqdp-v2f64.ll
…
xxeval-and-nand.ll
…
xxeval-eqv-nor-or-xor.ll
…
xxinsertw.ll
[PowerPC] Fix the undef register for VECINSERT
2024-04-11 04:01:07 -04:00
xxleqv_xxlnand_xxlorc.ll
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xxperm-swap.ll
[PowerPC] Fix the xxperm swap requirements
2023-04-05 20:13:40 -05:00
xxpermdi_mnemonics.s
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zero-not-run.ll
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zext-and-cmp.ll
…
zext-bitperm.ll
…
zext-free.ll
…