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llvm-project/llvm/test/CodeGen/RISCV
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Craig Topper b7d0c9b9d8
[SelectionDAG][RISCV] Treat zext nneg as sext in PromoteIntOp_ZERO_EXTEND if the promoted input is sign extended. (#145120) 
If the zext has the nneg flag and we can prove the promoted input
is sign extended, we can avoid generating an AND that we might not
be able to remove. RISC-V emits a lot of sext_inreg operations during
i32->i64 promotion that makes this likely.

I've restricted this to the case where the promoted type is the same
as the result type so we don't need to create an additional extend.

I've also restricted it to cases where the target has stated a
preference for sext like i32->i64 on RV64. This is largely to avoid
wasting time in computeNumSignBits until we have a test case that
benefits.
2025-06-21 18:56:00 -07:00
..
GlobalISel
fixup! [Remarks] Elaborate on called intrinsics (#143985)
2025-06-17 10:51:07 -07:00
intrinsics
…
rvv
[RISCV] Allow larger offset when matching build_vector as vid sequence (#144756)
2025-06-20 14:20:17 -07:00
abds-neg.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
abds.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
abdu-neg.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
abdu.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
add_sext_shl_constant.ll
[RISCV] Don't commute with shift if XAndesPerf is enabled (#142920)
2025-06-06 11:08:23 +08:00
add_shl_constant.ll
[RISCV] Don't commute with shift if XAndesPerf is enabled (#142920)
2025-06-06 11:08:23 +08:00
add-before-shl.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
add-imm64-to-sub.ll
[RISCV] Handle more (add x, C) -> (sub x, -C) cases (#138705)
2025-05-13 09:12:24 +02:00
add-imm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
addrspacecast.ll
…
aext-to-sext.ll
[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)
2024-11-25 18:59:31 -08:00
aext.ll
…
align-loops.ll
…
align.ll
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alloca.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
allow-check.ll
…
alu8.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
alu16.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
alu32.ll
…
alu64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
analyze-branch.ll
…
and-add-lsr.ll
…
and-shl.ll
[RISCV] Remove artificial restriction on ShAmt from (shl (and X, C2), C) -> (srli (slli X, C4), C4-C) isel. (#143010)
2025-06-05 17:48:35 -07:00
and.ll
…
arith-with-overflow.ll
…
atomic-cmpxchg-branch-on-result.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomic-fence.ll
…
atomic-load-store.ll
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
2024-12-17 00:19:45 -08:00
atomic-load-zext.ll
[RISCV] Remove AND mask generated by ( zext ( atomic_load ) ) by replacing the load with zextload for orderings not stronger then monotonic. (#136502)
2025-04-28 08:35:51 -07:00
atomic-rmw-discard.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
atomic-rmw-sub.ll
…
atomic-rmw.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
atomic-signext.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
atomicrmw-cond-sub-clamp.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
atomicrmw-uinc-udec-wrap.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
attributes-module-flag.ll
…
attributes-sifive.ll
[RISCV] Add MC layer support for XSfmm*. (#133031)
2025-05-21 08:26:35 -07:00
attributes.ll
[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (#144320)
2025-06-18 09:17:46 +08:00
avgceils.ll
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avgceilu.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
avgfloors.ll
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avgflooru.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
bf16-promote.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bfloat-arith.ll
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bfloat-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
bfloat-convert.ll
[RISCV][LibCall] Add libcall for i64 -> bf16 (#130024)
2025-03-07 09:23:50 +08:00
bfloat-fcmp.ll
…
bfloat-frem.ll
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bfloat-imm.ll
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bfloat-isnan.ll
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bfloat-mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bfloat-select-fcmp.ll
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bfloat-select-icmp.ll
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bfloat.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bitextract-mac.ll
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bitreverse-shift.ll
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bittest.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
blockaddress.ll
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branch_zero.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
branch-on-zero.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
branch-opt.ll
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branch-opt.mir
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branch-relaxation-rv32.ll
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branch-relaxation-rv32e.ll
[RISCV] Use X9 instead of X27 in RISCVInstrInfo::insertIndirectBranch for RVE (#139214)
2025-05-09 08:41:14 -07:00
branch-relaxation-rv64.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
branch.ll
[CodeGen] Limit number of analyzed predecessors
2025-06-20 11:23:00 +02:00
bswap-bitreverse.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
bswap-shift.ll
[RISCV] Remove the TODO for folding bswap and shift from the test. (NFC) (#129972)
2025-03-06 13:02:17 +08:00
byval.ll
…
callee-saved-fpr32s.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
callee-saved-fpr64s.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
callee-saved-gprs.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
calling-conv-half.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
calling-conv-ilp32-ilp32f-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-ilp32.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32d.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32e.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-ilp32f-ilp32d-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64-lp64f-common.ll
…
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
calling-conv-lp64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-rv32f-ilp32.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-rv32f-ilp32e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-sext-zext.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-vector-float.ll
…
calling-conv-vector-on-stack.ll
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calls.ll
[RISCV][GISel] Use the correct calling convention during call lowering (#142148)
2025-05-30 18:55:32 +02:00
clear-cache.ll
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cm_mvas_mvsa.ll
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cm_mvas_mvsa.mir
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cmov-branch-opt.ll
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cmp-bool.ll
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codemodel-lowering.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
compress-double.ll
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compress-float.ll
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compress-inline-asm.ll
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compress-opt-branch.ll
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compress-opt-select.ll
[llc] Add -M for InstPrinter options
2025-04-08 19:34:03 -07:00
compress.ll
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condbinops.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
condops.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
constpool-known-bits.ll
Re-commit "[RISCV] Properly support RISCVISD::LLA in getTargetConstantFromLoad. (#145112)"
2025-06-21 10:18:49 -07:00
convert-highly-predictable-select-to-branch.ll
[RISCV] Rename some Feature* to Tune* (#117966)
2024-11-28 15:01:49 +08:00
copy-frameindex.mir
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copyprop.ll
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copysign-casts.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
csr-first-use-cost.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
ctlz-cttz-ctpop.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
ctz_zero_return_test.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
debug-line.ll
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
di-assignment-tracking-vector.ll
[DebugInfo] Handle additional types of stores in assignment tracking (#129070)
2025-04-22 17:14:25 +01:00
disable-tail-calls.ll
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disjoint.ll
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div_minsize.ll
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div-by-constant.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
div-pow2.ll
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div.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
double_reduct.ll
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double-arith-strict.ll
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2025-05-27 21:52:20 -07:00
double-arith.ll
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2025-05-27 21:52:20 -07:00
double-bitmanip-dagcombines.ll
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double-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
double-calling-conv.ll
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
double-convert-strict.ll
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double-convert.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
double-fcmp-strict.ll
DAG: Assert fcmp uno runtime calls are boolean values (#142898)
2025-06-10 10:46:29 +09:00
double-fcmp.ll
DAG: Assert fcmp uno runtime calls are boolean values (#142898)
2025-06-10 10:46:29 +09:00
double-frem.ll
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double-imm.ll
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2025-05-27 21:52:20 -07:00
double-intrinsics-strict.ll
[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC
2024-11-27 10:24:34 -08:00
double-intrinsics.ll
[RISCV] Remove the TODO for fmaximum/fminimum from the tests. (NFC) (#129969)
2025-03-06 13:01:58 +08:00
double-isnan.ll
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double-maximum-minimum.ll
[RISCV] Remove unused check prefixes from double maximum/minimum test. NFC
2025-03-17 16:39:51 +08:00
double-mem.ll
[RISCV] Add X0_Pair to RISCVDeadRegisterDefinitions. (#141831)
2025-05-28 14:59:28 -07:00
double-previous-failure.ll
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
double-round-conv-sat.ll
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2025-05-27 21:52:20 -07:00
double-round-conv.ll
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double-select-fcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-select-icmp.ll
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double-stack-spill-restore.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-zfa.ll
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
dso_local_equivalent.ll
AsmPrinter: Remove ELF's special lowerRelativeReference for unnamed_addr function; use lowerDSOLocalEquivalent in more cases
2025-04-08 10:11:20 -07:00
dwarf-eh.ll
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early-clobber-tied-def-subreg-liveness.ll
[RISCV] Refine location size for segment spill and fill (#133268)
2025-03-28 07:06:17 -07:00
eh-dwarf-cfa.ll
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elf-preemption.ll
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emit-x8-as-fp.ll
[RISCV][MC] Emit x8 as fp instead of s0 (#135500)
2025-04-14 14:48:47 +08:00
emutls.ll
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exception-pointer-register.ll
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fastcc-bf16.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-float.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-half.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-int.ll
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fastcc-without-f-reg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
features-info.ll
[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (#144320)
2025-06-18 09:17:46 +08:00
fixed-csr.ll
[RISCV][MRI] Account for fixed registers when determining callee saved regs (#115756)
2024-12-06 14:07:27 -05:00
fixups-diff.ll
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fli-licm.ll
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float-arith-strict.ll
…
float-arith.ll
…
float-bit-preserving-dagcombines.ll
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float-bitmanip-dagcombines.ll
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float-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
float-convert-strict.ll
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float-convert.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
float-fcmp-strict.ll
DAG: Assert fcmp uno runtime calls are boolean values (#142898)
2025-06-10 10:46:29 +09:00
float-fcmp.ll
DAG: Assert fcmp uno runtime calls are boolean values (#142898)
2025-06-10 10:46:29 +09:00
float-frem.ll
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float-imm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
float-intrinsics-strict.ll
[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC
2024-11-27 10:24:34 -08:00
float-intrinsics.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
float-isnan.ll
…
float-maximum-minimum.ll
…
float-mem.ll
…
float-round-conv-sat.ll
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float-round-conv.ll
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float-select-fcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
float-select-icmp.ll
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float-select-verify.ll
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float-zfa.ll
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
flt-rounds.ll
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fmax-fmin.ll
…
fold-addi-loadstore-zilsd.ll
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2025-05-27 21:52:20 -07:00
fold-addi-loadstore.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
fold-binop-into-select-return-constant.ll
…
fold-binop-into-select.ll
…
fold-masked-merge.ll
Reland "[SelectionDAG] Make (a & x) | (~a & y) -> (a & (x ^ y)) ^ y available for all targets" (#143651)
2025-06-11 15:56:37 +08:00
fold-mem-offset.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
fold-mem-offset.mir
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
2025-04-22 19:24:29 -07:00
forced-atomics.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fp16-promote.ll
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fp128.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fp-fcanonicalize.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fpclamptosat.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
fpenv-xlen.ll
[RISCV][FPEnv] Lowering of fpenv intrinsics (#141498)
2025-06-11 19:08:23 +07:00
fpenv.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
frame-info.ll
…
frame.ll
…
frameaddr-returnaddr.ll
…
frm-dependency.ll
[RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). (#133200)
2025-03-27 07:45:42 -07:00
frm-write-in-loop.ll
[RISCV][FPEnv] Lowering of fpenv intrinsics (#141498)
2025-06-11 19:08:23 +07:00
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
ghccc-nest.ll
…
ghccc-rv32.ll
…
ghccc-rv64.ll
…
ghccc-without-f-reg.ll
…
global-merge-minsize-smalldata-nonzero.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-minsize-smalldata-zero.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-minsize.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-offset.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
graalcc.ll
…
half-arith-strict.ll
[RISCV] Remove unused check prefixes from half arith strict test. NFC
2025-03-17 12:51:39 +08:00
half-arith.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
half-bitmanip-dagcombines.ll
…
half-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
half-convert-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-convert.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
half-fcmp-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-fcmp.ll
…
half-frem.ll
…
half-imm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
half-intrinsics.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
half-isnan.ll
…
half-maximum-minimum.ll
…
half-mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-round-conv-sat.ll
…
half-round-conv.ll
…
half-select-fcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-select-icmp.ll
…
half-zfa-fli.ll
…
half-zfa.ll
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
hoist-global-addr-base.ll
…
hwasan-check-memaccess.ll
[llc] Add -M for InstPrinter options
2025-04-08 19:34:03 -07:00
i32-icmp.ll
[RISCV] Use QC_E_ADDI to improve codegen for icmp {eq, ne} with a constant (#139558)
2025-05-13 07:46:16 +05:30
i64-icmp.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
iabs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
icmp-non-byte-sized.ll
[RISCV] Support non-power-of-2 types when expanding memcmp
2025-06-18 16:11:18 +08:00
idiv_large.ll
…
imm-cse.ll
…
imm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
indirectbr.ll
…
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-d-modifier-N.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-f-modifier-N.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
[RISCV] Check the VT for R and cR inline asm constraints is 2*xlen. (#137749)
2025-04-29 08:12:32 -07:00
inline-asm-mem-constraint-2.ll
…
inline-asm-mem-constraint.ll
[ARM,AArch64] Don't put BTI at asm goto branch targets (#141562)
2025-06-03 08:44:13 +01:00
inline-asm-s-constraint-error.ll
…
inline-asm-s-constraint.ll
…
inline-asm-v-constraint.ll
[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283)
2024-12-06 00:48:05 +08:00
inline-asm-xsfvcp.ll
…
inline-asm-zdinx-constraint-r.ll
…
inline-asm-zfh-constraint-f.ll
…
inline-asm-zfh-modifier-N.ll
…
inline-asm-zfinx-constraint-r.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-zhinx-constraint-r.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-option-directive.ll
…
instruction-count-remark.mir
Register assembly printer passes (#138348)
2025-05-06 18:01:17 -07:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
…
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
[RISCV] Save vector registers in interrupt handler. (#143808)
2025-06-18 17:48:10 -07:00
intrinsic-cttz-elts-vscale.ll
[RISCV] Use a precise size for MMO on scalable spill and fill (#133171)
2025-03-26 18:25:59 -07:00
intrinsic-cttz-elts.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
ipra.ll
[RISCV] Implement getIPRACSRegs hook (#125586)
2025-02-04 10:02:42 -03:00
isel-optnone.ll
…
jumptable-swguarded.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
jumptable.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
kcfi-isel-mir.ll
[RISCV] Add call preserved regmask to tail calls. (#122181)
2025-01-08 16:19:31 -08:00
kcfi-mir.ll
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
kcfi-patchable-function-prefix.ll
…
kcfi.ll
[RISCV,test] Replace -riscv-no-aliases with -M no-aliases
2025-04-08 19:42:43 -07:00
lack-of-signed-truncation-check.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
large-stack.ll
…
legalize-fneg.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
libcall-tail-calls.ll
…
lit.local.cfg
…
live-sp.mir
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
llvm.exp10.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
llvm.frexp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
load-setcc-combine.ll
…
load-store-pair.ll
[RISCV] Generate MIPS load/store pair instructions (#124717)
2025-03-07 09:21:36 +01:00
local-stack-slot-allocation.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
loop-strength-reduce-add-cheaper-than-mul.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
loop-strength-reduce-loop-invar.ll
…
lpad.ll
[RISCV] Remove Last Traces of User Interrupts (#129300)
2025-03-04 11:36:16 -08:00
lsr-legaladdimm.ll
…
machine-combiner-mir.ll
…
machine-combiner-strategies.ll
…
machine-combiner.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
machine-combiner.mir
…
machine-copyprop-noop-removal.mir
[MachineCopyPropagation] Recognise and delete no-op moves produced after forwarded uses (#129889)
2025-03-10 13:22:59 +00:00
machine-copyprop-simplifyinstruction.mir
[MCP] Handle iterative simplification during forward copy prop (#140267)
2025-06-02 11:21:41 -07:00
machine-cp.mir
…
machine-cse.ll
…
machine-outliner-and-machine-copy-propagation.ll
…
machine-outliner-call-x5-liveout.mir
[RISCV] [MachineOutliner] Analyze all candidates (#127659)
2025-02-21 12:53:13 +05:30
machine-outliner-call.ll
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-cfi.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-leaf-descendants.ll
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-patchable.ll
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-position.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-throw.ll
…
machine-pipeliner.ll
[RISCV] Add software pipeliner support (#117546)
2024-12-19 13:00:08 +08:00
machine-sink-load-immediate.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
machinelicm-address-pseudos.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
machinelicm-constant-phys-reg.ll
…
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
…
machineoutliner-x5.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machineoutliner.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
MachineSink-implicit-x0.mir
[CodeGen][NewPM] Port MachineSink to NPM (#115434)
2025-03-03 15:49:37 +05:30
macro-fusion-lui-addi.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
macro-fusions.mir
…
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
…
make-compressible-zbc-zhinx.mir
…
make-compressible-zbc.mir
…
make-compressible-zfinx.mir
…
make-compressible-zilsd.mir
[RISCV] Correctly account for the copy cost of GPR pairs in RISCVMakeCompressible. (#141251)
2025-05-23 11:37:42 -07:00
make-compressible.mir
…
mem64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memcmp-optsize.ll
[RISCV] Support non-power-of-2 types when expanding memcmp
2025-06-18 16:11:18 +08:00
memcmp.ll
[RISCV] Support non-power-of-2 types when expanding memcmp
2025-06-18 16:11:18 +08:00
memcpy-inline.ll
…
memcpy.ll
Reapply "[RISCV] Rework memcpy test (#120364)"
2025-01-13 12:06:26 +08:00
memmove.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memset-inline.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
memset-pattern.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
min-max.ll
…
mir-target-flags.ll
…
misched-load-clustering.ll
…
misched-mem-clustering.mir
…
misched-postra-direction.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
miss-sp-restore-eh.ll
Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#136701)
2025-04-22 17:36:41 -04:00
module-elf-flags.ll
…
module-target-abi2.ll
…
module-target-abi3.ll
…
module-target-abi.ll
…
mul-expand.ll
[RISCV] Expand constant multiplication for targets without M extension (#137195)
2025-05-16 09:40:11 +08:00
mul.ll
[RISCV] Expand constant multiplication for targets without M extension (#137195)
2025-05-16 09:40:11 +08:00
musttail-call.ll
…
naked-fn-with-frame-pointer.ll
…
narrow-shl-cst.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
neg-abs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
nest-register.ll
[RISCV] Guard the alternative static chain register use on ILP32E/LP64E (#142715)
2025-06-12 02:24:10 +08:00
nomerge.ll
…
nontemporal-scalable.ll
…
nontemporal.ll
…
note-gnu-property-zicfiss.ll
[RISCV] Emit .note.gnu.property section when Zicfiss-based shadow stack is enabled (#127036)
2025-05-14 11:48:59 +08:00
O0-pipeline.ll
[RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation (#139993)
2025-06-17 17:21:24 +08:00
O3-pipeline.ll
[RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation (#139993)
2025-06-17 17:21:24 +08:00
opt-w-instrs.mir
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
option-exact-inlineasm.ll
[RISCV] Support .option {no}exact (#122483)
2025-03-26 11:14:16 -07:00
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax-relocation.ll
RISCV: Remove shouldForceRelocation and unneeded relocations
2025-05-23 18:44:15 -07:00
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
or-is-add.ll
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
2025-02-25 10:04:57 -08:00
orc-b-patterns.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
out-of-reach-emergency-slot.mir
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
overflow-intrinsic-optimizations.ll
…
overflow-intrinsics.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
patchable-function-entry.ll
[RISCV,test] Replace -riscv-no-aliases with -M no-aliases
2025-04-08 19:42:43 -07:00
pei-crash.ll
…
pic-models.ll
…
poison-legalization.ll
Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison value in the IR." (#135056)
2025-04-10 11:29:14 -04:00
postra-copy-expand.mir
[RISCV] Attach an implicit source operand on vector copies (#126155)
2025-02-08 16:25:27 -08:00
pr40333.ll
…
pr51206.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr53662.mir
…
pr55201.ll
…
pr56110.ll
…
pr56457.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr58025.ll
…
pr58286.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr58511.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr63365.ll
…
pr63816.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr64503.ll
…
pr64645.ll
…
pr64772.ll
…
pr64935.ll
…
pr65025.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
pr66603.ll
…
pr68855.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr69586.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr80052.mir
…
pr84200.ll
…
pr84653_pr85190.ll
[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)
2024-12-19 21:38:20 +01:00
pr88365.ll
…
pr90652.ll
…
pr90730.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr92193.ll
…
pr94145.ll
…
pr94265.ll
…
pr95271.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr95284.ll
…
pr96366.ll
…
pr97304.ll
…
pr101786.ll
[CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (#102731)
2025-04-23 08:54:10 +03:00
pr135206.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr142004.ll
[DAGCombiner] Teach SearchForAndLoads to handle an AND with 2 constant operands. (#142062)
2025-05-30 16:00:43 -07:00
prefer-w-inst.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
prefer-w-inst.mir
…
prefetch.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
prolog-epilogue.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
push-pop-opt-crash.ll
[RISCV] Update unrelated bad code from test case
2025-03-19 11:09:49 -07:00
push-pop-popret.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
qci-interrupt-attr-fpr.ll
[RISCV] QCI Interrupt Support (#129957)
2025-03-06 13:31:08 -08:00
qci-interrupt-attr.ll
[RISCV] Support Push/Pop with Xqci (#134191)
2025-04-28 08:12:45 -07:00
rda-stack.mir
[ReachingDefAnalysis] Fix management of MBBFrameObjsReachingDefs (#124943)
2025-02-04 10:04:19 -05:00
readcyclecounter.ll
…
readsteadycounter.ll
…
reassoc-shl-addi-add.ll
[RISCV] Simplify and remove unrelated testcases in reassoc-shl-addi-add.ll. NFC.
2025-06-10 19:10:48 +08:00
reduce-unnecessary-extension.ll
…
reduction-formation.ll
…
redundant-copy-from-tail-duplicate.ll
[RISCV] Set AllocationPriority in line with LMUL (#131176)
2025-03-18 08:25:49 -07:00
regalloc-last-chance-recoloring-failure.ll
[RISCV] Refine location size for segment spill and fill (#133268)
2025-03-28 07:06:17 -07:00
relative-reloc.ll
AsmPrinter: Remove ELF's special lowerRelativeReference for unnamed_addr function; use lowerDSOLocalEquivalent in more cases
2025-04-08 10:11:20 -07:00
relax-per-target-feature.ll
…
rem.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
remat.ll
…
renamable-copy.mir
…
repeated-fp-divisors.ll
…
replace-with-veclib-sleef-scalable.ll
[RISCV][SLEEF] Fix incorrect vector function mapping for llvm.exp.f64 (#121641)
2025-05-12 13:34:46 +08:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegen-prepare-atp.ll
…
riscv-codegenprepare-asm.ll
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
riscv-codegenprepare.ll
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
riscv-func-target-feature.ll
…
riscv-tail-dup-size.ll
…
riscv-zihintpause.ll
[RISCV] Add zihintpause LLVM/Clang intrinsic (#139519)
2025-05-16 14:20:53 +08:00
rotl-rotr.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32-fuchsia.ll
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rv32-inline-asm-pairs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll
[RISCV] Remove the TODO for lowering f32 libcall on RV64 with lp64 abi. (NFC)
2025-03-07 10:52:04 +08:00
rv32i-rv64i-half.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv32xandesperf.ll
[RISCV] Select signed bitfield insert for XAndesPerf (#143356)
2025-06-11 13:32:49 +08:00
rv32xtheadba.ll
[RISCV] Add 2^N + 2^M expanding pattern for mul (#137954)
2025-05-10 11:16:39 +08:00
rv32xtheadbb.ll
[CGP] Despeculate ctlz/cttz with "illegal" integer types (#137197)
2025-04-29 22:33:40 +03:00
rv32xtheadbs.ll
…
rv32zba.ll
[RISCV] Implement codegen for XAndesPerf lea instructions (#137925)
2025-05-12 10:41:53 +08:00
rv32zbb-intrinsic.ll
[RISCV] Add ORC_B to SimplifyDemandedBitsForTargetNode. (#141975)
2025-05-29 12:33:36 -07:00
rv32zbb-zbkb.ll
[RISCV] Sink NOT to be fold into ANDN/ORN/XNOR/VANDN (#131632)
2025-03-19 06:06:13 +01:00
rv32zbb.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
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rv32zbkb.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32zimop-intrinsic.ll
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rv32zknd-intrinsic-autoupgrade.ll
…
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic-autoupgrade.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic-autoupgrade.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-double-convert-strict.ll
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rv64-double-convert.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-float-convert-strict.ll
[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)
2024-12-02 09:06:08 -08:00
rv64-float-convert.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64-half-convert-strict.ll
[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)
2024-12-02 09:06:08 -08:00
rv64-half-convert.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64-inline-asm-pairs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-large-stack.ll
…
rv64-patchpoint.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64-stackmap-args.ll
[CodeGen] @llvm.experimental.stackmap make operands immediate (#117932)
2024-12-11 17:41:19 +08:00
rv64-stackmap-frame-setup.ll
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rv64-stackmap-nops.ll
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rv64-stackmap.ll
…
rv64-statepoint-call-lowering-x1.ll
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rv64-statepoint-call-lowering-x2.ll
…
rv64-statepoint-call-lowering.ll
…
rv64-trampoline-cfi.ll
[RISC-V] Adjust trampoline code for branch control flow protection (#141949)
2025-06-07 23:51:08 +08:00
rv64-trampoline.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64-typepromotion.ll
…
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
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rv64e.ll
…
rv64f-float-convert-strict.ll
…
rv64f-float-convert.ll
…
rv64i-complex-float.ll
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rv64i-demanded-bits.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64i-double-softfloat.ll
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rv64i-exhaustive-w-insts.ll
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rv64i-shift-sext.ll
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rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
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rv64m-exhaustive-w-insts.ll
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rv64m-w-insts-legalization.ll
[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)
2024-11-25 18:59:31 -08:00
rv64xandesperf.ll
[RISCV] Select signed bitfield insert for XAndesPerf (#143356)
2025-06-11 13:32:49 +08:00
rv64xtheadba.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64xtheadbb.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64xtheadbs.ll
…
rv64zba.ll
[RISCV] Select (add/or C, x) -> (add.uw C|0xffffffff00000000, x) (#143375)
2025-06-10 13:28:49 +02:00
rv64zbb-intrinsic.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64zbb-zbkb.ll
[RISCV] Sink NOT to be fold into ANDN/ORN/XNOR/VANDN (#131632)
2025-03-19 06:06:13 +01:00
rv64zbb.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkb.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
…
rv64zfh-half-intrinsics.ll
…
rv64zfhmin-half-convert-strict.ll
…
rv64zfhmin-half-convert.ll
…
rv64zfhmin-half-intrinsics.ll
…
rv64zimop-intrinsic.ll
…
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic-autoupgrade2.ll
…
rv64zksed-intrinsic-autoupgrade.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic-autoupgrade.ll
…
rv64zksh-intrinsic.ll
…
sadd_sat_plus.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
sadd_sat.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
saverestore-scs.ll
…
saverestore.ll
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scmp.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
sdata-limit-0.ll
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sdata-limit-4.ll
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sdata-limit-8.ll
…
sdata-local-sym.ll
…
sdata-sections.ll
…
sdiv-pow2-cmov.ll
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select-and.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-bare.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-binop-identity.ll
…
select-cc.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
select-cond.ll
[RISCV][NFC] Improve test coverage for xtheadcondmov and xmipscmov (#143567)
2025-06-11 09:56:12 +05:30
select-const.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
select-constant-xor.ll
[CodeGenPrepare][RISCV] Combine (X ^ Y) and (X == Y) where appropriate (#130922)
2025-04-02 09:56:09 -07:00
select-optimize-multiple.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
select-optimize-multiple.mir
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select-or.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-to-and-zext.ll
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select.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
selectcc-to-shiftand.ll
[RISCV] Remove the FIXME for using sraiw+and. NFC.
2025-04-22 09:13:11 +08:00
setcc-logic.ll
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sext-zext-trunc.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
sextw-removal-debug.mir
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sextw-removal.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
shadowcallstack.ll
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shift-amount-mod.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
shift-and.ll
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shift-masked-shamt.ll
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shifts.ll
[SelectionDAG][RISCV] Treat zext nneg as sext in PromoteIntOp_ZERO_EXTEND if the promoted input is sign extended. (#145120)
2025-06-21 18:56:00 -07:00
shl-cttz.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
shl-demanded.ll
…
shlimm-addimm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
short-forward-branch-opt.ll
[RISCV] Lower SELECT's with one constant more efficiently using Zicond (#143581)
2025-06-13 08:57:46 -04:00
shrinkwrap-jump-table.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
shrinkwrap.ll
[RISCV] Add shrinkwrap test cases showing gaps in current impl
2024-11-27 11:14:51 -08:00
sifive7-enable-intervals.mir
[MISched] Unify the way to specify scheduling direction (#119518)
2024-12-12 11:24:07 +08:00
sifive-interrupt-attr-err.ll
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
sifive-interrupt-attr.ll
[RISCV] Fix Defs/Uses for SiFive CLIC Support (#137724)
2025-04-28 19:35:11 -07:00
signbit-test.ll
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signed-truncation-check.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
simplify-condbr.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
sink-and-fold-crash.mir
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sink-icmp.ll
…
spill-fill-fold.ll
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spill-fpr-scalar.ll
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spir-kernel-cc.ll
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split-offsets.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
split-sp-adjust.ll
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split-store.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
split-udiv-by-constant.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
split-urem-by-constant.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
srem-lkk.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
srem-seteq-illegal-types.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
srem-vector-lkk.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
srodata.ll
…
ssub_sat_plus.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
ssub_sat.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-clash-prologue-nounwind.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-clash-prologue.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-folding.ll
…
stack-guard-global.ll
…
stack-guard-tls.ll
…
stack-inst-compress.mir
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-offset.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-protector-target.ll
…
stack-realignment-with-variable-sized-objects.ll
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stack-realignment.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-slot-coloring.mir
[win] NFC: Rename EHCatchret to EHCont to allow for EH Continuation targets that aren't catchret instructions (#129953)
2025-03-06 09:28:44 -08:00
stack-slot-size.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
stack-store-check.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
subtarget-features-std-ext.ll
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switch-width.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
tagged-globals.ll
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tail-calls.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
target-abi-invalid.ll
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target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
…
tlsdesc-symbol.ll
…
trunc-free.ll
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trunc-nsw-nuw.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
typepromotion-overflow.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
uadd_sat_plus.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
uadd_sat.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
ucmp.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
umulo-128-legalisation-lowering.ll
…
unaligned-load-store.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
unfold-masked-merge-scalar-variablemask.ll
Reland "[SelectionDAG] Make (a & x) | (~a & y) -> (a & (x ^ y)) ^ y available for all targets" (#143651)
2025-06-11 15:56:37 +08:00
unroll-loop-cse.ll
…
urem-lkk.ll
…
urem-seteq-illegal-types.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
urem-vector-lkk.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
usub_sat_plus.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
usub_sat.ll
…
vararg-ilp32e.ll
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vararg.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
varargs-with-fp-and-second-adj.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
vector-abi.ll
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vector-tuple-zeroinitializer.ll
[RISCV] Handle zeroinitializer of vector tuple Type (#113995)
2024-12-04 13:40:02 +08:00
verify-instr.mir
…
vlenb.ll
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vscale-demanded-bits.ll
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wide-mem.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
wide-scalar-shift-legalization.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
xaluo.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
xcvalu.ll
[RISCV] Rename XCValu intrinsic name *_slet(u) to *_sle(u)) (#138498)
2025-05-06 09:57:07 +08:00
xcvbi.ll
…
xcvbitmanip.ll
…
xcvmac.ll
…
xcvmem-heuristic.ll
[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533)
2024-12-31 10:56:28 +08:00
xcvmem.ll
RISCV: Convert test to opaque pointers
2025-04-07 23:45:54 +07:00
xqccmp_mvas_mvsa.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-additional-stack.ll
[RISCV] Expand constant multiplication for targets without M extension (#137195)
2025-05-16 09:40:11 +08:00
xqccmp-callee-saved-gprs.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
xqccmp-cm-popretz.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-cm-push-pop.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-push-pop-popret.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
xqccmp-with-float.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
xqcia.ll
[RISCV] Add ISel patterns for Xqcia instructions (#136548)
2025-04-22 15:40:03 +05:30
xqcibi.ll
[RISCV] Add Xqcibi Select_GPR_Using_CC_<Imm> Pseudos to isSelectPseudo (#140698)
2025-05-22 08:57:26 +05:30
xqcibm-cto-clo.ll
[RISCV] Add patterns for generating QC_CTO and QC_CLO (#144532)
2025-06-18 07:54:08 +05:30
xqcibm-extract.ll
[RISCV] Don't prefer QC_EXT for SEXT_INREG patterns when Zbb is enabled (#144837)
2025-06-19 13:29:57 +05:30
xqcilia.ll
[RISCV] Add ISel patterns for Xqcilia instructions (#135724)
2025-04-16 06:48:56 +05:30
xqcilo.ll
[RISCV] Add basic ISel patterns for Xqcilo instructions (#135901)
2025-04-16 11:19:13 +05:30
xqcisls.ll
[RISCV] Add basic ISel patterns for Xqcisls instructions (#135918)
2025-04-16 13:10:56 +05:30
xray-attribute-instrumentation.ll
[XRay][RISCV] RISCV support for XRay (#117368)
2024-12-10 17:57:04 -08:00
xtheadfmemidx.ll
…
xtheadmac.ll
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xtheadmemidx.ll
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
xtheadmempair.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
zalasr-offset-folding.ll
[RISCV] Return false for Zalasr load/store in isWorthFoldingAdd. (#136799)
2025-04-23 14:47:42 -07:00
zbb-cmp-combine.ll
[RISCV][test] Fix a comment typo (#134242)
2025-04-07 20:47:21 +02:00
zbb-logic-neg-imm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
zcb-regalloc-hints.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
zcmp-additional-stack.ll
[RISCV] Expand constant multiplication for targets without M extension (#137195)
2025-05-16 09:40:11 +08:00
zcmp-cm-popretz.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
zcmp-cm-push-pop.mir
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
zcmp-prolog-epilog-crash.mir
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zcmp-with-float.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
zdinx-asm-constraint.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
zdinx-boundary-check.ll
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
zdinx-large-spill.mir
[RISCV] Tweak zdinx-large-spill.mir so it tests what it was intended to. NFC
2025-05-14 12:35:49 -07:00
zdinx-memoperand.ll
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
zdinx-spill.ll
[RISCV] Add test for spilling and reloading a GPRPair for Zdinx+RV32. NFC (#139983)
2025-05-15 08:34:18 -07:00
zext-with-load-is-free.ll
[RISCV] Remove the TODO that lbu and lhu should be selected to avoid the unnecessary masking. NFC.
2025-04-21 11:02:04 +08:00
zfh-half-intrinsics-strict.ll
[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633)
2024-11-25 16:12:45 -08:00
zfh-half-intrinsics.ll
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zfhmin-half-intrinsics-strict.ll
[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633)
2024-11-25 16:12:45 -08:00
zfhmin-half-intrinsics.ll
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zfhmin-imm.ll
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zicfilp-indirect-branch.ll
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zicond-opts.ll
[RISCV] Lower SELECT's with one constant more efficiently using Zicond (#143581)
2025-06-13 08:57:46 -04:00
zilsd.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
zmmul.ll
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