pico-ice-video/ice/mandelbrot/mandelbrot.rdf

<?xml version="1.0" encoding="UTF-8"?>
<RadiantProject version="4.2" radiant="2024.1.0.34.2" title="mandelbrot" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" family_int="ice40tp" device_int="itpa08" package_int="SG48" operation_int="IND" speed_int="6" default_implementation="impl_1">
    <Options/>
    <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1">
        <Options def_top="top" top="top"/>
        <Source name="source/impl_1/top.sv" type="Verilog" type_short="Verilog">
            <Options VerilogStandard="System Verilog" top_module="top"/>
        </Source>
        <Source name="../ram.sv" type="Verilog" type_short="Verilog">
            <Options VerilogStandard="System Verilog"/>
        </Source>
        <Source name="../coords.sv" type="Verilog" type_short="Verilog">
            <Options VerilogStandard="System Verilog"/>
        </Source>
        <Source name="source/impl_1/renderer.sv" type="Verilog" type_short="Verilog">
            <Options VerilogStandard="System Verilog"/>
        </Source>
        <Source name="source/impl_1/multiplier.sv" type="Verilog" type_short="Verilog">
            <Options VerilogStandard="System Verilog"/>
        </Source>
        <Source name="../spram.sv" type="Verilog" type_short="Verilog">
            <Options VerilogStandard="System Verilog"/>
        </Source>
        <Source name="../constraints.pdc" type="Physical Constraints File" type_short="PDC">
            <Options/>
        </Source>
        <Source name="../constraints.sdc" type="Pre-Synthesis Constraints File" type_short="SDC">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="mandelbrot1.sty"/>
</RadiantProject>