Mirko Brkušanin 80f3b376b3

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731) ...

When either one of the operands is all ones in high or low parts,
splitting these opens up other opportunities for combines. One of two
new instructions will either be removed or become a simple copy.

2025-08-20 17:32:29 +02:00

..

add_shl.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

add.v2i16.ll

[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)

2025-05-16 10:31:03 +02:00

add.vni16.ll

MachineScheduler: Improve instruction clustering (#137784)

2025-06-05 15:28:04 +08:00

addo.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

addsubu64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

amdgpu-irtranslator.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

amdgpu-prelegalizer-combiner-crash.mir

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and.ll

[GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (#138574)

2025-05-08 19:31:28 +02:00

andn2.i1.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

andn2.ll

[AMDGPU] Remove widen-16-bit-ops from CGP (#145483)

2025-07-16 10:14:19 +02:00

artifact-combiner-anyext.mir

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artifact-combiner-asserts.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

artifact-combiner-build-vector.mir

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artifact-combiner-concat-vectors.mir

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artifact-combiner-cse-leaves-dead-cast.mir

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artifact-combiner-extract.mir

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artifact-combiner-sext.mir

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artifact-combiner-trunc.mir

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artifact-combiner-unmerge-values.mir

[GlobalISel] Combine unmerge(unmerge()) if the result is legal. (#109606)

2024-09-25 07:04:09 +01:00

artifact-combiner-zext.mir

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ashr.ll

MachineScheduler: Reset next cluster candidate for each node (#139513)

2025-05-28 14:53:46 +08:00

assert-align.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

atomic_load_flat.ll

GlobalISel: Fix combine duplicating atomic loads (#111730)

2024-10-31 07:55:12 -07:00

atomic_load_global.ll

GlobalISel: Fix combine duplicating atomic loads (#111730)

2024-10-31 07:55:12 -07:00

atomic_load_local_2.ll

GlobalISel: Fix combine duplicating atomic loads (#111730)

2024-10-31 07:55:12 -07:00

atomic_load_local.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

atomic_optimizations_mul_one.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

atomic_store_local.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

atomicrmw_fmax.ll

[PHIElimination] Revert #131837 #146320 #146337 (#146850)

2025-07-03 07:48:08 -04:00

atomicrmw_fmin.ll

[PHIElimination] Revert #131837 #146320 #146337 (#146850)

2025-07-03 07:48:08 -04:00

atomicrmw_udec_wrap.ll

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

atomicrmw_uinc_wrap.ll

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

bitcast_38_i16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

bool-legalization.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

br-constant-invalid-sgpr-copy.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

bswap.ll

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buffer-atomic-fadd.f32-no-rtn.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

buffer-atomic-fadd.f32-rtn.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

buffer-atomic-fadd.f64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

buffer-atomic-fadd.v2f16-no-rtn.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

buffer-atomic-fadd.v2f16-rtn.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

buffer-load-store-pointers.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

buffer-schedule.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

bug_shuffle_vector_to_scalar.ll

[GISel] Fix ShuffleVector assert (#139769)

2025-05-20 21:25:31 -04:00

bug-legalization-artifact-combiner-dead-def.ll

AMDGPU: Replace tests using undef in shufflevector with poison (#130899)

2025-03-12 20:45:02 +07:00

bug-legalization-artifact-combiner-dead-def.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

call-outgoing-stack-args.ll

[GISel] Introduce MachineIRBuilder::(build|materialize)ObjectPtrOffset (#150392)

2025-07-29 13:04:04 +02:00

clamp-fmed3-const-combine.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

clamp-minmax-const-combine.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

combine-add-nullptr.mir

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combine-add-to-ptradd.mir

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combine-amdgpu-cvt-f32-ubyte.mir

Revert "[GlobalISel] Combine [s,z]ext of undef into 0" (#118746)

2024-12-05 07:48:20 +01:00

combine-ashr-narrow.mir

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combine-binop-s64-with-s32-mask.mir

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

combine-ext-legalizer.mir

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combine-extract-vector-load.mir

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combine-fabs-fneg.mir

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combine-fcanonicalize.mir

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combine-fdiv-sqrt-to-rsq.mir

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combine-fma-add-ext-fma.ll

AMDGPU/GlobalISel: Fix isExtractHiElt when selecting fma_mix (#102130)

2024-08-07 12:13:39 +02:00

combine-fma-add-ext-mul.ll

[AMDGPU][GlobalISel] Align selectVOP3PMadMixModsImpl with the SelectionDAG counterpart (#110168)

2024-10-08 09:41:24 -04:00

combine-fma-add-fma-mul.ll

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

combine-fma-add-mul-post-legalize.mir

[GlobalISel] Remove UnsafeFPMath references (#146319)

2025-07-29 12:11:52 +08:00

combine-fma-add-mul-pre-legalize.mir

[GlobalISel] Remove UnsafeFPMath references (#146319)

2025-07-29 12:11:52 +08:00

combine-fma-add-mul.ll

[GlobalISel] Remove UnsafeFPMath references (#146319)

2025-07-29 12:11:52 +08:00

combine-fma-sub-ext-mul.ll

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combine-fma-sub-ext-neg-mul.ll

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combine-fma-sub-mul.ll

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

combine-fma-sub-neg-mul.ll

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combine-fma-unmerge-values.mir

[GlobalISel] Remove UnsafeFPMath references (#146319)

2025-07-29 12:11:52 +08:00

combine-fold-binop-into-select.mir

[GlobaISel] Allow expanding of sdiv -> mul by constant (#146504)

2025-07-14 15:01:12 +01:00

combine-foldable-fneg.mir

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combine-fpneg-one-fneg.mir

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combine-fsh.mir

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combine-fsub-fneg.mir

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combine-itofp.mir

[GlobalIsel] Combine trunc of binop (#107721)

2024-09-11 15:04:55 +02:00

combine-lshr-narrow.mir

[GlobalISel] Combine G_MERGE_VALUES of x and zero (#116283)

2024-11-16 08:00:21 +01:00

combine-or-redundant.mir

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combine-redundant-and.mir

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combine-redundant-neg.mir

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combine-redundant-sext-inreg.mir

[GlobalISel] Combine redundant sext_inreg (#131624)

2025-04-14 11:48:08 +02:00

combine-rot.mir

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combine-rsq.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

combine-rsq.mir

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combine-sext-inreg.mir

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combine-sext-trunc-sextinreg.mir

[GlobalISel] Combine redundant sext_inreg (#131624)

2025-04-14 11:48:08 +02:00

combine-shift-amount-zext.mir

[AMDGPU] Canonicalize G_ZEXT of the shift amount in RegBankCombiner (#131792)

2025-05-14 10:48:51 +02:00

combine-shift-imm-chain-illegal-types.mir

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combine-shift-imm-chain-shlsat.mir

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combine-shift-imm-chain.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

combine-shift-of-shifted-logic-shlsat.mir

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combine-shift-of-shifted-logic.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

combine-shifts.mir

[GISel] Fold shifts to constant result. (#123510)

2025-01-21 05:10:45 -08:00

combine-shl-from-extend-narrow.postlegal.mir

[GISel] Fold shifts to constant result. (#123510)

2025-01-21 05:10:45 -08:00

combine-shl-from-extend-narrow.prelegal.mir

[GISel] Fold shifts to constant result. (#123510)

2025-01-21 05:10:45 -08:00

combine-shl-narrow.mir

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combine-short-clamp.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

combine-trunc-sext.mir

[AMDGPU] Add sext_trunc in RegBankCombiner (#131623)

2025-04-14 10:15:29 +02:00

combine-trunc-shift.mir

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combine-urem-pow-2.mir

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combine-zext-trunc.mir

[GlobalIsel] Combine trunc of binop (#107721)

2024-09-11 15:04:55 +02:00

combiner-crash.ll

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compute-num-sign-bits-med3.mir

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constant-bus-restriction.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

crash-stack-address-O0.ll

AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)

2025-04-24 17:13:03 +02:00

cvt_f32_ubyte.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

dereferenceable-declaration.ll

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divergence-divergent-i1-phis-no-lane-mask-merging.ll

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

divergence-divergent-i1-phis-no-lane-mask-merging.mir

AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)

2025-03-12 12:15:00 +01:00

divergence-divergent-i1-used-outside-loop.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

divergence-divergent-i1-used-outside-loop.mir

AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)

2025-03-12 12:15:00 +01:00

divergence-structurizer.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

divergence-structurizer.mir

AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)

2025-03-12 12:15:00 +01:00

divergence-temporal-divergent-i1.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

divergence-temporal-divergent-i1.mir

AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)

2025-03-12 12:15:00 +01:00

divergence-temporal-divergent-reg.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

divergence-temporal-divergent-reg.mir

AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)

2025-03-12 12:09:37 +01:00

divergent-control-flow.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

dropped_debug_info_assert.ll

Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"

2025-05-17 21:41:59 -04:00

dummy-target.ll

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dynamic-alloca-uniform.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

extractelement-stack-lower.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

extractelement.i8.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

extractelement.i16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

extractelement.i128.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

extractelement.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

fdiv.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

fdiv.f32.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

fdiv.f64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

flat-atomic-fadd.f32.ll

[AMDGPU] Add NoaliasAddrSpace to AAMDnodes (#149247)

2025-07-29 10:10:06 +08:00

flat-atomic-fadd.f64.ll

[AMDGPU] Add NoaliasAddrSpace to AAMDnodes (#149247)

2025-07-29 10:10:06 +08:00

flat-atomic-fadd.v2f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

flat-scratch-init.gfx.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

flat-scratch-init.ll

[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)

2025-04-15 15:17:33 -07:00

flat-scratch.ll

[AMDGPU] Do not fold an immediate into instructions with frame indexes (#151263)

2025-08-06 11:47:37 -07:00

floor.f64.ll

AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)

2024-07-30 18:18:16 +04:00

fma.ll

[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)

2025-02-19 11:37:24 -05:00

fmamix-constant-bus-violation.ll

Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"

2024-11-08 20:21:16 -05:00

fmamix-constant-bus-violation.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

fmax_legacy.ll

AMDGPU: Replace ptr addrspace(3) undef in tests with poison (#131049)

2025-03-13 13:28:55 +07:00

fmed3-min-max-const-combine.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

fmin_legacy.ll

AMDGPU: Replace ptr addrspace(3) undef in tests with poison (#131049)

2025-03-13 13:28:55 +07:00

fmul.v2f16.ll

[AMDGPU] Re-Re-apply: Implement vop3p complex pattern optmization for gisel (#146984)

2025-07-08 15:10:44 +08:00

fp64-atomics-gfx90a.ll

[AMDGPU] Support 64-bit LDS atomic fadd on gfx1250 (#152368)

2025-08-06 13:07:56 -07:00

fp-atomics-gfx942.ll

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

fpow.ll

[AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (#128905)

2025-02-26 23:55:29 +07:00

frem.ll

[AMDGPU] Remove UnsafeFPMath uses (#151079)

2025-07-31 17:36:57 +08:00

fshl.ll

MachineScheduler: Reset next cluster candidate for each node (#139513)

2025-05-28 14:53:46 +08:00

fshr.ll

MachineScheduler: Reset next cluster candidate for each node (#139513)

2025-05-28 14:53:46 +08:00

function-returns.ll

[GISel] Set more MIFlags when translating GEPs (#151708)

2025-08-04 13:25:33 +02:00

function-returns.v2i65.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

global-atomic-fadd.f32-no-rtn.ll

[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)

2025-02-26 14:13:39 +01:00

global-atomic-fadd.f32-rtn.ll

[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)

2025-02-26 14:13:39 +01:00

global-atomic-fadd.f64.ll

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

global-atomic-fadd.v2f16-no-rtn.ll

[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)

2025-02-13 15:17:12 +01:00

global-atomic-fadd.v2f16-rtn.ll

[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)

2025-02-13 15:17:12 +01:00

global-value.illegal.ll

GlobalISel: Replace use of report_fatal_error (#145866)

2025-06-27 21:16:23 +09:00

global-value.ll

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hip.extern.shared.array.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

i1-copy.ll

AMDGPU: Replace some float undef test uses with poison (#131090)

2025-03-13 20:07:48 +07:00

image-waterfall-loop-O0.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

implicit-kernarg-backend-usage-global-isel.ll

[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)

2025-04-15 15:17:33 -07:00

inline-asm-mismatched-size.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

inline-asm.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

insertelement-stack-lower.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

insertelement.i8.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

insertelement.i16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

insertelement.large.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

insertelement.ll

Reland: [GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements (#144661)

2025-06-18 13:04:24 +02:00

inst-select-abs.mir

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inst-select-add.mir

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inst-select-add.s16.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-amdgcn.class.mir

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inst-select-amdgcn.class.s16.mir

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inst-select-amdgcn.cos.mir

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inst-select-amdgcn.cos.s16.mir

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inst-select-amdgcn.cvt.pk.i16.mir

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inst-select-amdgcn.cvt.pk.u16.mir

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inst-select-amdgcn.cvt.pknorm.i16.mir

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inst-select-amdgcn.cvt.pknorm.u16.mir

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inst-select-amdgcn.cvt.pkrtz.mir

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inst-select-amdgcn.ds.swizzle.mir

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inst-select-amdgcn.exp.compr.mir

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inst-select-amdgcn.exp.mir

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inst-select-amdgcn.fcmp.constants.w32.mir

[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)

2025-01-30 12:18:00 -05:00

inst-select-amdgcn.fcmp.constants.w64.mir

[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)

2025-01-30 12:18:00 -05:00

inst-select-amdgcn.fmad.ftz.mir

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inst-select-amdgcn.fmed3.mir

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inst-select-amdgcn.fmed3.s16.mir

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inst-select-amdgcn.fract.mir

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inst-select-amdgcn.fract.s16.mir

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inst-select-amdgcn.groupstaticsize.mir

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inst-select-amdgcn.mbcnt.lo.mir

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inst-select-amdgcn.mul.u24.mir

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inst-select-amdgcn.mulhi.i24.mir

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inst-select-amdgcn.mulhi.u24.mir

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inst-select-amdgcn.rcp.legacy.mir

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inst-select-amdgcn.rcp.mir

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inst-select-amdgcn.rcp.s16.mir

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inst-select-amdgcn.readfirstlane.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

inst-select-amdgcn.reloc.constant.mir

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inst-select-amdgcn.rsq.clamp.mir

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inst-select-amdgcn.rsq.legacy.mir

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inst-select-amdgcn.rsq.mir

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inst-select-amdgcn.rsq.s16.mir

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inst-select-amdgcn.s.barrier.mir

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inst-select-amdgcn.s.sendmsg.mir

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inst-select-amdgcn.sffbh.mir

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inst-select-amdgcn.sin.mir

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inst-select-amdgcn.sin.s16.mir

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inst-select-amdgpu-atomic-cmpxchg-flat.mir

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

inst-select-amdgpu-atomic-cmpxchg-global.mir

[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)

2024-09-24 11:08:41 +04:00

inst-select-amdgpu-ffbh-u32.mir

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inst-select-amdgpu-ffbl-b32.mir

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inst-select-amdgpu-wave-address.mir

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inst-select-and.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-anyext.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-ashr.mir

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inst-select-ashr.s16.mir

[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)

2025-06-26 14:08:13 -07:00

inst-select-ashr.v2s16.mir

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inst-select-atomic-cmpxchg-local.mir

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inst-select-atomic-cmpxchg-region.mir

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inst-select-atomicrmw-add-flat.mir

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

inst-select-atomicrmw-add-global.mir

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inst-select-atomicrmw-fadd-local.mir

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inst-select-atomicrmw-fadd-region.mir

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inst-select-atomicrmw-xchg-local.mir

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inst-select-atomicrmw-xchg-region.mir

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inst-select-bitcast.mir

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inst-select-bitreverse.mir

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inst-select-br.mir

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inst-select-brcond.mir

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inst-select-bswap.mir

Reapply "[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and … (#149262)

2025-07-21 10:14:45 -07:00

inst-select-build-vector-trunc.v2s16.mir

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inst-select-build-vector.mir

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inst-select-concat-vectors.mir

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inst-select-constant.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-copy.mir

[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)

2024-09-24 11:08:41 +04:00

inst-select-ctlz-zero-undef.mir

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inst-select-ctpop.mir

[TableGen][GISel] Import more "multi-level" patterns (#120332)

2024-12-18 14:44:55 +03:00

inst-select-cttz-zero-undef.mir

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inst-select-extract-vector-elt.mir

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inst-select-extract.mir

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inst-select-fabs.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-fadd.s16.mir

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inst-select-fadd.s32.mir

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inst-select-fadd.s64.mir

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inst-select-fcanonicalize.mir

[AMDGPU][True16][CodeGen] true16 codegen pattern for f16 canonicalize (#122000)

2025-01-24 10:44:00 -05:00

inst-select-fceil.mir

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inst-select-fceil.s16.mir

[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)

2024-10-16 12:26:01 -04:00

inst-select-fcmp.mir

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inst-select-fcmp.s16.gfx11plus-fake16.mir

[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)

2025-02-04 11:20:40 -05:00

inst-select-fcmp.s16.gfx11plus.mir

[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)

2025-02-04 11:20:40 -05:00

inst-select-fcmp.s16.mir

[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)

2025-02-04 11:20:40 -05:00

inst-select-fconstant.mir

AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)

2024-07-30 18:18:16 +04:00

inst-select-fexp2.mir

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inst-select-ffloor.s16.mir

[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)

2024-10-16 12:26:01 -04:00

inst-select-ffloor.s32.mir

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inst-select-ffloor.s64.mir

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inst-select-fma.s32.mir

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inst-select-fmad.s32.mir

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inst-select-fmaxnum-ieee.mir

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inst-select-fmaxnum-ieee.s16.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-fmaxnum-ieee.v2s16.mir

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inst-select-fmaxnum.mir

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inst-select-fmaxnum.s16.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-fmaxnum.v2s16.mir

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inst-select-fminnum-ieee.mir

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inst-select-fminnum-ieee.s16.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-fminnum-ieee.v2s16.mir

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inst-select-fminnum.mir

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inst-select-fminnum.s16.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-fminnum.v2s16.mir

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inst-select-fmul.mir

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inst-select-fmul.v2s16.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-fneg.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-fptosi.mir

[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)

2024-10-16 12:26:01 -04:00

inst-select-fptoui.mir

[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)

2024-10-16 12:26:01 -04:00

inst-select-fract.f64.mir

[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)

2024-09-24 11:08:41 +04:00

inst-select-frame-index.mir

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inst-select-freeze.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-fshr.mir

Reapply "[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and … (#149262)

2025-07-21 10:14:45 -07:00

inst-select-i1-copy.mir

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inst-select-icmp.mir

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inst-select-icmp.s16.mir

[AMDGPU][True16][CodeGen] gisel true16 for ICMP (#128913)

2025-03-13 12:03:17 -04:00

inst-select-icmp.s64.mir

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inst-select-implicit-def.mir

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inst-select-insert-vector-elt.mir

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inst-select-insert.mir

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inst-select-intrinsic-trunc.mir

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inst-select-intrinsic-trunc.s16.mir

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inst-select-inttoptr.mir

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inst-select-load-atomic-flat.mir

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

inst-select-load-atomic-global.mir

[AMDGPU] More flatGVS gfx1250 patterns (#149410)

2025-07-17 16:10:59 -07:00

inst-select-load-atomic-local.mir

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inst-select-load-constant.mir

AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)

2024-07-30 18:18:16 +04:00

inst-select-load-flat.mir

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

inst-select-load-global-old-legalization.mir

Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)

2024-11-01 11:13:29 -05:00

inst-select-load-global-saddr.mir

[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)

2024-09-24 11:08:41 +04:00

inst-select-load-global.mir

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inst-select-load-global.s96.mir

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inst-select-load-local-128.mir

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inst-select-load-local.mir

Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)

2024-11-01 11:13:29 -05:00

inst-select-load-private.mir

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inst-select-load-smrd.mir

AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)

2024-07-30 18:18:16 +04:00

inst-select-lshr.mir

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inst-select-lshr.s16.mir

[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)

2025-06-26 14:08:13 -07:00

inst-select-lshr.v2s16.mir

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inst-select-mad_64_32.mir

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inst-select-merge-values.mir

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inst-select-mul.mir

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inst-select-or.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-pattern-add3.mir

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inst-select-pattern-and-or.mir

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inst-select-pattern-or3.mir

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inst-select-pattern-smed3.mir

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inst-select-pattern-smed3.s16.mir

[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)

2025-06-26 14:08:13 -07:00

inst-select-pattern-umed3.mir

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inst-select-pattern-umed3.s16.mir

[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)

2025-06-26 14:08:13 -07:00

inst-select-pattern-xor3.mir

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inst-select-phi.mir

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inst-select-pseudo-scalar-transcendental.mir

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inst-select-ptr-add.mir

[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)

2024-07-28 11:26:29 +04:00

inst-select-ptrmask.mir

AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)

2024-07-30 18:18:16 +04:00

inst-select-ptrtoint.mir

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inst-select-returnaddress.mir

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inst-select-sbfx.mir

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inst-select-scalar-float-sop1.mir

[AMDGPU] Add some more GFX12 test coverage (#120581)

2024-12-23 09:42:52 +00:00

inst-select-scalar-float-sop2.mir

[AMDGPU] Add some more GFX12 test coverage (#120581)

2024-12-23 09:42:52 +00:00

inst-select-scalar-float-sopc.mir

[AMDGPU] Add some more GFX12 test coverage (#120581)

2024-12-23 09:42:52 +00:00

inst-select-scalar-packed.xfail.mir

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inst-select-select.mir

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inst-select-sext-inreg.mir

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inst-select-sext.mir

[TableGen][GISel] Extract helper function for constraining operands (#115148)

2024-11-07 07:16:54 +03:00

inst-select-sextload-local.mir

AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)

2024-10-10 14:01:49 +04:00

inst-select-shl.mir

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inst-select-shl.s16.mir

[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)

2025-06-26 14:08:13 -07:00

inst-select-shl.v2s16.mir

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inst-select-sitofp.mir

[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)

2024-10-16 12:26:01 -04:00

inst-select-smax.mir

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inst-select-smin.mir

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inst-select-smulh.mir

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inst-select-stacksave-stackrestore.invalid.mir

GlobalISel: Replace use of report_fatal_error (#145866)

2025-06-27 21:16:23 +09:00

inst-select-stacksave-stackrestore.mir

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inst-select-store-atomic-flat.mir

[AMDGPU] More flatGVS gfx1250 patterns (#149410)

2025-07-17 16:10:59 -07:00

inst-select-store-atomic-local.mir

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inst-select-store-flat.mir

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

inst-select-store-global.mir

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inst-select-store-global.s96.mir

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inst-select-store-local.mir

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inst-select-store-private.mir

[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)

2024-07-28 11:26:29 +04:00

inst-select-sub.mir

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inst-select-trunc.mir

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inst-select-trunc.v2s16.mir

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inst-select-uadde.gfx10.mir

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inst-select-uadde.mir

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inst-select-uaddo.mir

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inst-select-ubfx.mir

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inst-select-uitofp.mir

[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)

2024-10-16 12:26:01 -04:00

inst-select-umax.mir

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inst-select-umin.mir

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inst-select-umulh.mir

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inst-select-unmerge-values.mir

[AMDGPU] Fix failing test after #109958 (#109964)

2024-09-25 15:02:23 +02:00

inst-select-usube.gfx10.mir

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inst-select-usube.mir

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inst-select-usubo.mir

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inst-select-xor.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

inst-select-zext.mir

[TableGen][GISel] Extract helper function for constraining operands (#115148)

2024-11-07 07:16:54 +03:00

inst-select-zextload-local.mir

AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)

2024-10-10 14:01:49 +04:00

irtranslate-bf16.ll

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irtranslator-amdgcn-cs-chain.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-amdgcn-sendmsg.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-amdgpu_kernel-system-sgprs.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

irtranslator-amdgpu_kernel.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-amdgpu_ps.ll

AMDGPU: Replace undef with poison in tests using insertvalue (#130895)

2025-03-12 16:11:11 +07:00

irtranslator-amdgpu_vs.ll

AMDGPU: Replace some float undef test uses with poison (#131090)

2025-03-13 20:07:48 +07:00

irtranslator-assert-align.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-atomicrmw.ll

AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)

2025-04-24 17:13:03 +02:00

irtranslator-call-abi-attribute-hints.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-call-implicit-args.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-call-non-fixed.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-call-return-values.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-call-sret.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-call.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-constant-fold-vector-op.ll

AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)

2025-04-24 17:13:03 +02:00

irtranslator-constantexpr.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-constrained-fp.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-fast-math-flags.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

irtranslator-fence.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-fixed-function-abi-vgpr-args.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

irtranslator-function-args.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-function-args.v2i65.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

irtranslator-getelementptr.ll

…

irtranslator-indirect-call.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-inline-asm.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-invariant.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-memory-intrinsics.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-metadata.ll

Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"

2025-05-17 21:41:59 -04:00

irtranslator-non-integral-address-spaces-vectors.ll

[AMDGPULowerBufferFatPointers] Use InstSimplifyFolder during rewrites (#134137)

2025-04-03 10:12:18 -05:00

irtranslator-non-integral-address-spaces.ll

…

irtranslator-prefetch.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-ptrmask.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-readnone-intrinsic-callsite.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

irtranslator-sat.ll

…

irtranslator-sibling-call.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-struct-return-intrinsics.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

irtranslator-tail-call.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-zext-vec-index.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

is-safe-to-sink-bug.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

known-bits-sbfe.mir

[AMDGPU] Compute GISel KnownBits for S_BFE instructions (#141588)

2025-07-16 09:56:45 +02:00

knownbits-ptrtoint.mir

[GISelValueTracking] Add test case for G_PTRTOINT

2025-06-11 10:47:17 -07:00

lds-global-value.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

lds-misaligned-bug.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

lds-relocs.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

lds-zero-initializer.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

legalize-abs.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-add.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-addrspacecast.mir

[AMDGPU] Implement addrspacecast from flat <-> private on gfx1250 (#152218)

2025-08-05 16:25:23 -07:00

legalize-amdgcn.if-invalid.mir

…

legalize-amdgcn.if.xfail.mir

…

legalize-amdgcn.rsq.clamp.mir

…

legalize-amdgcn.wavefrontsize.mir

…

legalize-amdgcn.workitem.id.mir

…

legalize-and.mir

[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)

2024-12-16 05:57:11 +00:00

legalize-anyext.mir

…

legalize-ashr.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-atomic-cmpxchg-with-success.mir

…

legalize-atomic-cmpxchg.mir

…

legalize-atomicrmw-add.mir

…

legalize-atomicrmw-and.mir

…

legalize-atomicrmw-fadd-global.mir

…

legalize-atomicrmw-fadd-local.mir

…

legalize-atomicrmw-max.mir

…

legalize-atomicrmw-min.mir

…

legalize-atomicrmw-nand.mir

GlobalISel: Replace use of report_fatal_error (#145866)

2025-06-27 21:16:23 +09:00

legalize-atomicrmw-or.mir

…

legalize-atomicrmw-sub.mir

…

legalize-atomicrmw-umax.mir

…

legalize-atomicrmw-umin.mir

…

legalize-atomicrmw-xchg-flat.mir

GlobalISel: Replace use of report_fatal_error (#145866)

2025-06-27 21:16:23 +09:00

legalize-atomicrmw-xchg.mir

…

legalize-atomicrmw-xor.mir

…

legalize-bitcast.mir

…

legalize-bitreverse.mir

…

legalize-block-addr.mir

…

legalize-brcond.mir

[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)

2024-07-28 11:26:29 +04:00

legalize-bswap.mir

…

legalize-build-vector-splat.mir

…

legalize-build-vector-trunc.mir

…

legalize-build-vector.mir

…

legalize-build-vector.s16.mir

…

legalize-concat-vectors.mir

…

legalize-constant.mir

…

legalize-ctlz-zero-undef.mir

[LegalizeDAG] Optimize CodeGen for ISD::CTLZ_ZERO_UNDEF (#83039)

2024-07-08 14:01:32 +01:00

legalize-ctlz.mir

…

legalize-ctpop.mir

…

legalize-cttz-zero-undef.mir

…

legalize-cttz.mir

…

legalize-extract-vector-elt.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-extract.mir

…

legalize-extractelement-crash.mir

…

legalize-fabs.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fadd.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fcanonicalize.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fceil.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fcmp-s32.mir

…

legalize-fcmp.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fconstant.mir

…

legalize-fcopysign.mir

…

legalize-fcos.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fdiv.mir

[AMDGPU] Remove UnsafeFPMath uses (#151079)

2025-07-31 17:36:57 +08:00

legalize-fexp2.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fexp.mir

…

legalize-ffloor.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-flog2.mir

…

legalize-flog10.mir

…

legalize-flog.mir

…

legalize-fma.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fmad.s16.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fmad.s32.mir

…

legalize-fmad.s64.mir

…

legalize-fmaxnum.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fminnum.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fmul.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fneg.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fpext.mir

…

legalize-fpow.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fpowi.mir

…

legalize-fptosi.mir

…

legalize-fptoui.mir

…

legalize-fptrunc.mir

[GlobalISel] Remove UnsafeFPMath references (#146319)

2025-07-29 12:11:52 +08:00

legalize-freeze.mir

Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)

2024-09-25 13:02:29 +02:00

legalize-fshl.mir

[AArch64][GlobalISel] Add disjoint handling for add_and_or_is_add. (#123594)

2025-02-02 21:01:49 +00:00

legalize-fshr.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fsin.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fsqrt.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-fsub.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-icmp.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-implicit-def-s1025.mir

…

legalize-implicit-def.mir

Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)

2024-09-25 13:02:29 +02:00

legalize-insert-vector-elt.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-insert.mir

…

legalize-intrinsic-amdgcn-fdiv-fast.mir

…

legalize-intrinsic-round.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-intrinsic-trunc.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-inttoptr.mir

…

legalize-jump-table.mir

GlobalISel: Replace use of report_fatal_error (#145866)

2025-06-27 21:16:23 +09:00

legalize-llvm.amdgcn.image.atomic.dim.a16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

legalize-llvm.amdgcn.image.dim.a16.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

legalize-llvm.amdgcn.image.load.2d.d16.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

legalize-llvm.amdgcn.image.load.2d.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

legalize-llvm.amdgcn.image.load.2darraymsaa.ll

…

legalize-llvm.amdgcn.image.load.3d.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

legalize-llvm.amdgcn.image.sample.a16.ll

[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)

2024-11-19 15:54:27 +00:00

legalize-llvm.amdgcn.image.sample.d.ll

…

legalize-llvm.amdgcn.image.sample.g16.a16.ll

…

legalize-llvm.amdgcn.image.sample.g16.ll

…

legalize-llvm.amdgcn.image.store.2d.d16.ll

[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)

2024-11-19 15:54:27 +00:00

legalize-llvm.amdgcn.s.buffer.load.mir

…

legalize-load-constant-32bit.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-load-constant.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-load-flat.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-load-global.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-load-local.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-load-memory-metadata.mir

MachineVerifier: Fix check for range type (#124894)

2025-01-30 10:56:12 +07:00

legalize-load-private.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-lshr.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-memcpy.mir

[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)

2025-07-22 00:42:23 -07:00

legalize-memcpyinline.mir

[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)

2025-07-22 00:42:23 -07:00

legalize-memmove.mir

[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)

2025-07-22 00:42:23 -07:00

legalize-memset.mir

[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)

2025-07-22 00:42:23 -07:00

legalize-merge-values-build-vector.mir

…

legalize-merge-values.mir

[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)

2024-12-16 05:57:11 +00:00

legalize-mul.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-or.mir

[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)

2024-12-16 05:57:11 +00:00

legalize-phi.mir

[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)

2024-12-16 05:57:11 +00:00

legalize-ptr-add.mir

…

legalize-ptrmask.mir

…

legalize-ptrtoint.mir

…

legalize-rotl-rotr.mir

…

legalize-sadde.mir

…

legalize-saddo.mir

…

legalize-saddsat.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-sbfx.mir

…

legalize-sdiv.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-select.mir

…

legalize-sext-inreg.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-sext.mir

[AMDGPU][Legalizer] Widen i16 G_SEXT_INREG (#131308)

2025-05-07 10:22:15 +02:00

legalize-sextload-constant-32bit.mir

…

legalize-sextload-flat.mir

…

legalize-sextload-global.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-sextload-local.mir

…

legalize-sextload-private.mir

…

legalize-shl.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-shuffle-vector.mir

…

legalize-shuffle-vector.s16.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-sitofp.mir

…

legalize-smax.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-smin.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-smulh.mir

[GlobalISel] Add computeNumSignBits for ASHR (#139503)

2025-07-21 10:23:26 +01:00

legalize-smulo.mir

…

legalize-srem.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-sshlsat.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-ssube.mir

…

legalize-ssubo.mir

…

legalize-ssubsat.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-store-global.mir

[AMDGPU] Narrow only on store to pow of 2 mem location (#150093)

2025-08-19 00:04:27 +09:00

legalize-store.mir

[AMDGPU] Narrow only on store to pow of 2 mem location (#150093)

2025-08-19 00:04:27 +09:00

legalize-strict_fsub.mir

…

legalize-sub.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-trap-gfx11.mir

…

legalize-trap.mir

…

legalize-trunc.mir

[GlobalISel] Combine unmerge(unmerge()) if the result is legal. (#109606)

2024-09-25 07:04:09 +01:00

legalize-uadde.mir

…

legalize-uaddo.mir

…

legalize-uaddsat.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-ubfx.mir

…

legalize-udiv.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-uitofp.mir

…

legalize-umax.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-umin.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-umulh.mir

…

legalize-umulo.mir

…

legalize-unmerge-values.mir

[AMDGPU][GlobalISel] Fix G_UNMERGE_VALUES combine (#141812)

2025-08-04 17:06:34 -07:00

legalize-urem.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-ushlsat.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-usube.mir

…

legalize-usubo.mir

…

legalize-usubsat.mir

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

legalize-vector-args-gfx7.mir

…

legalize-vector-args-gfx8-plus.mir

…

legalize-xor.mir

[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)

2024-12-16 05:57:11 +00:00

legalize-zext.mir

[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)

2024-12-16 05:57:11 +00:00

legalize-zextload-constant-32bit.mir

…

legalize-zextload-flat.mir

…

legalize-zextload-global.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-zextload-local.mir

…

legalize-zextload-private.mir

…

llvm.abs.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.ballot.i32.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.ballot.i64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.dispatch.ptr.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.div.fmas.ll

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

llvm.amdgcn.div.scale.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.end.cf.i32.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

llvm.amdgcn.end.cf.i64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.fdot2.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.fmul.legacy.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.global.atomic.csub.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.if.break.i32.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

llvm.amdgcn.if.break.i64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.atomic.dim.a16.ll

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

llvm.amdgcn.image.atomic.dim.ll

…

llvm.amdgcn.image.atomic.dim.mir

[AMDGPU][MC] Fix disassembler problem for image_atomic with TFE (#112622)

2024-10-24 16:19:18 -07:00

llvm.amdgcn.image.gather4.a16.dim.ll

[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)

2025-05-08 17:37:08 -04:00

llvm.amdgcn.image.gather4.dim.ll

…

llvm.amdgcn.image.gather4.o.dim.ll

GlobalISel: Replace use of report_fatal_error (#145866)

2025-06-27 21:16:23 +09:00

llvm.amdgcn.image.getresinfo.a16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.getresinfo.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.load.1d.d16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.load.1d.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.load.2d.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.load.2darraymsaa.a16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.load.2darraymsaa.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.load.3d.a16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.load.3d.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.sample.cd.g16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.sample.g16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.image.store.2d.d16.ll

…

llvm.amdgcn.image.store.2d.ll

[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)

2024-10-21 09:39:52 -07:00

llvm.amdgcn.implicit.ptr.buffer.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

llvm.amdgcn.interp.inreg.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.interp.p1.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.intersect_ray.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.kernarg.segment.ptr.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.make.buffer.rsrc.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.mfma.gfx90a.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.mov.dpp.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.queue.ptr.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.buffer.atomic.add.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.raw.buffer.atomic.cmpswap.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.buffer.atomic.fadd.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.buffer.load.format.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.buffer.load.format.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.buffer.load.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.raw.buffer.load.tfe.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.raw.buffer.store.format.f16.ll

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

llvm.amdgcn.raw.buffer.store.format.f32.ll

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

llvm.amdgcn.raw.buffer.store.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.raw.ptr.buffer.atomic.add.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.buffer.load.format.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.buffer.load.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

llvm.amdgcn.raw.ptr.buffer.store.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.tbuffer.load.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.tbuffer.store.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.tbuffer.load.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.tbuffer.load.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.tbuffer.store.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.tbuffer.store.i8.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.tbuffer.store.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.rsq.clamp.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.s.buffer.load.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.s.setreg.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.s.sleep.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.sbfe.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.sdot2.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.sdot4.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.sdot8.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.set.inactive.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.softwqm.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.buffer.atomic.add.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.struct.buffer.atomic.cmpswap.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.buffer.atomic.fadd.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.buffer.load.format.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.buffer.load.format.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.buffer.load.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.struct.buffer.load.tfe.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.struct.buffer.store.format.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.buffer.store.format.f32.ll

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

llvm.amdgcn.struct.buffer.store.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.struct.ptr.buffer.atomic.add.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.buffer.load.format.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.buffer.load.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

llvm.amdgcn.struct.ptr.buffer.store.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.tbuffer.load.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.tbuffer.load.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.tbuffer.load.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.sudot4.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.sudot8.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.trig.preop.ll

[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)

2025-04-15 15:17:33 -07:00

llvm.amdgcn.ubfe.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.udot2.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.udot4.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.udot8.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.update.dpp.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.wmma_32.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.wmma_64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.workgroup.id.ll

Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)

2024-07-15 11:51:44 +04:00

llvm.amdgcn.workitem.id.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.wqm.demote.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.wqm.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.writelane.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.wwm.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.memcpy.inline.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

llvm.memcpy.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.memmove.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.memset.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.powi.ll

[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)

2025-01-06 17:42:38 +05:30

load-constant32bit.ll

…

load-constant.96.ll

…

load-legalize-range-metadata.ll

Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"

2025-05-17 21:41:59 -04:00

load-local.96.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

load-local.128.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

load-unaligned.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

load-uniform-in-vgpr.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for uniform global loads (#145909)

2025-07-23 16:35:19 +02:00

localizer-wrong-insert-point.mir

…

localizer.ll

[AMDGPU] Add identity_combines to RegBankCombiner (#131305)

2025-03-17 10:11:28 +01:00

lshr.ll

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

madmix-constant-bus-violation.ll

Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"

2024-11-08 20:21:16 -05:00

madmix-constant-bus-violation.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

memory-legalizer-atomic-fence.ll

[AMDGPU] introduce S_WAITCNT_LDS_DIRECT in the memory legalizer (#150887)

2025-07-30 11:23:28 +05:30

merge-buffer-stores.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

minmaxabs-i64.ll

[AMDGPU] gfx1250 V_{MIN|MAX}_{I|U}64 opcodes (#151256)

2025-07-29 19:13:51 -07:00

minmaxabs.ll

…

mmra.ll

Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"

2025-05-17 21:41:59 -04:00

mubuf-global.ll

[AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (#135340)

2025-04-22 14:53:55 +02:00

mul-known-bits.i64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

mul-known-bits.i64.mir

…

mul.ll

[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)

2025-08-20 10:26:49 -04:00

mul.v2i16.ll

…

no-cse-nonlocal-convergent-instrs.mir

[CodeGen][NewPM] Port MachineCSE pass to new pass manager. (#106605)

2024-09-04 18:54:07 +05:30

no-ctlz-from-umul-to-lshr-in-postlegalizer.ll

[GlobalISel] Check whether G_CTLZ is legal in matchUMulHToLShr (#126457)

2025-02-10 00:11:09 -05:00

no-ctlz-from-umul-to-lshr-in-postlegalizer.mir

[GlobalISel] Check whether G_CTLZ is legal in matchUMulHToLShr (#126457)

2025-02-10 00:11:09 -05:00

no-legalize-atomic.mir

…

non-entry-alloca.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

or.ll

[GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (#138574)

2025-05-08 19:31:28 +02:00

orn2.ll

[AMDGPU] Remove widen-16-bit-ops from CGP (#145483)

2025-07-16 10:14:19 +02:00

postlegalizer-combiner-buildvector-identities.mir

…

postlegalizer-combiner-divrem.mir

…

postlegalizer-combiner-fcanonicalize.mir

…

postlegalizer-combiner-freeze.mir

…

postlegalizer-combiner-reassoc.mir

…

postlegalizer-combiner-sextload-from-sextinreg.mir

GlobalISel: Fix combine duplicating atomic loads (#111730)

2024-10-31 07:55:12 -07:00

postlegalizer-combiner-trunc-bitcast-buildvector.mir

…

postlegalizer-combiner-unmerge-undef.mir

…

postlegalizer-combiner-zextload-from-and.mir

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

postlegalizercombiner-and.mir

[AMDGPU][GlobalISel] Disable fixed-point iteration in all Combiners (#105517)

2024-08-22 17:14:53 +01:00

postlegalizercombiner-ashr.mir

…

postlegalizercombiner-load-and-mask.mir

…

postlegalizercombiner-lshr.mir

…

postlegalizercombiner-mul.mir

…

postlegalizercombiner-sbfx.mir

[GlobalISel] Add computeNumSignBits for ASHR (#139503)

2025-07-21 10:23:26 +01:00

postlegalizercombiner-select.mir

…

postlegalizercombiner-shl.mir

…

postlegalizercombiner-ubfx.mir

…

prelegalizer-combiner-divrem.mir

AMDGPU: Replace more undef test pointer uses with poison (#131102)

2025-03-14 09:53:45 +07:00

prelegalizer-combiner-fptrunc_fpext.mir

…

prelegalizer-combiner-redundant-bitcast.mir

…

prelegalizer-combiner-sext_inreg-to-and.mir

…

prelegalizer-combiner-shuffle.mir

[GISel] Fix ShuffleVector assert (#139769)

2025-05-20 21:25:31 -04:00

promote-dependency-on-invariant-result.ll

GlobalISel: Fix defined register of invariant.start (#125664)

2025-02-04 23:59:03 +07:00

readanylane-combines.ll

AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)

2025-07-23 16:44:53 +02:00

readanylane-combines.mir

AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)

2025-07-23 16:44:53 +02:00

regbankcombiner-clamp-fmed3-const.mir

…

regbankcombiner-clamp-minmax-const.mir

…

regbankcombiner-fmed3-minmax-const.mir

…

regbankcombiner-redundant-and.mir

AMDGPU/GlobalISel: Run redundant_and combine in RegBankCombiner (#112353)

2024-10-16 09:43:16 +02:00

regbankcombiner-smed3.mir

…

regbankcombiner-umed3.mir

…

regbankselect-abs.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-add.s16.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-add.s32.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-add.v2s16.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn-exp-compr.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn-exp.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn-s-buffer-load.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.ballot.i64.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.class.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.cvt.pkrtz.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.div.fmas.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.div.scale.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.ds.append.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.ds.bpermute.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.ds.consume.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.ds.gws.init.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.ds.gws.sema.v.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.ds.ordered.add.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.ds.ordered.swap.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.ds.permute.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.ds.swizzle.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.else.32.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.else.64.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.fcmp.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.fmul.legacy.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.groupstaticsize.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.icmp.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.image.load.1d.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

regbankselect-amdgcn.image.sample.1d.ll

AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)

2025-03-13 08:25:02 +07:00

regbankselect-amdgcn.interp.mov.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.interp.p1.f16.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.interp.p1.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.interp.p2.f16.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.interp.p2.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.kernarg.segment.ptr.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.kill.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.lds.direct.load.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.lds.param.load.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.live.mask.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.mfma.gfx90a.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.mfma.gfx942.mir

[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)

2025-02-13 15:17:12 +01:00

regbankselect-amdgcn.mfma.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.ps.live.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.raw.buffer.load.ll

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

regbankselect-amdgcn.raw.ptr.buffer.load.ll

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

regbankselect-amdgcn.readfirstlane.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-amdgcn.readlane.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.s.buffer.load.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

regbankselect-amdgcn.s.buffer.load.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.s.get.waveid.in.workgroup.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.s.getpc.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-amdgcn.s.getreg.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.s.memrealtime.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.s.memtime.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.s.sendmsg.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.s.sendmsghalt.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.struct.buffer.load.ll

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

regbankselect-amdgcn.struct.buffer.store.ll

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.struct.ptr.buffer.load.ll

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

regbankselect-amdgcn.struct.ptr.buffer.store.ll

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.update.dpp.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.wqm.demote.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.wqm.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.wqm.vote.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgcn.writelane.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-amdgcn.wwm.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgpu-ffbh-u32.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgpu-ffbl-b32.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-amdgpu-wave-address.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-and-s1.mir

AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)

2025-07-23 16:44:53 +02:00

regbankselect-and.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (#132382)

2025-05-26 12:07:46 +02:00

regbankselect-anyext.mir

AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)

2025-07-23 16:44:53 +02:00

regbankselect-ashr.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

regbankselect-assert-align.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-assert-zext.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomic-cmpxchg.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-add.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-and.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-fadd.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-max.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-min.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-or.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-sub.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-umax.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-umin.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-xchg.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-atomicrmw-xor.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-bitcast.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-bitreverse.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-block-addr.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-brcond.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-bswap.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-build-vector.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-concat-vector.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-constant.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-copy.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-ctlz-zero-undef.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-ctpop.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-cttz-zero-undef.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-default.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-dyn-stackalloc.mir

[AMDGPU] Support divergent sized dynamic alloca (#121148)

2025-01-06 12:28:24 +07:00

regbankselect-extract-vector-elt.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-extract.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fabs.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fadd.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-fcanonicalize.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fceil.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fcmp.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fexp2.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-flog2.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fma.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fmul.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fneg.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fpext.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fptosi.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fptoui.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fptrunc.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-frame-index.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-freeze.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fshr.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fsqrt.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-fsub.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-icmp.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-icmp.s16.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-illegal-copy.mir

GlobalISel: Replace use of report_fatal_error (#145866)

2025-06-27 21:16:23 +09:00

regbankselect-implicit-def.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-insert-vector-elt.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-insert.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-intrinsic-trunc.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-inttoptr.mir

[AMDGPU] New RegBankSelect: Add rules for G_PTRTOINT and G_INTTOPTR (#142604)

2025-06-19 10:21:17 +02:00

regbankselect-load.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

regbankselect-lshr.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

regbankselect-mad_64_32.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-merge-values.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-mui-regbanklegalize.mir

MachineUniformityAnalysis: Improve isConstantOrUndefValuePhi (#112866)

2025-01-24 12:43:40 +01:00

regbankselect-mui-regbankselect.mir

AMDGPU/GlobalISel: Disable LCSSA pass (#124297)

2025-03-12 11:09:50 +01:00

regbankselect-mui-salu-float.ll

AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)

2025-01-24 12:12:45 +01:00

regbankselect-mui-salu-float.mir

AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)

2025-01-24 12:12:45 +01:00

regbankselect-mui.ll

[AMDGPU] Add identity_combines to RegBankCombiner (#131305)

2025-03-17 10:11:28 +01:00

regbankselect-mui.mir

AMDGPU/GlobalISel: Disable LCSSA pass (#124297)

2025-03-12 11:09:50 +01:00

regbankselect-mul.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-or.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (#132382)

2025-05-26 12:07:46 +02:00

regbankselect-phi-s1.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-phi.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-pseudo-scalar-transcendental.mir

…

regbankselect-ptr-add.mir

AMDGPU/GlobalISel: Add regbanklegalize rules for ptr-add (#153175)

2025-08-13 15:49:48 +02:00

regbankselect-ptrmask.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-ptrtoint.mir

[AMDGPU] New RegBankSelect: Add rules for G_PTRTOINT and G_INTTOPTR (#142604)

2025-06-19 10:21:17 +02:00

regbankselect-reg-sequence.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-sadde.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-salu-float.mir

…

regbankselect-sbfx.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)

2025-05-26 11:58:57 +02:00

regbankselect-select.mir

[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule (#142560)

2025-06-19 09:56:07 +02:00

regbankselect-sext-inreg.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

regbankselect-sext.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (#132383)

2025-05-26 12:10:54 +02:00

regbankselect-sextload.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-shl.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

regbankselect-sitofp.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-smax.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-smin.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-smulh.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-split-scalar-load-metadata.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-ssube.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-sub.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-trunc.mir

AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)

2025-07-23 16:44:53 +02:00

regbankselect-uadde.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-uaddo.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-ubfx.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)

2025-05-26 11:58:57 +02:00

regbankselect-uitofp.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-umax.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-umin.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-umulh.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-uniform-load-noclobber.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

regbankselect-unmerge-values.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-usube.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-usubo.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-waterfall-agpr.mir

[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)

2025-02-26 13:14:03 +01:00

regbankselect-whole-wave-functions.mir

[AMDGPU] ISel & PEI for whole wave functions (#145858)

2025-07-21 10:39:09 +02:00

regbankselect-widen-scalar-loads.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

regbankselect-xor.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (#132382)

2025-05-26 12:07:46 +02:00

regbankselect-zext.mir

AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (#132383)

2025-05-26 12:10:54 +02:00

regbankselect-zextload.mir

AMDGPU/GlobalISel: RegBankLegalize rules for load (#112882)

2025-01-24 12:36:41 +01:00

regbankselect.mir

Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)

2024-11-27 13:16:22 -05:00

saddsat.ll

MachineScheduler: Reset next cluster candidate for each node (#139513)

2025-05-28 14:53:46 +08:00

sbfx.ll

AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)

2025-05-26 11:58:57 +02:00

sdiv.i32.ll

[GlobaISel] Allow expanding of sdiv -> mul by constant (#146504)

2025-07-14 15:01:12 +01:00

sdiv.i64.ll

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

sdivrem.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

select-to-fmin-fmax.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

selected-inst-flags.mir

[GlobalISel] Fix silently dropped MIFlags on selected instructions (#138851)

2025-05-07 14:07:16 +02:00

sext_inreg.ll

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

shader-epilogs.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

shl-ext-reduce.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

shl.ll

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

shlN_add.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

shufflevector-pointer-crash.mir

[GlobalISel] support lowering of G_SHUFFLEVECTOR with pointer args (#141959)

2025-06-05 09:13:51 -07:00

shufflevector.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

smed3.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

smrd.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

srem.i32.ll

[GlobalISel] Allow expansion of srem by constant in prelegalizer (#148845)

2025-07-17 14:43:58 +01:00

srem.i64.ll

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

ssubsat.ll

MachineScheduler: Reset next cluster candidate for each node (#139513)

2025-05-28 14:53:46 +08:00

store-local.96.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

store-local.128.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

store-weird-size.ll

[AMDGPU] Narrow only on store to pow of 2 mem location (#150093)

2025-08-19 00:04:27 +09:00

strict_fma.f16.ll

…

strict_fma.f32.ll

…

strict_fma.f64.ll

…

sub.v2i16.ll

[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)

2025-05-16 10:31:03 +02:00

subo.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

trunc.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

twoaddr-extract-dyn-v7f64.mir

[llc] Provide opt like verifier options (#106665)

2024-09-04 17:37:34 +08:00

uaddsat.ll

[AMDGPU] Account for existing SDWA selections (#123221)

2025-03-03 17:07:28 +01:00

ubfx.ll

AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)

2025-05-26 11:58:57 +02:00

udiv.i32.ll

…

udiv.i64.ll

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

udivrem.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

umed3.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

unsupported-load.ll

GlobalISel: Replace use of report_fatal_error (#145866)

2025-06-27 21:16:23 +09:00

unsupported-ptr-add.ll

GlobalISel: Replace use of report_fatal_error (#145866)

2025-06-27 21:16:23 +09:00

urem.i32.ll

[GlobalISel] Allow expansion of urem by constant in prelegalizer (#145914)

2025-07-02 13:46:36 +01:00

urem.i64.ll

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

usubsat.ll

[AMDGPU] Account for existing SDWA selections (#123221)

2025-03-03 17:07:28 +01:00

v_bfe_i32.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

vni8-across-blocks.ll

Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"

2024-11-08 20:21:16 -05:00

widen-i8-i16-scalar-loads.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

wmma-gfx12-w32-f16-f32-matrix-modifiers.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

wmma-gfx12-w32-imm.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

wmma-gfx12-w32-iu-modifiers.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

wmma-gfx12-w32-swmmac-index_key.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

wmma-gfx12-w32.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

wmma-gfx12-w64-f16-f32-matrix-modifiers.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

wmma-gfx12-w64-imm.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

wmma-gfx12-w64-iu-modifiers.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

wmma-gfx12-w64-swmmac-index_key.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

wmma-gfx12-w64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

xnor.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

xor.ll

[GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (#138574)

2025-05-08 19:31:28 +02:00

zextload.ll

…