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llvm-project/llvm/lib/Target/RISCV
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Craig Topper defbbf0129
[RISCV][MoveMerge] Don't copy kill flag when moving past an instruction that reads the register. (#153644) 
If we're moving the second copy before another instruction that reads
the copied register, we need to clear the kill flag on the combined
move.

Fixes #153598.
2025-08-14 14:52:54 -07:00
..
AsmParser
[RISCV] Handle 'c.addi x0, $imm' alias for c.nop using PseudoC_ADDI_NOP. (#150719)
2025-07-25 20:55:52 -07:00
Disassembler
[RISCV] Move the decoder table for XCV, Xqci and XRivos from standard section to vendor section. NFC
2025-08-08 11:18:18 +08:00
GISel
[CodeGen] Move IsFixed into ArgFlags (NFCI) (#152319)
2025-08-07 09:12:40 +02:00
MCA
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
MCTargetDesc
[RISCV] Track Linker Relaxable through Assembly Relaxation (#152602)
2025-08-12 09:02:48 +01:00
TargetInfo
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
CMakeLists.txt
[RISCV][NFC] Split InterleavedAccess related TLI hooks into a separate file (#148040)
2025-07-11 11:04:41 -07:00
RISCV.h
…
RISCV.td
[RISCV] Implement base scheduling model for andes 45 series processor. (#141008)
2025-06-04 16:11:43 +08:00
RISCVAsmPrinter.cpp
[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructions. (#150710)
2025-07-25 20:55:15 -07:00
RISCVCallingConv.cpp
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.h
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.td
[RISCV] Support PreserveMost calling convention (#148214)
2025-07-30 16:30:48 +08:00
RISCVCodeGenPrepare.cpp
…
RISCVCombine.td
…
RISCVConstantPoolValue.cpp
…
RISCVConstantPoolValue.h
…
RISCVDeadRegisterDefinitions.cpp
[RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0,x0 vsetvli. NFC (#141875)
2025-05-29 10:21:38 -07:00
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Add nds.bfos and nds.bfoz for the short forward branch optimization. (#145836)
2025-06-27 10:54:41 +08:00
RISCVFeatures.td
[RISCV] add load/store misched/PostRA subtarget features (#149409)
2025-08-06 09:08:25 -07:00
RISCVFoldMemOffset.cpp
…
RISCVFrameLowering.cpp
[llvm] Use a range-based for loop instead of {std,llvm}::for_each (NFC) (#150841)
2025-07-27 10:43:52 -07:00
RISCVFrameLowering.h
[RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531)
2025-07-15 08:09:18 -07:00
RISCVGatherScatterLowering.cpp
[RISCV] Create disjoint or in RISCVGatherScatterLowering (#151981)
2025-08-05 12:19:10 +08:00
RISCVGISel.td
…
RISCVIndirectBranchTracking.cpp
[RISCV] Make RISCVIndirectBranchTracking visible in debug output (#141623)
2025-05-28 14:56:44 +08:00
RISCVInsertReadWriteCSR.cpp
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RISCVInsertVSETVLI.cpp
[RISCV] Don't increase vslide or splat vl if +vl-dependent-latency is present (#147089)
2025-07-09 16:25:22 +08:00
RISCVInsertWriteVXRM.cpp
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RISCVInstrFormats.td
[RISCV] Fix VLOptimizer assert, relax ElementsDependOn on viota/vms{b,i,o}f.m (#149698)
2025-07-21 14:51:41 +08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
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RISCVInstrGISel.td
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RISCVInstrInfo.cpp
Revert "[X86][ARM][RISCV][XCore][M68K] Invert the low bit to get the inverse predicate (NFC) (#151748)"
2025-08-04 15:24:52 -07:00
RISCVInstrInfo.h
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVInstrInfo.td
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
RISCVInstrInfoA.td
…
RISCVInstrInfoC.td
[RISCV] Accept c.slli/c.srli/c.srli with a 0 immediate as hints. (#150689)
2025-07-26 00:05:33 -07:00
RISCVInstrInfoD.td
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
RISCVInstrInfoF.td
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
RISCVInstrInfoM.td
…
RISCVInstrInfoP.td
[RISCV] Add MC support for P extensions with scalar second operands. (#153502)
2025-08-14 07:03:36 -07:00
RISCVInstrInfoQ.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVInstrInfoSFB.td
…
RISCVInstrInfoV.td
[RISCV] Fix VLOptimizer assert, relax ElementsDependOn on viota/vms{b,i,o}f.m (#149698)
2025-07-21 14:51:41 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove unused vector pseudo class. NFC (#151327)
2025-07-31 10:14:36 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Use (i64 GPR:$rs1) instead of i64:$rs1 in isel patterns.
2025-08-01 09:44:09 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Use (i64 GPR:$rs1) instead of i64:$rs1 in isel patterns.
2025-08-01 09:44:09 -07:00
RISCVInstrInfoXAndes.td
[RISCV] Implement load/store support for XAndesBFHCvt (#150350)
2025-07-25 11:29:17 +08:00
RISCVInstrInfoXCV.td
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVInstrInfoXMips.td
[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)
2025-07-03 10:59:10 +02:00
RISCVInstrInfoXqccmp.td
…
RISCVInstrInfoXqci.td
[RISCV] Add Tied operands to insert instructions in Qualcomm uC extension Xqcibm (#151339)
2025-08-05 15:02:19 +05:30
RISCVInstrInfoXRivos.td
[RISCV] Make RISCVVPseudo extend Pseudo. NFC (#149785)
2025-07-23 16:29:12 +08:00
RISCVInstrInfoXSf.td
[RISCV] Make RISCVVPseudo extend Pseudo. NFC (#149785)
2025-07-23 16:29:12 +08:00
RISCVInstrInfoXSfmm.td
[RISCV] Add MC layer support for XSfmm*. (#133031)
2025-05-21 08:26:35 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Use (i64 GPR:$rs1) instead of i64:$rs1 in isel patterns.
2025-08-01 09:44:09 -07:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
…
RISCVInstrInfoZa.td
…
RISCVInstrInfoZalasr.td
…
RISCVInstrInfoZb.td
[RISCV] Add a high half PACKW+PACK pattern for RV64. (#152760)
2025-08-11 07:37:55 -05:00
RISCVInstrInfoZc.td
[RISCV] Remove extra operands from Zcb compression patterns. NFC (#150541)
2025-07-24 18:03:30 -07:00
RISCVInstrInfoZclsd.td
…
RISCVInstrInfoZcmop.td
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RISCVInstrInfoZfa.td
[RISCV] Fix schedule info for FMVP_D_X. (#140766)
2025-05-22 08:39:57 -07:00
RISCVInstrInfoZfbfmin.td
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RISCVInstrInfoZfh.td
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RISCVInstrInfoZicbo.td
[RISCV] Change the InstFormat for Zicbop prefetch instructions to InstFormatOther. (#148934)
2025-07-15 14:49:54 -07:00
RISCVInstrInfoZicfiss.td
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RISCVInstrInfoZicond.td
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RISCVInstrInfoZilsd.td
[RISCV] Lower i64 load/stores to ld/sd with Zilsd. (#139808)
2025-05-14 09:54:07 -07:00
RISCVInstrInfoZimop.td
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RISCVInstrInfoZk.td
…
RISCVInstrInfoZvfbf.td
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RISCVInstrInfoZvk.td
[RISCV] Remove duplicate vsha2ch/vsha2cl/vsha2ms i32 patterns. NFC (#151835)
2025-08-02 21:53:58 -07:00
RISCVInstrInfoZvqdotq.td
[RISCV] Fix schedule info for Zqvdotq (#142717)
2025-06-05 12:22:43 +08:00
RISCVInstrPredicates.td
[RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions (#145147)
2025-07-03 12:47:53 +08:00
RISCVInterleavedAccess.cpp
[IA][RISCV] Recognize deinterleaved loads that could lower to strided segmented loads (#151612)
2025-08-12 14:08:18 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Add CodeGen support for qc.insbi and qc.insb insert instructions (#152447)
2025-08-14 12:08:28 +05:30
RISCVISelDAGToDAG.h
[RISCV] Add CodeGen support for qc.insbi and qc.insb insert instructions (#152447)
2025-08-14 12:08:28 +05:30
RISCVISelLowering.cpp
[CodeGen] Remove unnecessary setTypeListBeforeSoften() parameter (NFC)
2025-08-14 10:04:56 +02:00
RISCVISelLowering.h
[IA][RISCV] Recognize deinterleaved loads that could lower to strided segmented loads (#151612)
2025-08-12 14:08:18 -07:00
RISCVLandingPadSetup.cpp
…
RISCVLateBranchOpt.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVLoadStoreOptimizer.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVMachineFunctionInfo.cpp
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RISCVMachineFunctionInfo.h
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RISCVMacroFusion.td
[RISCV] add more generic macrofusions (#151140)
2025-08-06 14:46:34 -04:00
RISCVMakeCompressible.cpp
[RISCV][NFC] Remove hasStdExtCOrZca (#145139)
2025-06-23 10:49:47 -07:00
RISCVMergeBaseOffset.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVMoveMerger.cpp
[RISCV][MoveMerge] Don't copy kill flag when moving past an instruction that reads the register. (#153644)
2025-08-14 14:52:54 -07:00
RISCVOptWInstrs.cpp
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
RISCVPfmCounters.td
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RISCVPostRAExpandPseudoInsts.cpp
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RISCVProcessors.td
[RISCV] add more generic macrofusions (#151140)
2025-08-06 14:46:34 -04:00
RISCVProfiles.td
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RISCVPushPopOptimizer.cpp
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RISCVRedundantCopyElimination.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVRegisterInfo.cpp
[RISCV] Fix a warning
2025-07-30 09:43:57 -07:00
RISCVRegisterInfo.h
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RISCVRegisterInfo.td
[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructions. (#150710)
2025-07-25 20:55:15 -07:00
RISCVSchedAndes45.td
[RISCV] Fix typo in comment Interger->Integer. NFC
2025-08-13 11:19:49 -07:00
RISCVSchedGenericOOO.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedMIPSP8700.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedRocket.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFive7.td
[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)
2025-07-09 09:38:44 -07:00
RISCVSchedSiFiveP400.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP500.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP600.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP800.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSpacemitX60.td
[RISCV] Update SpacemiT-X60 vector fixed-point arithmetic latencies (#150517)
2025-08-08 11:57:35 -03:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedTTAscalonD8.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedule.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVScheduleV.td
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RISCVScheduleXSf.td
[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)
2025-07-09 09:38:44 -07:00
RISCVScheduleZb.td
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RISCVScheduleZvk.td
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RISCVSchedXiangShanNanHu.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSelectionDAGInfo.cpp
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555)
2025-08-04 12:51:14 +05:30
RISCVSelectionDAGInfo.h
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555)
2025-08-04 12:51:14 +05:30
RISCVSubtarget.cpp
[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy (#149297)
2025-07-22 15:55:12 +08:00
RISCVSubtarget.h
[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy (#149297)
2025-07-22 15:55:12 +08:00
RISCVSystemOperands.td
[RISCV] Sort RISCVSystemOperands to match the RISC-V Privilege Specification. (#140967)
2025-05-22 08:46:48 -07:00
RISCVTargetMachine.cpp
[RISCV] add load/store misched/PostRA subtarget features (#149409)
2025-08-06 09:08:25 -07:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetObjectFile.h
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetTransformInfo.cpp
[RISCV] Cost casts with illegal types that can't be legalized (#153030)
2025-08-12 00:29:39 +08:00
RISCVTargetTransformInfo.h
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
RISCVVectorMaskDAGMutation.cpp
Reland "[RISCV] AddEdge between mask producer and user of V0 (#146855)" (#148566)
2025-07-18 10:56:07 +08:00
RISCVVectorPeephole.cpp
[RISCV] Fold vmv.v.v into vmerge (#151341)
2025-07-31 10:15:12 +08:00
RISCVVLOptimizer.cpp
[RISCV][VLOPT] Added support for the zvbc and the remaining zvbb instructions (#153234)
2025-08-13 14:43:25 +00:00
RISCVVMV0Elimination.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVZacasABIFix.cpp
…