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llvm-project/llvm/test/CodeGen/RISCV
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Philip Reames c2c7b7efab [RISCV] Add coverage for the tryFoldSelectIntoOp combine with constants 
An upcoming change will relax the requirement that the operands be
non-constant.
2025-09-07 17:01:26 -07:00
..
GlobalISel
[RISCV][GISel] Lower G_ABDS and G_ABDU (#155888)
2025-09-05 21:16:35 +08:00
intrinsics
…
rvv
[RISCV] Check for legal type before calling getSimpleValueType() in matchSplatAsGather. (#157188)
2025-09-05 22:00:38 -07:00
abds-neg.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
abds.ll
[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDValue with just the frozen node (#150017)
2025-08-05 09:24:09 +01:00
abdu-neg.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
abdu.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
add_sext_shl_constant.ll
[RISCV] Don't commute with shift if XAndesPerf is enabled (#142920)
2025-06-06 11:08:23 +08:00
add_shl_constant.ll
[RISCV] Don't commute with shift if XAndesPerf is enabled (#142920)
2025-06-06 11:08:23 +08:00
add-before-shl.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
add-imm64-to-sub.ll
[RISCV] Handle more (add x, C) -> (sub x, -C) cases (#138705)
2025-05-13 09:12:24 +02:00
add-imm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
addc-adde-sube-subc.ll
…
addcarry.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
addimm-mulimm.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
addrspacecast.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
aext-to-sext.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
aext.ll
…
align-loops.ll
…
align.ll
…
alloca.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
allow-check.ll
…
alu8.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
alu16.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
alu32.ll
…
alu64.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
analyze-branch.ll
…
and-add-lsr.ll
…
and-negpow2-cmp.ll
[RISCV] Fold (X & (7 << 29)) == 0 -> (srliw X, 29) == 0 for RV64. (#156769)
2025-09-03 22:16:05 -07:00
and-shl.ll
[RISCV] Remove artificial restriction on ShAmt from (shl (and X, C2), C) -> (srli (slli X, C4), C4-C) isel. (#143010)
2025-06-05 17:48:35 -07:00
and.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
arith-with-overflow.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
atomic-cmpxchg-branch-on-result.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomic-fence.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
atomic-load-store.ll
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
2024-12-17 00:19:45 -08:00
atomic-load-zext.ll
[RISCV] Remove AND mask generated by ( zext ( atomic_load ) ) by replacing the load with zextload for orderings not stronger then monotonic. (#136502)
2025-04-28 08:35:51 -07:00
atomic-rmw-discard.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
atomic-rmw-sub.ll
…
atomic-rmw.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
atomic-signext.ll
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
atomicrmw-cond-sub-clamp.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
atomicrmw-uinc-udec-wrap.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
attributes-andes.ll
[RISCV] Split the attribute test for Andes to attributes-andes.ll. NFC.
2025-09-02 09:01:55 +08:00
attributes-module-flag.ll
[RISCV] Make M imply Zmmul (#95070)
2024-06-21 11:11:10 +08:00
attributes-qc.ll
[RISCV] Split the attribute test for Qualcomm to attributes-qc.ll. NFC.
2025-09-02 09:01:55 +08:00
attributes-sifive.ll
[RISCV] Split the attribute test for xsfvfwmaccqqq to attributes-sifive.ll. NFC. (#155973)
2025-08-29 05:40:51 +00:00
attributes-thead.ll
[RISCV] Split the attribute test for THead to attributes-thead.ll. NFC.
2025-09-01 13:14:27 +08:00
attributes.ll
[RISCV] Split the attribute test for Qualcomm to attributes-qc.ll. NFC.
2025-09-02 09:01:55 +08:00
avgceils.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
avgceilu.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
avgfloors.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
avgflooru.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
bf16-promote.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bfloat-arith.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
bfloat-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
bfloat-convert.ll
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
bfloat-fcmp.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
bfloat-frem.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-imm.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-isnan.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bfloat-select-fcmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
bfloat-select-icmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
bfloat.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bitextract-mac.ll
[RISCV] Add th.ext(u) to RISCVDAGToDAGISel::hasAllNBitUsers. (#157133)
2025-09-05 11:57:26 -07:00
bitreverse-shift.ll
…
bittest.ll
[RISCV] Fold (X & (7 << 29)) == 0 -> (srliw X, 29) == 0 for RV64. (#156769)
2025-09-03 22:16:05 -07:00
blockaddress.ll
…
branch_zero.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
branch-on-zero.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
branch-opt.ll
…
branch-opt.mir
[RISCV] Fix a correctness issue in optimizeCondBranch. Prevent optimizing compare with x0. NFC (#145440)
2025-06-24 15:45:06 -07:00
branch-relaxation-rv32.ll
[RISCV][NFC] Split branch-relaxation test
2024-11-12 09:35:16 -08:00
branch-relaxation-rv32e.ll
[RISCV] Use X9 instead of X27 in RISCVInstrInfo::insertIndirectBranch for RVE (#139214)
2025-05-09 08:41:14 -07:00
branch-relaxation-rv64.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
branch.ll
[CodeGen] Limit number of analyzed predecessors
2025-06-20 11:23:00 +02:00
bswap-bitreverse.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
bswap-shift.ll
[RISCV] Remove the TODO for folding bswap and shift from the test. (NFC) (#129972)
2025-03-06 13:02:17 +08:00
byval.ll
…
callee-saved-fpr32s.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
callee-saved-fpr64s.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
callee-saved-gprs.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
calleetypeid-directcall-mismatched.ll
[llvm] Extract and propagate callee_type metadata
2025-07-30 14:56:39 -07:00
calling-conv-half.ll
[RISCV] Add exhausted_gprs_fprs test to calling-conv-half.ll. NFC (#156586)
2025-09-03 16:17:34 -07:00
calling-conv-ilp32-ilp32f-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-ilp32.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32d.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32e.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-ilp32f-ilp32d-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64-lp64f-common.ll
…
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
calling-conv-lp64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-preserve-most.ll
[RISCV] Support PreserveMost calling convention (#148214)
2025-07-30 16:30:48 +08:00
calling-conv-rv32f-ilp32.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-rv32f-ilp32e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-sext-zext.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-vector-float.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-vector-on-stack.ll
…
calls.ll
[RISCV][GISel] Use the correct calling convention during call lowering (#142148)
2025-05-30 18:55:32 +02:00
callsite-emit-calleetypeid-tailcall.ll
[llvm] Extract and propagate callee_type metadata
2025-07-30 14:56:39 -07:00
callsite-emit-calleetypeid.ll
[llvm] Extract and propagate callee_type metadata
2025-07-30 14:56:39 -07:00
clear-cache.ll
[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets (#93481)
2024-06-20 07:27:07 +02:00
cm_mvas_mvsa.ll
…
cm_mvas_mvsa.mir
…
cmov-branch-opt.ll
[RISCV] Reorganize select lowering to pull binop expansion early (#156974)
2025-09-05 18:13:53 -07:00
cmp-bool.ll
…
codemodel-lowering.ll
[RISCV] Use QC_E_LI to materialise addresses (#155819)
2025-09-05 12:58:28 +05:30
combine-storetomstore.ll
[DAG] Combine store + vselect to masked_store (#145176)
2025-08-04 19:05:36 +05:30
compress-double.ll
…
compress-float.ll
…
compress-inline-asm.ll
…
compress-opt-branch.ll
…
compress-opt-select.ll
[llc] Add -M for InstPrinter options
2025-04-08 19:34:03 -07:00
compress.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
condbinops.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
condops.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
constpool-known-bits.ll
Re-commit "[RISCV] Properly support RISCVISD::LLA in getTargetConstantFromLoad. (#145112)"
2025-06-21 10:18:49 -07:00
convert-highly-predictable-select-to-branch.ll
[RISCV] Rename some Feature* to Tune* (#117966)
2024-11-28 15:01:49 +08:00
copy-frameindex.mir
…
copyprop.ll
…
copysign-casts.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
csr-first-use-cost.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
ctlz-cttz-ctpop.ll
[RISCV] Add th.ext(u) to RISCVDAGToDAGISel::hasAllNBitUsers. (#157133)
2025-09-05 11:57:26 -07:00
ctz_zero_return_test.ll
[RISCV] Fix incorrect folding of select on ctlz/cttz (#155231)
2025-09-03 09:13:54 +08:00
debug-line.ll
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
di-assignment-tracking-vector.ll
[DebugInfo] Handle additional types of stores in assignment tracking (#129070)
2025-04-22 17:14:25 +01:00
disable-tail-calls.ll
…
disjoint.ll
…
div_minsize.ll
…
div-by-constant.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
div-pow2.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
div.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
double_reduct.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
double-arith-strict.ll
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2025-05-27 21:52:20 -07:00
double-arith.ll
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2025-05-27 21:52:20 -07:00
double-bitmanip-dagcombines.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
double-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
double-calling-conv.ll
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
double-convert-strict.ll
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
double-convert.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
double-fcmp-strict.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
double-fcmp.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
double-frem.ll
…
double-imm.ll
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2025-05-27 21:52:20 -07:00
double-intrinsics-strict.ll
[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC
2024-11-27 10:24:34 -08:00
double-intrinsics.ll
[RISCV] Remove the TODO for fmaximum/fminimum from the tests. (NFC) (#129969)
2025-03-06 13:01:58 +08:00
double-isnan.ll
…
double-maximum-minimum.ll
[RISCV] Remove unused check prefixes from double maximum/minimum test. NFC
2025-03-17 16:39:51 +08:00
double-mem.ll
[RISCV] Add X0_Pair to RISCVDeadRegisterDefinitions. (#141831)
2025-05-28 14:59:28 -07:00
double-previous-failure.ll
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
double-round-conv-sat.ll
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2025-05-27 21:52:20 -07:00
double-round-conv.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
double-select-fcmp.ll
[RISCV] Move CascadeSelect test into float/half/double-select-fcmp.ll. NFC
2025-06-26 09:46:14 -07:00
double-select-icmp.ll
…
double-stack-spill-restore.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-zfa.ll
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
dso_local_equivalent.ll
AsmPrinter: Remove ELF's special lowerRelativeReference for unnamed_addr function; use lowerDSOLocalEquivalent in more cases
2025-04-08 10:11:20 -07:00
dwarf-eh.ll
[TargetLoweringObjectFile] Handle riscv BE (#155166)
2025-08-28 17:04:47 +02:00
early-clobber-tied-def-subreg-liveness.ll
[RISCV] Optimize the spill/reload of segment registers (#153184)
2025-08-21 16:38:53 +08:00
eh-dwarf-cfa.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
elf-preemption.ll
…
emit-x8-as-fp.ll
[RISCV][MC] Emit x8 as fp instead of s0 (#135500)
2025-04-14 14:48:47 +08:00
emutls.ll
…
exception-pointer-register.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
fastcc-bf16.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-float.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-half.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-int.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
fastcc-without-f-reg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
features-info.ll
[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (#155747)
2025-09-01 10:40:28 +02:00
fixed-csr.ll
[RISCV][MRI] Account for fixed registers when determining callee saved regs (#115756)
2024-12-06 14:07:27 -05:00
fixups-diff.ll
…
fli-licm.ll
…
float-arith-strict.ll
…
float-arith.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
float-bit-preserving-dagcombines.ll
…
float-bitmanip-dagcombines.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
float-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
float-convert-strict.ll
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
float-convert.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
float-fcmp-strict.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
float-fcmp.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
float-frem.ll
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
float-imm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
float-intrinsics-strict.ll
[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC
2024-11-27 10:24:34 -08:00
float-intrinsics.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
float-isnan.ll
…
float-maximum-minimum.ll
[LegalizeTypes] Support softening FMINIMUM/FMAXIMUM (#115463)
2024-11-09 10:02:06 +00:00
float-mem.ll
…
float-round-conv-sat.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
float-round-conv.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
float-select-fcmp.ll
[RISCV] Move CascadeSelect test into float/half/double-select-fcmp.ll. NFC
2025-06-26 09:46:14 -07:00
float-select-icmp.ll
…
float-select-verify.ll
…
float-zfa.ll
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
flt-rounds.ll
…
fmax-fmin.ll
…
fold-addi-loadstore-zilsd.ll
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2025-05-27 21:52:20 -07:00
fold-addi-loadstore.ll
[RISCV] Use QC_E_LI to materialise addresses (#155819)
2025-09-05 12:58:28 +05:30
fold-binop-into-select-return-constant.ll
[RISCV] Add a check in lowerSELECT after foldBinOpIntoSelectIfProfitable (#97391)
2024-07-05 10:55:36 +08:00
fold-binop-into-select.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
fold-masked-merge.ll
Reland "[SelectionDAG] Make (a & x) | (~a & y) -> (a & (x ^ y)) ^ y available for all targets" (#143651)
2025-06-11 15:56:37 +08:00
fold-mem-offset.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
fold-mem-offset.mir
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
2025-04-22 19:24:29 -07:00
forced-atomics.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
fp16-promote.ll
…
fp128.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fp-fcanonicalize.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fpclamptosat.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
fpenv-xlen.ll
[RISCV][FPEnv] Lowering of fpmode intrinsics (#148569)
2025-07-16 16:02:15 +07:00
fpenv.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
frame-info.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
frame.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
frameaddr-returnaddr.ll
…
frm-dependency.ll
[RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). (#133200)
2025-03-27 07:45:42 -07:00
frm-write-in-loop.ll
[RISCV][FPEnv] Lowering of fpenv intrinsics (#141498)
2025-06-11 19:08:23 +07:00
get-register-invalid.ll
CodeGen: Emit error if getRegisterByName fails (#145194)
2025-06-23 16:33:35 +09:00
get-register-noreserve.ll
…
get-register-reserve.ll
[RISCV] Mark More Fatal Errors as Usage/Internal (#154876)
2025-08-22 11:57:17 -07:00
get-setcc-result-type.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
ghccc-nest.ll
…
ghccc-rv32.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
ghccc-rv64.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
ghccc-without-f-reg.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
global-merge-minsize-smalldata-nonzero.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-minsize-smalldata-zero.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-minsize.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-offset.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
graalcc.ll
…
half-arith-strict.ll
[RISCV] Remove unused check prefixes from half arith strict test. NFC
2025-03-17 12:51:39 +08:00
half-arith.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
half-bitmanip-dagcombines.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
half-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
half-convert-strict.ll
[RISCV] Add more common check prefixes to reduce the lines in half-convert-strict.ll. NFC.
2025-08-25 13:57:11 +08:00
half-convert.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
half-fcmp-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-fcmp.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
half-frem.ll
…
half-imm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
half-intrinsics.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
half-isnan.ll
…
half-maximum-minimum.ll
…
half-mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-round-conv-sat.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
half-round-conv.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
half-select-fcmp.ll
[RISCV] Move CascadeSelect test into float/half/double-select-fcmp.ll. NFC
2025-06-26 09:46:14 -07:00
half-select-icmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
half-zfa-fli.ll
…
half-zfa.ll
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
hoist-global-addr-base.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
hwasan-check-memaccess.ll
[llc] Add -M for InstPrinter options
2025-04-08 19:34:03 -07:00
i32-icmp.ll
[RISCV] Lower (setugt X, 2047) as (setne (srl X, 11), 0) (#155541)
2025-08-26 23:05:41 -07:00
i64-icmp.ll
[RISCV] Lower (setugt X, 2047) as (setne (srl X, 11), 0) (#155541)
2025-08-26 23:05:41 -07:00
iabs.ll
[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDValue with just the frozen node (#150017)
2025-08-05 09:24:09 +01:00
icmp-non-byte-sized.ll
[RISCV] Support non-power-of-2 types when expanding memcmp
2025-06-18 16:11:18 +08:00
idiv_large.ll
…
imm-cse.ll
…
imm.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
indirectbr.ll
…
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-d-modifier-N.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-f-modifier-N.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-fixed-v-constraint.ll
[RISCV][llvm] Support fixed-length vector inline assembly constraints (#150724)
2025-08-18 03:36:12 +00:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
[RISCV] Check the VT for R and cR inline asm constraints is 2*xlen. (#137749)
2025-04-29 08:12:32 -07:00
inline-asm-mem-constraint-2.ll
[test][RISCV] Precommit inline asm tests for #104925
2024-08-26 13:30:23 +03:00
inline-asm-mem-constraint.ll
[ARM,AArch64] Don't put BTI at asm goto branch targets (#141562)
2025-06-03 08:44:13 +01:00
inline-asm-s-constraint-error.ll
…
inline-asm-s-constraint.ll
…
inline-asm-v-constraint.ll
[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283)
2024-12-06 00:48:05 +08:00
inline-asm-xsfvcp.ll
[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)
2024-09-30 23:52:35 -07:00
inline-asm-zdinx-constraint-r.ll
[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)
2024-10-18 18:17:23 -07:00
inline-asm-zfh-constraint-f.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
inline-asm-zfh-modifier-N.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-asm-zfinx-constraint-r.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-zhinx-constraint-r.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-option-directive.ll
…
instruction-count-remark.mir
Register assembly printer passes (#138348)
2025-05-06 18:01:17 -07:00
interrupt-attr-args-error.ll
[RISCV] Mark More Fatal Errors as Usage/Internal (#154876)
2025-08-22 11:57:17 -07:00
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
[RISCV] Mark More Fatal Errors as Usage/Internal (#154876)
2025-08-22 11:57:17 -07:00
interrupt-attr-nocall.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
interrupt-attr-ret-error.ll
[RISCV] Mark More Fatal Errors as Usage/Internal (#154876)
2025-08-22 11:57:17 -07:00
interrupt-attr.ll
[RISCV][llvm] Handle vector callee saved register correctly (#149467)
2025-07-21 17:49:34 -07:00
intrinsic-cttz-elts-vscale.ll
[DAG] visitFREEZE - limit freezing of multiple operands (#149797)
2025-07-22 15:40:55 +01:00
intrinsic-cttz-elts.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
ipra.ll
[RISCV] Implement getIPRACSRegs hook (#125586)
2025-02-04 10:02:42 -03:00
isel-optnone.ll
…
jumptable-swguarded.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
jumptable.ll
[RISCV] Use QC_E_LI to materialise addresses (#155819)
2025-09-05 12:58:28 +05:30
kcfi-isel-mir.ll
[RISCV] Add call preserved regmask to tail calls. (#122181)
2025-01-08 16:19:31 -08:00
kcfi-mir.ll
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
kcfi-patchable-function-prefix.ll
…
kcfi.ll
[RISCV,test] Replace -riscv-no-aliases with -M no-aliases
2025-04-08 19:42:43 -07:00
lack-of-signed-truncation-check.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
large-stack.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
legalize-fneg.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
libcall-tail-calls.ll
…
lit.local.cfg
…
live-sp.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
llvm.exp10.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
llvm.frexp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
load-setcc-combine.ll
…
load-store-pair.ll
[RISCV] Generate MIPS load/store pair instructions (#124717)
2025-03-07 09:21:36 +01:00
local-stack-slot-allocation.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
loop-strength-reduce-add-cheaper-than-mul.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
loop-strength-reduce-loop-invar.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
lpad.ll
[RISCV] Remove Last Traces of User Interrupts (#129300)
2025-03-04 11:36:16 -08:00
lrint-conv.ll
[Test] Add and update tests for lrint/llrint (NFC) (#152662)
2025-08-12 09:56:51 +09:00
lsr-legaladdimm.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
machine-combiner-mir.ll
[CodeGen] Drop disjoint flag when reassociating (#156218)
2025-08-31 11:23:15 -07:00
machine-combiner-strategies.ll
…
machine-combiner.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
machine-combiner.mir
…
machine-copyprop-noop-removal.mir
[MachineCopyPropagation] Recognise and delete no-op moves produced after forwarded uses (#129889)
2025-03-10 13:22:59 +00:00
machine-copyprop-simplifyinstruction.mir
[MCP] Handle iterative simplification during forward copy prop (#140267)
2025-06-02 11:21:41 -07:00
machine-cp.mir
…
machine-cse.ll
…
machine-outliner-and-machine-copy-propagation.ll
…
machine-outliner-call-x5-liveout.mir
[RISCV] [MachineOutliner] Analyze all candidates (#127659)
2025-02-21 12:53:13 +05:30
machine-outliner-call.ll
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-cfi.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-leaf-descendants.ll
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-patchable.ll
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-position.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-throw.ll
…
machine-pipeliner.ll
[PHIElimination] Revert #131837 #146320 #146337 (#146850)
2025-07-03 07:48:08 -04:00
machine-sink-load-immediate.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
machinelicm-address-pseudos.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
machinelicm-constant-phys-reg.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
[RISCV] Don't outline pcrel_lo when the function has a section prefix (#107943)
2024-09-11 09:53:11 -07:00
machineoutliner-x5.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machineoutliner.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
MachineSink-implicit-x0.mir
[CodeGen][NewPM] Port MachineSink to NPM (#115434)
2025-03-03 15:49:37 +05:30
macro-fusion-lui-addi.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
macro-fusions.mir
[RISCV] add more generic macrofusions (#151140)
2025-08-06 14:46:34 -04:00
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
…
make-compressible-zbc-zhinx.mir
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
make-compressible-zbc.mir
[RISCV] Fix IR for store_large_offset_no_opt_i16 in make-compressible-zbc.mir. NFC
2024-09-16 12:51:07 -07:00
make-compressible-zfinx.mir
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
make-compressible-zilsd.mir
[RISCV] Correctly account for the copy cost of GPR pairs in RISCVMakeCompressible. (#141251)
2025-05-23 11:37:42 -07:00
make-compressible.mir
…
mem64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memcmp-optsize.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
memcmp.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
memcpy-inline.ll
…
memcpy.ll
Reapply "[RISCV] Rework memcpy test (#120364)"
2025-01-13 12:06:26 +08:00
memmove.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memset-inline.ll
[RISCV][NFC] Rename memset tests (#151486)
2025-07-31 18:47:57 +08:00
memset-pattern.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
min-max.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
mir-target-flags.ll
…
misched-load-clustering.ll
[RISCV] add load/store misched/PostRA subtarget features (#149409)
2025-08-06 09:08:25 -07:00
misched-mem-clustering.mir
[RISCV] add load/store misched/PostRA subtarget features (#149409)
2025-08-06 09:08:25 -07:00
misched-postra-direction.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
misched-store-clustering.ll
[RISCV] add load/store misched/PostRA subtarget features (#149409)
2025-08-06 09:08:25 -07:00
miss-sp-restore-eh.ll
Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#136701)
2025-04-22 17:36:41 -04:00
module-elf-flags.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
module-target-abi2.ll
…
module-target-abi3.ll
…
module-target-abi.ll
…
mul-expand.ll
[RISCV] Expand constant multiplication for targets without M extension (#137195)
2025-05-16 09:40:11 +08:00
mul.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
musttail-call.ll
…
naked-fn-with-frame-pointer.ll
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
narrow-shl-cst.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
neg-abs.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
nest-register.ll
[RISCV] Guard the alternative static chain register use on ILP32E/LP64E (#142715)
2025-06-12 02:24:10 +08:00
nomerge.ll
…
nontemporal-scalable.ll
…
nontemporal.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
note-gnu-property-zicfiss.ll
[RISCV] Improvements to .note.gnu.property section. (#151436)
2025-08-04 09:20:25 -07:00
O0-pipeline.ll
[RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation (#139993)
2025-06-17 17:21:24 +08:00
O3-pipeline.ll
[RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation (#139993)
2025-06-17 17:21:24 +08:00
opt-w-instrs.mir
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
option-exact-inlineasm.ll
[RISCV] Support .option {no}exact (#122483)
2025-03-26 11:14:16 -07:00
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax-relocation.ll
RISCV: Remove shouldForceRelocation and unneeded relocations
2025-05-23 18:44:15 -07:00
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
or-is-add.ll
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
2025-02-25 10:04:57 -08:00
orc-b-patterns.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
out-of-reach-emergency-slot.mir
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
overflow-intrinsic-optimizations.ll
…
overflow-intrinsics.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
patchable-function-entry.ll
[RISCV,test] Replace -riscv-no-aliases with -M no-aliases
2025-04-08 19:42:43 -07:00
pei-crash.ll
…
pic-models.ll
…
poison-legalization.ll
Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison value in the IR." (#135056)
2025-04-10 11:29:14 -04:00
postra-copy-expand.mir
[RISCV] Attach an implicit source operand on vector copies (#126155)
2025-02-08 16:25:27 -08:00
pr40333.ll
…
pr51206.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr53662.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
pr55201.ll
…
pr56110.ll
…
pr56457.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr58025.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
pr58286.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr58511.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr63365.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
pr63816.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr64503.ll
…
pr64645.ll
…
pr64772.ll
…
pr64935.ll
…
pr65025.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
pr66603.ll
…
pr68855.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr69586.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr80052.mir
…
pr84200.ll
…
pr84653_pr85190.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
pr88365.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
pr90652.ll
…
pr90730.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr92193.ll
…
pr94145.ll
[DAG] canCreateUndefOrPoison - fix missing argument typo
2024-06-02 10:34:48 +01:00
pr94265.ll
[RISCV] Replace hasStdExtV with hasVInstructions in isTruncateFree.
2024-07-29 17:15:02 -07:00
pr95271.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr95284.ll
[DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (#114389)
2024-10-31 16:40:29 +00:00
pr96366.ll
[SDAG] Intersect poison-generating flags after CSE (#97434)
2024-07-03 20:32:46 +08:00
pr97304.ll
[RISCV] Add correct MachinePointerInfo when putting arguments on the stack. (#110140)
2024-09-27 13:48:01 -07:00
pr101786.ll
[CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (#102731)
2025-04-23 08:54:10 +03:00
pr135206.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
pr142004.ll
[DAGCombiner] Teach SearchForAndLoads to handle an AND with 2 constant operands. (#142062)
2025-05-30 16:00:43 -07:00
pr145360.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
pr145363.ll
[SelectionDAG] Combine range metadata when loads are CSEd. (#146026)
2025-06-27 08:58:06 -07:00
pr148084.ll
[RISCV] Add test coverage for #148084
2025-07-23 09:21:07 +01:00
pr153598.mir
[RISCV][MoveMerge] Don't copy kill flag when moving past an instruction that reads the register. (#153644)
2025-08-14 14:52:54 -07:00
prefer-w-inst.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
prefer-w-inst.mir
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
prefetch.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
print-pipeline-passes.ll
[RISCV] Add -print-pipeline-passes test as follow up to #156798. NFC (#157011)
2025-09-05 08:07:39 -07:00
prolog-epilogue.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
push-pop-opt-crash.ll
[RISCV] Update unrelated bad code from test case
2025-03-19 11:09:49 -07:00
push-pop-popret.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
qci-interrupt-attr-fpr.ll
[RISCV] QCI Interrupt Support (#129957)
2025-03-06 13:31:08 -08:00
qci-interrupt-attr.ll
[RISCV] Support Push/Pop with Xqci (#134191)
2025-04-28 08:12:45 -07:00
rda-stack.mir
[ReachingDefAnalysis] Fix management of MBBFrameObjsReachingDefs (#124943)
2025-02-04 10:04:19 -05:00
readcyclecounter.ll
…
readsteadycounter.ll
…
reassoc-shl-addi-add.ll
[RISCV] Simplify and remove unrelated testcases in reassoc-shl-addi-add.ll. NFC.
2025-06-10 19:10:48 +08:00
reduce-unnecessary-extension.ll
…
reduction-formation.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
redundant-copy-from-tail-duplicate.ll
[RISCV] Set AllocationPriority in line with LMUL (#131176)
2025-03-18 08:25:49 -07:00
regalloc-last-chance-recoloring-failure.ll
[RISCV] Optimize the spill/reload of segment registers (#153184)
2025-08-21 16:38:53 +08:00
relative-reloc.ll
AsmPrinter: Remove ELF's special lowerRelativeReference for unnamed_addr function; use lowerDSOLocalEquivalent in more cases
2025-04-08 10:11:20 -07:00
relax-per-target-feature.ll
…
rem.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
remat.ll
…
renamable-copy.mir
[TII][RISCV] Add renamable bit to copyPhysReg (#91179)
2024-08-27 10:08:43 +08:00
repeated-fp-divisors.ll
…
replace-with-veclib-sleef-scalable.ll
[RISCV][SLEEF] Fix incorrect vector function mapping for llvm.exp.f64 (#121641)
2025-05-12 13:34:46 +08:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegen-prepare-atp.ll
[RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (#102560)
2024-08-15 10:37:04 +08:00
riscv-codegenprepare-asm.ll
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
riscv-codegenprepare.ll
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
riscv-func-target-feature.ll
…
riscv-tail-dup-size.ll
[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873)
2024-08-01 12:24:25 +08:00
riscv-zihintpause.ll
[RISCV] Add zihintpause LLVM/Clang intrinsic (#139519)
2025-05-16 14:20:53 +08:00
rnmi-interrupt-attr-error.ll
[RISCV] Support resumable non-maskable interrupt handlers (#148134)
2025-08-04 10:54:50 +02:00
rnmi-interrupt-attr.ll
[RISCV] Support resumable non-maskable interrupt handlers (#148134)
2025-08-04 10:54:50 +02:00
rotl-rotr.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv32-fuchsia.ll
…
rv32-inline-asm-pairs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll
[RISCV] Remove the TODO for lowering f32 libcall on RV64 with lp64 abi. (NFC)
2025-03-07 10:52:04 +08:00
rv32i-rv64i-half.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv32xandesperf.ll
[RISCV] Fold (sext_inreg (setcc), i1) -> (sub 0, (setcc). (#154206)
2025-08-18 21:24:03 -07:00
rv32xtheadba.ll
[RISCV] Add 2^N + 2^M expanding pattern for mul (#137954)
2025-05-10 11:16:39 +08:00
rv32xtheadbb.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
rv32xtheadbs.ll
…
rv32zba.ll
[RISCV] Implement codegen for XAndesPerf lea instructions (#137925)
2025-05-12 10:41:53 +08:00
rv32zbb-intrinsic.ll
[RISCV] Add ORC_B to SimplifyDemandedBitsForTargetNode. (#141975)
2025-05-29 12:33:36 -07:00
rv32zbb-zbkb.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
rv32zbb.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
[RISCV] Relax one of the zexti8 in the PACKH+PACK(W)/SLLI patterns. (#152384)
2025-08-06 17:46:43 -07:00
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
rv32zimop-intrinsic.ll
…
rv32zknd-intrinsic-autoupgrade.ll
…
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic-autoupgrade.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic-autoupgrade.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-double-convert-strict.ll
[RISCV] Add test cases for RV64 i128<->half/float/double (#115124)
2024-11-06 11:36:30 -08:00
rv64-double-convert.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
rv64-float-convert-strict.ll
[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)
2024-12-02 09:06:08 -08:00
rv64-float-convert.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
rv64-half-convert-strict.ll
[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)
2024-12-02 09:06:08 -08:00
rv64-half-convert.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
rv64-inline-asm-pairs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-large-stack.ll
…
rv64-patchpoint.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64-stackmap-args.ll
[CodeGen] @llvm.experimental.stackmap make operands immediate (#117932)
2024-12-11 17:41:19 +08:00
rv64-stackmap-frame-setup.ll
…
rv64-stackmap-nops.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
rv64-stackmap.ll
…
rv64-statepoint-call-lowering-x1.ll
…
rv64-statepoint-call-lowering-x2.ll
…
rv64-statepoint-call-lowering.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
rv64-trampoline-cfi.ll
[RISC-V] Adjust trampoline code for branch control flow protection (#141949)
2025-06-07 23:51:08 +08:00
rv64-trampoline.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64-typepromotion.ll
…
rv64d-double-convert-strict.ll
[RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC
2024-11-05 21:48:38 -08:00
rv64d-double-convert.ll
[RISCV] Add Zdinx RUN line to rv64d-double-convert.ll. NFC
2024-11-05 21:12:09 -08:00
rv64e.ll
…
rv64f-float-convert-strict.ll
[RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC
2024-11-05 21:48:38 -08:00
rv64f-float-convert.ll
…
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv64i-shift-sext.ll
[RISCV] Add computeKnownBitsForTargetNode for RISCVISD::SRAW. (#156191)
2025-08-30 18:27:18 -07:00
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)
2024-11-25 18:59:31 -08:00
rv64xandesperf.ll
[RISCV] Fold (sext_inreg (setcc), i1) -> (sub 0, (setcc). (#154206)
2025-08-18 21:24:03 -07:00
rv64xtheadba.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64xtheadbb.ll
[RISCV] Add th.ext(u) to isSignExtendingOpW in RISCVOptWInstrs. (#157147)
2025-09-05 12:05:28 -07:00
rv64xtheadbs.ll
…
rv64zba.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv64zbb-intrinsic.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64zbb-zbkb.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv64zbb.ll
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkb.ll
[RISCV] Add another packh+packw pattern. (#152744)
2025-08-09 09:23:44 -05:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
[RISCV] Don't combine (sext_inreg (fmv_x_anyexth X), i16) with Zhinx.
2024-08-14 15:18:10 -07:00
rv64zfh-half-intrinsics.ll
…
rv64zfhmin-half-convert-strict.ll
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
2024-09-03 13:33:14 -07:00
rv64zfhmin-half-convert.ll
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
2024-09-03 13:33:14 -07:00
rv64zfhmin-half-intrinsics.ll
…
rv64zimop-intrinsic.ll
…
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic-autoupgrade2.ll
…
rv64zksed-intrinsic-autoupgrade.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic-autoupgrade.ll
…
rv64zksh-intrinsic.ll
…
sadd_sat_plus.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
sadd_sat.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
saverestore-scs.ll
…
saverestore.ll
…
scmp.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
sdata-sections.ll
[RISCV] Let -data-sections also work on sbss/sdata sections (#87040)
2024-08-23 14:06:12 +01:00
sdiv-pow2-cmov.ll
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select-and.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-bare.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-binop-identity.ll
[RISCV] Add a conditional-cmv-fusion RUN line to select-binop-identity.ll. NFC (#155950)
2025-08-28 19:35:58 -07:00
select-cc.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
select-cond.ll
[RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (#146675)
2025-07-11 10:27:13 +05:30
select-const.ll
[RISCV] Use arithmetic for select c, 0, simm12 even with zicond (#156957)
2025-09-04 14:51:14 -07:00
select-constant-xor.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
select-optimize-multiple.ll
[RISCV] Move CascadeSelect test into float/half/double-select-fcmp.ll. NFC
2025-06-26 09:46:14 -07:00
select-optimize-multiple.mir
[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)
2024-06-04 09:23:52 +08:00
select-or.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-to-and-zext.ll
…
select.ll
[RISCV] Add coverage for the tryFoldSelectIntoOp combine with constants
2025-09-07 17:01:26 -07:00
selectcc-to-shiftand.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
setcc-logic.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
sext-zext-trunc.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
sextw-removal-debug.mir
…
sextw-removal.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
shadowcallstack.ll
[RISCV] Separate HW/SW shadow stack on RISC-V (#112478)
2024-11-08 00:16:45 +08:00
shift-amount-mod.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
shift-and.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
shift-masked-shamt.ll
…
shifts.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
shl-cttz.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
shl-demanded.ll
…
shlimm-addimm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
short-forward-branch-opt.ll
[RISCV] Guard CFI emission code with MF.needsFrameMoves() (#136060)
2025-07-18 16:49:30 +03:00
shrinkwrap-jump-table.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
shrinkwrap.ll
[RISCV] Add shrinkwrap test cases showing gaps in current impl
2024-11-27 11:14:51 -08:00
sifive7-enable-intervals.mir
[MISched] Unify the way to specify scheduling direction (#119518)
2024-12-12 11:24:07 +08:00
sifive-interrupt-attr-err.ll
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
sifive-interrupt-attr.ll
[RISCV] Fix Defs/Uses for SiFive CLIC Support (#137724)
2025-04-28 19:35:11 -07:00
signbit-test.ll
…
signed-truncation-check.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
simplify-condbr.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
sink-and-fold-crash.mir
[MachineSink][RISCV] Only call isConstantPhysReg or isIgnorableUse for uses. (#99363)
2024-07-17 13:06:58 -07:00
sink-icmp.ll
…
spill-fill-fold.ll
…
spill-fpr-scalar.ll
…
spir-kernel-cc.ll
…
split-offsets.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
split-sp-adjust.ll
…
split-store.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
split-udiv-by-constant.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
split-urem-by-constant.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
srem-lkk.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
srem-seteq-illegal-types.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
srem-vector-lkk.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
srodata.ll
…
ssub_sat_plus.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
ssub_sat.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-clash-prologue-nounwind.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-clash-prologue.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-folding.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
stack-guard-global.ll
[RISCV] Support -mstack-protector-guard=tls (#108942)
2024-10-02 16:33:31 -07:00
stack-guard-tls.ll
[RISCV] Support -mstack-protector-guard=tls (#108942)
2024-10-02 16:33:31 -07:00
stack-inst-compress.mir
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-offset.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-probing-frame-setup.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
stack-protector-target.ll
RuntimeLibcalls: Add some tests for OpenBSD stack protectors (#147888)
2025-07-15 15:50:54 +09:00
stack-realignment-with-variable-sized-objects.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
stack-realignment.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
stack-slot-coloring.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
stack-slot-size.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
stack-store-check.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
subtarget-features-std-ext.ll
…
switch-width.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
tagged-globals.ll
…
tail-calls.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
…
tlsdesc-symbol.ll
…
trunc-free.ll
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trunc-nsw-nuw.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
typepromotion-overflow.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
uadd_sat_plus.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
uadd_sat.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
ucmp.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
umulo-128-legalisation-lowering.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
unaligned-load-store.ll
[RISCV] Add a high half PACKW+PACK pattern for RV64. (#152760)
2025-08-11 07:37:55 -05:00
unfold-masked-merge-scalar-variablemask.ll
Reland "[SelectionDAG] Make (a & x) | (~a & y) -> (a & (x ^ y)) ^ y available for all targets" (#143651)
2025-06-11 15:56:37 +08:00
unroll-loop-cse.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
urem-lkk.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
urem-seteq-illegal-types.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
urem-vector-lkk.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
usub_sat_plus.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
usub_sat.ll
…
vararg-ilp32e.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
vararg.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
varargs-with-fp-and-second-adj.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
vector-abi.ll
…
vector-tuple-zeroinitializer.ll
[RISCV] Handle zeroinitializer of vector tuple Type (#113995)
2024-12-04 13:40:02 +08:00
verify-instr.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
vlenb.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
vscale-demanded-bits.ll
Move stepvector intrinsic out of experimental namespace (#98043)
2024-08-28 12:48:20 +01:00
wide-mem.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
wide-scalar-shift-legalization.ll
[DAG] visitFREEZE - limit freezing of multiple operands (#149797)
2025-07-22 15:40:55 +01:00
xaluo.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
xandesbfhcvt.ll
[RISCV] Implement load/store support for XAndesBFHCvt (#150350)
2025-07-25 11:29:17 +08:00
xcvalu.ll
[RISCV] Rename XCValu intrinsic name *_slet(u) to *_sle(u)) (#138498)
2025-05-06 09:57:07 +08:00
xcvbi.ll
[PHIElimination] Revert #131837 #146320 #146337 (#146850)
2025-07-03 07:48:08 -04:00
xcvbitmanip.ll
…
xcvmac.ll
[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112)
2024-07-15 10:25:25 +10:00
xcvmem-heuristic.ll
[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533)
2024-12-31 10:56:28 +08:00
xcvmem.ll
RISCV: Convert test to opaque pointers
2025-04-07 23:45:54 +07:00
xmips-cbop.ll
[RISCV] Handled the uimm9 offset while FrameIndex folding. (#149303)
2025-07-30 17:43:10 +02:00
xqccmp_mvas_mvsa.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-additional-stack.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
xqccmp-callee-saved-gprs.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
xqccmp-cm-popretz.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-cm-push-pop.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-push-pop-popret.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
xqccmp-with-float.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
xqcia.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
xqciac.ll
[RISCV] Compress shxadd to qc.c.muliadd when rd = rs2 (#155843)
2025-09-01 12:34:25 +05:30
xqcibi.ll
[RISCV] Fix Immediate Check for Xqcibi UGT (#153141)
2025-08-12 11:06:00 -07:00
xqcibm-cto-clo-brev.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
xqcibm-extract.ll
[RISCV] Update some tests to use a common check prefix. NFC.
2025-08-20 11:29:57 +08:00
xqcibm-insbi.ll
[RISCV] Add changes to have better coverage for qc.insb and qc.insbi (#154135)
2025-09-03 12:35:38 +05:30
xqcibm-insert.ll
[RISCV] Generate QC_INSB/QC_INSBI instructions from OR of AND Imm (#154023)
2025-08-19 11:14:14 +05:30
xqcicli.ll
[RISCV] Add ISel patterns for Qualcomm uC Xqcicli extension (#148121)
2025-07-15 12:13:57 +05:30
xqcicm.ll
[RISCV] Correct immediate operand type in QC_MVLTUI ISel pattern (#147509)
2025-07-08 21:28:45 +05:30
xqcics.ll
[RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (#146675)
2025-07-11 10:27:13 +05:30
xqcilia.ll
[RISCV] Add ISel patterns for Xqcilia instructions (#135724)
2025-04-16 06:48:56 +05:30
xqcilo.ll
[RISCV] Add basic ISel patterns for Xqcilo instructions (#135901)
2025-04-16 11:19:13 +05:30
xqcilsm-memset.ll
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555)
2025-08-04 12:51:14 +05:30
xqcisls.ll
[RISCV] Add profitability checks to SelectAddrRegRegScale. (#150135)
2025-07-22 21:10:52 -07:00
xray-attribute-instrumentation.ll
[XRay][RISCV] RISCV support for XRay (#117368)
2024-12-10 17:57:04 -08:00
xtheadfmemidx.ll
[RISCV] Improves to xtheadmemidx.ll and xtheadfmemidx.ll. NFC
2025-07-22 12:46:03 -07:00
xtheadmac.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
xtheadmemidx.ll
[RISCV] Add profitability checks to SelectAddrRegRegScale. (#150135)
2025-07-22 21:10:52 -07:00
xtheadmempair.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
zalasr-offset-folding.ll
[RISCV] Return false for Zalasr load/store in isWorthFoldingAdd. (#136799)
2025-04-23 14:47:42 -07:00
zbb-cmp-combine.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
zbb-logic-neg-imm.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
zcb-regalloc-hints.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
zcmp-additional-stack.ll
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
2025-08-27 15:59:08 -07:00
zcmp-cm-popretz.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
zcmp-cm-push-pop.mir
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
zcmp-prolog-epilog-crash.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
zcmp-with-float.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
zdinx-asm-constraint.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
zdinx-boundary-check.ll
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
zdinx-large-spill.mir
[RISCV] Tweak zdinx-large-spill.mir so it tests what it was intended to. NFC
2025-05-14 12:35:49 -07:00
zdinx-memoperand.ll
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
zdinx-spill.ll
[RISCV] Guard CFI emission code with MF.needsFrameMoves() (#136060)
2025-07-18 16:49:30 +03:00
zext-with-load-is-free.ll
[RISCV] Remove the TODO that lbu and lhu should be selected to avoid the unnecessary masking. NFC.
2025-04-21 11:02:04 +08:00
zfh-half-intrinsics-strict.ll
[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633)
2024-11-25 16:12:45 -08:00
zfh-half-intrinsics.ll
…
zfhmin-half-intrinsics-strict.ll
[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633)
2024-11-25 16:12:45 -08:00
zfhmin-half-intrinsics.ll
[RISCV] Add test for llvm.round.i32.f16 RV64+Zfhmin/Zhinxmin. NFC
2024-09-01 12:15:00 -07:00
zfhmin-imm.ll
…
zicfilp-indirect-branch.ll
…
zicond-opts.ll
[RISCV] Efficiently lower (select %cond, andn (f, x), f) using zicond (#147369)
2025-07-09 09:32:54 -04:00
zilsd.ll
[RISCV] Add RISCVISD::LD_RV32/SD_RV32 to isWorthFoldingAdd. (#151606)
2025-07-31 22:03:29 -07:00
zmmul.ll
…