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llvm-project/llvm/test/CodeGen/AMDGPU
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Krzysztof Drewniak 469757efaf
[AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621) 
Since LowerBufferFatPointers runs before PreISelIntrinsicLowering, which
normally handles unsupported memcpy()s,, and since you can't have a
`noalias {ptr addrspace(8), i32}` becasue it crashes later passes,
manually expand memcpy()s involving buffer fat pointers to loops.

Additionally, though they're unlikely to be used, this commit adds
support for memset().

This commit doesn't implement writing direct-to-LDS loads as the
intrinsics, but leaves the option in the future.
2025-02-26 16:03:32 -06:00
..
GlobalISel
[AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (#128905)
2025-02-26 23:55:29 +07:00
32-bit-local-address-space.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
aa-as-infer.ll
[Attributor] Take the address space from addrspacecast directly (#108258)
2024-10-09 22:51:07 -04:00
aa-points-to-constant-memory.ll
…
abi-attribute-hints-undefined-behavior.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
abs_i16.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
acc-ldst.ll
[AMDGPU] Update LiveInterval def index for early-clobber (#79285)
2024-03-11 14:54:11 +09:00
accvgpr-copy.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
accvgpr-spill-scc-clobber.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
add3.ll
…
add64-low-32-bits-known-zero.ll
AMDGPU: Reduce 64-bit add width if low bits are known 0 (#122049)
2025-01-08 22:33:54 +07:00
add_i1.ll
[DAG] getNode - convert scalar i1 arithmetic calls to bitwise instructions (#125486)
2025-02-03 16:36:01 +00:00
add_i64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
add_i128.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
add_shl.ll
…
add_sub_u64_pseudos.mir
[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)
2024-06-04 09:23:52 +08:00
add-debug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
add.i16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
add.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
add.v2i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
addrspacecast-captured.ll
…
addrspacecast-constantexpr.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
addrspacecast-initializer-unsupported.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
addrspacecast-initializer.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
addrspacecast-known-non-null.ll
…
addrspacecast.gfx6.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
addrspacecast.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
addrspacecast.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
adjust-writemask-cse.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
adjust-writemask-invalid-copy.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
adjust-writemask-vectorized.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
agpr-copy-no-free-registers-assertion-after-ra-failure.ll
RegAlloc: Use new approach to handling failed allocations (#128469)
2025-02-26 15:34:47 +07:00
agpr-copy-no-free-registers.ll
AMDGPU: Respect amdgpu-no-agpr in functions and with calls (#128147)
2025-02-23 09:00:37 +07:00
agpr-copy-no-vgprs.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
agpr-copy-propagation.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
agpr-copy-reuse-writes.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
agpr-copy-sgpr-no-vgprs.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
agpr-csr.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
agpr-register-count.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
agpr-remat.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
agpr-to-agpr-copy.mir
[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)
2025-02-11 11:09:38 +05:30
alignbit-pat.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
alloc-aligned-tuples-gfx90a.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
alloc-aligned-tuples-gfx908.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
alloc-all-regs-reserved-in-class.mir
RegAlloc: Do not fatal error if there are no registers in the alloc order (#119640)
2024-12-16 10:52:49 +09:00
alloca.ll
…
allow-check.ll
[CodeGen] Add default lowering for llvm.allow.{runtime,ubsan}.check() (#86049)
2024-03-31 22:19:33 -07:00
always-uniform.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
amd.endpgm.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
amdgcn-ieee.ll
…
amdgcn-load-offset-from-reg.ll
[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)
2024-07-23 13:59:15 +05:30
amdgcn.bitcast.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
amdgcn.private-memory.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
amdgpu-alias-analysis.ll
[AMDGPU] Fix spurious NoAlias results (#122309)
2025-01-20 14:19:30 +00:00
amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
[Attributor] Fix an issue that could potentially cause AccessList and OffsetBins out of sync (#106187)
2024-08-29 01:02:19 -04:00
amdgpu-attributor-no-agpr.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
amdgpu-branch-weight-metadata.ll
[NFC][AMDGPU] Rename test (#126725)
2025-02-11 15:10:37 +01:00
amdgpu-codegenprepare-break-large-phis-heuristics.ll
…
amdgpu-codegenprepare-break-large-phis.ll
[AMDGPU] Reland: Add IR LiveReg type-based optimization
2024-07-03 09:26:19 -07:00
amdgpu-codegenprepare-fdiv.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
amdgpu-codegenprepare-fold-binop-select.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
amdgpu-codegenprepare-i16-to-i32.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
amdgpu-codegenprepare-idiv.ll
PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)
2025-01-30 20:42:02 +07:00
amdgpu-codegenprepare-mul24.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
amdgpu-codegenprepare-sqrt.ll
…
amdgpu-cs-chain-cc.ll
[AMDGPU] Fix @llvm.amdgcn.cs.chain with SGPR args not provably uniform (#114232)
2024-10-30 16:12:37 +00:00
amdgpu-cs-chain-preserve-cc.ll
AMDGPU: Handle v_add* in eliminateFrameIndex (#102346)
2024-10-02 21:19:45 +04:00
amdgpu-function-calls-option.ll
…
amdgpu-inline.ll
…
amdgpu-late-codegenprepare.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
amdgpu-libcall-sincos-pass-ordering.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
amdgpu-max-num-workgroups-load-annotate.ll
AMDGPU: Mark grid size loads with range metadata (#113019)
2024-12-09 11:01:55 -05:00
amdgpu-mul24-knownbits.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
amdgpu-nsa-threshold.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
amdgpu-reloc-const.ll
[test] Remove immarg parameter attribute from calls (#97432)
2024-07-03 09:02:31 +01:00
amdgpu-shader-calling-convention.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
amdgpu-simplify-libcall-ceil.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-copysign.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-exp2.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-exp.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-fabs.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-floor.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-fma.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-fmax-splat.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-fmax.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-fmin-splat.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-fmin.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-image-function-signatures.ll
AMDGPU: Fix libcall recognition of image array types (#119832)
2024-12-16 15:04:53 +09:00
amdgpu-simplify-libcall-ldexp-splat.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-ldexp.ll
AMDGPU: Verify function type matches when matching libcalls (#119043)
2024-12-16 15:01:48 +09:00
amdgpu-simplify-libcall-log2.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-log10.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-log.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-mad.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-pow-codegen.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
amdgpu-simplify-libcall-pow.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
amdgpu-simplify-libcall-pown.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
amdgpu-simplify-libcall-powr.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
amdgpu-simplify-libcall-rint.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-rootn.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
amdgpu-simplify-libcall-round.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-sincos.defined.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
amdgpu-simplify-libcall-sincos.defined.nobuiltin.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
amdgpu-simplify-libcall-sincos.defined.sin.cos.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
amdgpu-simplify-libcall-sincos.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
amdgpu-simplify-libcall-sincos.nobuiltins.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
amdgpu-simplify-libcall-sincos.weak.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
amdgpu-simplify-libcall-sqrt.ll
AMDGPU: Replace sqrt OpenCL libcalls with llvm.sqrt (#74197)
2024-01-09 15:13:58 +07:00
amdgpu-simplify-libcall-trunc.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
amdgpu-simplify-libcall-unexpected-types.ll
AMDGPU: Do not assert on unhandled types when demangling libcalls (#120068)
2024-12-16 20:27:06 +07:00
amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-dynamic-indirect-access.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-dynamic-lds-test.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-multiple-blocks-return-asan.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-multiple-blocks-return.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-non-kernel-declaration.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-static-dynamic-lds-test.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-static-indirect-access-asan.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-static-indirect-access-function-param.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-indirect-access-nested.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-indirect-access.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
[AMDGPU] Remove amdgpu-no-heap-ptr and amdgpu-no-lds-kernel-id attributes from lowered kernels in amdgpu-sw-lower-lds pass (#120887)
2024-12-23 12:42:31 +05:30
amdgpu-sw-lower-lds-static-lds-O0.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-lds-test-asan.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
[AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (#87265)
2024-08-26 08:59:26 +05:30
amdgpu-sw-lower-lds-static-lds-test.ll
[AMDGPU] Add amdgpu-sw-lower-lds pass to NPM codegen addIRPasses. (#124102)
2025-01-24 11:15:30 +05:30
amdgpu-sw-lower-lds-static-lds-vector-ptrs.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-unroll-threshold.ll
…
amdgpu.private-memory.ll
[AsmParser] Convert empty arrays to poison (#119754)
2024-12-12 22:44:10 +01:00
amdgpu.work-item-intrinsics.deprecated.ll
AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (#128700)
2025-02-25 22:21:03 +07:00
amdhsa-kernarg-preload-num-sgprs.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
amdhsa-trap-num-sgprs.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
amdpal_scratch_mergedshader.ll
…
amdpal-callable.ll
[AMDGPU] Update base addr of dyn alloca considering GrowingUp stack (#119822)
2024-12-20 10:27:27 +05:30
amdpal-chain-metadata.ll
[AMDGPU] Emit backend_stack_size PAL metadata (#72509)
2023-11-20 10:01:13 +01:00
amdpal-cs.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
amdpal-elf.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
amdpal-es.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
amdpal-gs.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
amdpal-hs.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
amdpal-ls.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
amdpal-metadata-agpr-register-count.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
amdpal-msgpack-cs.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-default.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-denormal.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-dx10-clamp.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-es.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-gs.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-hs.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-ieee.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-ls.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-ps.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-psenable.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-msgpack-vs.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-ps.ll
…
amdpal-psenable.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
amdpal-usersgpr-init.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
amdpal-vs.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
amdpal.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
and_or.ll
…
and-gcn.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
and.ll
[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)
2024-07-23 13:59:15 +05:30
andorbitset.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
andorn2.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
andorxorinvimm.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
annotate-existing-abi-attributes.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
annotate-kernel-features-hsa-call.ll
[AMDGPU][Attributor] Make AAAMDWavesPerEU honor existing attribute (#114438)
2024-12-11 16:50:06 -05:00
annotate-kernel-features-hsa.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
annotate-kernel-features.ll
Reapply "[AMDGPU] Infer amdgpu-no-flat-scratch-init attribute in AMDGPUAttributor (#94647)" (#118907)
2024-12-09 16:44:48 -08:00
annotate-noclobber.ll
AMDGPU/NewPM: Port AMDGPUAnnotateUniformValues to new pass manager (#102654)
2024-08-10 07:06:08 +04:00
anonymous-gv.ll
…
any_extend_vector_inreg.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
anyext.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
are-loads-from-same-base-ptr.ll
…
array-ptr-calc-i32.ll
AMDGPU: Handle v_add* in eliminateFrameIndex (#102346)
2024-10-02 21:19:45 +04:00
array-ptr-calc-i64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
artificial-terminators.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ashr.v2i16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
asm-printer-check-vcc.mir
…
assert-wrong-alloca-addrspace.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
at-least-one-def-value-assert.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
atomic_cmp_swap_local.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
atomic_load_add.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
atomic_load_local.ll
AMDGPU: Add atomic bfloat load/store codegen tests
2024-04-25 16:08:11 +02:00
atomic_load_sub.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
atomic_optimization_split_dt_update.ll
[AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (#89217)
2024-06-25 14:35:19 +05:30
atomic_optimizations_buffer.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
atomic_optimizations_global_pointer.ll
AMDGPU: Fix creating illegally typed readfirstlane in atomic optimizer (#128388)
2025-02-24 18:39:49 +07:00
atomic_optimizations_local_pointer.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
atomic_optimizations_pixelshader.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
atomic_optimizations_raw_buffer.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
atomic_optimizations_struct_buffer.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
atomic_store_local.ll
AMDGPU: Add atomic bfloat load/store codegen tests
2024-04-25 16:08:11 +02:00
atomic-optimizer-promote-i8.ll
AMDGPU: Fix creating illegally typed readfirstlane in atomic optimizer (#128388)
2025-02-24 18:39:49 +07:00
atomic-optimizer-strict-wqm.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
atomic-oversize.ll
[AMDGPU] Set MaxAtomicSizeInBitsSupported. (#75185)
2023-12-18 16:51:06 -05:00
atomicrmw-expand.ll
AMDGPU: Stop emitting an error on illegal addrspacecasts (#127487)
2025-02-17 21:03:50 +07:00
atomicrmw-nand.ll
[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)
2023-12-15 12:33:32 +01:00
atomics_cond_sub.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
atomics-cas-remarks-gfx90a.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
atomics-hw-remarks-gfx90a.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
attr-amdgpu-flat-work-group-size-vgpr-limit.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
attr-amdgpu-flat-work-group-size.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
attr-amdgpu-max-num-workgroups-propagate.ll
[AMDGPU][Attributor] Make AAAMDWavesPerEU honor existing attribute (#114438)
2024-12-11 16:50:06 -05:00
attr-amdgpu-max-num-workgroups.ll
AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups (#113751)
2024-11-05 12:50:44 -08:00
attr-amdgpu-num-sgpr.ll
…
attr-amdgpu-num-vgpr.ll
…
attr-amdgpu-num-workgroups_error_check.ll
[AMDGPU] Adding the amdgpu_num_work_groups function attribute (#79035)
2024-03-12 10:30:39 -07:00
attr-amdgpu-waves-per-eu.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
attr-unparseable.ll
…
attributor-flatscratchinit-globalisel.ll
Reapply "[AMDGPU] Infer amdgpu-no-flat-scratch-init attribute in AMDGPUAttributor (#94647)" (#118907)
2024-12-09 16:44:48 -08:00
attributor-flatscratchinit.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
attributor-loop-issue-58639.ll
[AMDGPU][Attributor] Make AAAMDWavesPerEU honor existing attribute (#114438)
2024-12-11 16:50:06 -05:00
attributor-noopt.ll
[FIX][AMDGPU] Fix test case failures that caused by reapply of #112403
2024-11-08 20:38:42 -05:00
av_spill_cross_bb_usage.mir
[MachineFrameInfo] Refactoring around computeMaxcallFrameSize() (NFC) (#78001)
2024-03-18 10:37:59 -04:00
av-spill-expansion-with-machine-cp.mir
[AMDGPU] Mark AGPR tuple implicit in the first instr of AGPR spills. (#115285)
2024-12-12 19:47:17 +05:30
back-off-barrier-subtarget-feature.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
barrier-elimination-gfx12.ll
[AMDGPU] Optimize out s_barrier_signal/_wait (#116993)
2024-11-26 10:04:32 +01:00
barrier-elimination.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
basic-branch.ll
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
basic-call-return.ll
…
basic-loop.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
bb-prolog-spill-during-regalloc.ll
[AMDGPU] Include WWM register spill into BB Prolog (#111496)
2024-10-08 15:13:12 +05:30
bf16-conversions.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
bf16-ops.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
bf16.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
bfe_uint.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
bfe-combine.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
bfe-patterns.ll
Revert "AMDGPU: Don't avoid clamp of bit shift in BFE pattern (#115372)" (#116091)
2024-11-13 14:01:21 -08:00
bfi_int.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
bfi_int.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
bfi_nested.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
bfm.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
big_alu.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
bitcast_vector_bigint.ll
DAG: Avoid stack usage in bitcast operand promotion to legal vector (#125637)
2025-02-04 16:43:42 +07:00
bitcast-constant-to-vector.ll
…
bitcast-v4f16-v4i16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
bitcast-vector-extract.ll
[SelectionDAG] Preserve volatile undef stores. (#99918)
2024-07-24 08:41:56 -04:00
bitop3.ll
[AMDGPU] Allow selection of BITOP3 for some 2 opcodes and B32 cases (#122267)
2025-01-10 07:49:11 +01:00
bitreverse-inline-immediates.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
bitreverse.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
blender-coalescer-verifier-error-empty-subrange.mir
[CodeGen][NewPM] Port RegisterCoalescer to NPM (#124698)
2025-02-03 13:41:51 +07:00
blender-no-live-segment-at-def-implicit-def.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
block-should-not-be-in-alive-blocks.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
br_cc.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
branch-condition-and.ll
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
branch-folder-requires-no-phis.mir
…
branch-folding-implicit-def-subreg.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
branch-relax-bundle.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
branch-relax-indirect-branch.mir
[AMDGPU][True16] Remove the VGPR_LO/HI16 register classes. (#76500)
2023-12-29 12:13:24 +00:00
branch-relax-no-terminators.mir
[AMDGPU][True16] Remove the VGPR_LO/HI16 register classes. (#76500)
2023-12-29 12:13:24 +00:00
branch-relax-spill.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
branch-relaxation-debug-info.mir
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
branch-relaxation-gfx10-branch-offset-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
branch-relaxation-inst-size-gfx10.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
branch-relaxation.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
branch-uniformity.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
break-smem-soft-clauses.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
break-vmem-soft-clauses.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
bswap.ll
[AMDGPU][True16][CodeGen] true16 codegen for bswap (#122849)
2025-01-17 09:36:55 -05:00
buffer-atomic-fadd.f32-no-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-atomic-fadd.f32-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-atomic-fadd.f64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-atomic-fadd.v2f16-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-fat-pointer-atomicrmw-fadd.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-fat-pointer-atomicrmw-fmax.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
buffer-fat-pointer-atomicrmw-fmin.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
buffer-fat-pointers-contents-legalization.ll
DAG: Avoid stack usage in bitcast operand promotion to legal vector (#125637)
2025-02-04 16:43:42 +07:00
buffer-fat-pointers-memcpy.ll
[AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621)
2025-02-26 16:03:32 -06:00
buffer-intrinsic-mmo-type.ll
AMDGPU: Fix using wrong memory type for non-image resource intrinsics (#94911)
2024-06-13 11:10:28 +02:00
buffer-intrinsics-mmo-offsets.ll
[SelectionDAG] Use the nuw flag when expanding loads. (#119288)
2024-12-10 06:28:09 -08:00
buffer-rsrc-ptr-ops.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
buffer-schedule.ll
[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (#93801)
2024-06-10 12:14:51 +01:00
bug-cselect-b64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
bug-deadlanes.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
bug-sdag-emitcopyfromreg.ll
[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)
2024-09-19 09:00:21 +02:00
bug-sdag-scheduler-cycle.ll
…
bug-v4f64-subvector.ll
AMDGPU/NewPM: Fill out addPreISelPasses (#102814)
2024-08-14 20:57:00 +04:00
bug-vopc-commute.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
build_vector-r600.ll
[AMDGPU] Auto-generating lit test patterns (NFC) (#93837)
2024-06-07 09:02:18 +05:30
build_vector.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
build-vector-insert-elt-infloop.ll
…
build-vector-packed-partial-undef.ll
…
bundle-latency.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
bypass-div.ll
Reapply [AMDGPU] prevent shrinking udiv/urem if either operand exceeds signed max (#119325)
2024-12-12 15:24:34 -05:00
byval-frame-setup.ll
…
call_fs.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
call-alias-register-usage0.ll
[AMDGPU] Change scope of resource usage info symbols (#114810)
2025-01-21 13:10:06 +00:00
call-alias-register-usage1.ll
[AMDGPU] Change scope of resource usage info symbols (#114810)
2025-01-21 13:10:06 +00:00
call-alias-register-usage2.ll
[AMDGPU] Change scope of resource usage info symbols (#114810)
2025-01-21 13:10:06 +00:00
call-alias-register-usage3.ll
[AMDGPU] Change scope of resource usage info symbols (#114810)
2025-01-21 13:10:06 +00:00
call-alias-register-usage-agpr.ll
[AMDGPU] Change scope of resource usage info symbols (#114810)
2025-01-21 13:10:06 +00:00
call-args-inreg-no-sgpr-for-csrspill-xfail.ll
[AMDGPU] Disable verifier in call-args-inreg-no-sgpr-for-csrspill-xfail.ll
2024-11-08 17:26:36 -05:00
call-args-inreg.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
call-argument-types.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
call-c-function.ll
…
call-constant.ll
…
call-constexpr.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
call-defs-mode-register.ll
[ConstraintFP] Model rounding control registers for inline asm (#92846)
2024-05-23 22:50:39 +08:00
call-encoding.ll
…
call-graph-register-usage.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
call-preserved-registers.ll
[NFC][AMDGPU] Auto generate check lines for three test cases (#127352)
2025-02-17 11:22:08 -05:00
call-reqd-group-size.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
call-return-types.ll
…
call-skip.ll
…
call-to-kernel-undefined.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
call-to-kernel.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
call-waitcnt.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
call-waw-waitcnt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
callee-frame-setup.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
callee-special-input-sgprs-fixed-abi.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
callee-special-input-vgprs-packed.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
callee-special-input-vgprs.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
calling-conventions.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
captured-frame-index.ll
AMDGPU: Do not fold copy to physreg from operation on frame index (#115977)
2024-11-12 21:35:51 -08:00
carryout-selection.ll
[AMDGPU] Add commute for some VOP3 inst (#121326)
2025-01-22 11:08:26 +07:00
cayman-loop-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
cc-sgpr-limit.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
cc-sgpr-over-limit.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
cc-update.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
cf_end.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
cf-loop-on-constant.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
cf-stack-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
cgp-addressing-modes-flat.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
cgp-addressing-modes-gfx908.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
cgp-addressing-modes-gfx1030.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
cgp-addressing-modes-smem.ll
[AMDGPU] Disallow negative s_load offsets in isLegalAddressingMode (#91327)
2024-06-25 17:43:00 +01:00
cgp-addressing-modes.ll
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
2024-02-09 09:20:25 +01:00
cgp-bitfield-extract.ll
[llvm] Remove br i1 undef in some llvm/test/CodeGen tests (#127368)
2025-02-16 18:44:46 +00:00
chain-hi-to-lo.ll
[AMDGPU][True16][CodeGen] flat/global/scratch load/store pseudo for true16 (#127945)
2025-02-21 17:06:48 -05:00
change-scc-to-vcc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
check-subtarget-features.ll
[AMDGPU] Remove wavefrontsize feature from GFX10+ (#98400)
2024-07-16 01:02:25 -07:00
clamp-modifier.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
clamp-omod-special-case.mir
AMDGPU: Don't fold clamp/omod modifiers without nofpexcept (#95950)
2024-06-18 23:55:49 +02:00
clamp.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
cluster_stores.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
cluster-flat-loads-postra.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
cluster-flat-loads.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
cmp_shrink.mir
[AMDGPU] Add commute for some VOP3 inst (#121326)
2025-01-22 11:08:26 +07:00
cndmask-no-def-vcc.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
coalesce-identity-copies-undef-subregs.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
coalesce-into-dead-subreg-copies.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
coalesce-liveout-undef-copy.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
coalesce-vgpr-alignment.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
coalescer_distribute.ll
…
coalescer_remat.ll
…
coalescer-early-clobber-subreg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
coalescer-extend-pruned-subrange.mir
…
coalescer-identical-values-undef.mir
…
coalescer-remat-dead-use.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
coalescer-removepartial-extend-undef-subrange.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
coalescer-subranges-another-copymi-not-live.mir
…
coalescer-subranges-another-prune-error.mir
…
coalescer-subranges-prune-kill-copy.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
coalescer-subreg-join.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
coalescer-subregjoin-fullcopy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
coalescer-undef-subreg-use-invalid-lanemask.mir
RegisterCoalescer: Fix creating full / empty subrange on undef subreg use (#117936)
2024-11-28 11:12:19 -05:00
coalescer-with-subregs-bad-identical.mir
…
coalescing_makes_lanes_undef.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
coalescing-subreg-was-undef-but-became-def.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
coalescing-with-subregs-in-loop-bug.mir
[CodeGen][NewPM] Port RenameIndependentSubregs to NPM (#125192)
2025-02-05 17:54:57 +05:30
code-object-v3.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
code-size-estimate.ll
[AMDGPU] Add some gfx1200 test coverage
2024-06-27 14:53:59 +01:00
code-size-estimate.mir
[AMDGPU] Respect MBB alignment in the getFunctionCodeSize() (#127142)
2025-02-18 13:19:33 -08:00
codegen-internal-only-func.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
codegen-prepare-addrmode-sext.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
codegen-prepare-addrspacecast-non-null-vector.ll
[AMDGPU] Improve detection of non-null addrspacecast operands (#82311)
2024-03-01 14:01:10 +01:00
codegen-prepare-addrspacecast-non-null.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
collapse-endcf2.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
collapse-endcf-broken.mir
[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)
2025-02-20 17:35:56 +05:30
collapse-endcf.ll
[AMDGPU] Skip non-wwm reg implicit-def from bb prolog (#115834)
2024-11-12 23:30:57 +05:30
collapse-endcf.mir
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
combine_andor_with_cmps.ll
Revert "Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on targets using scratch instructions for stack #78226" (#86273)
2024-03-26 11:01:08 +01:00
combine_vloads.ll
[AMDGPU] Remove duplicate -mtriple options in tests (#91576)
2024-05-09 10:59:25 +01:00
combine-add-zext-xor.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-and-sext-bool.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-cond-add-sub.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
combine-ftrunc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-reg-or-const.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
combine-sreg64-inits.mir
[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)
2025-02-11 11:09:38 +05:30
combine-vload-extract.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
comdat.ll
…
commute_modifiers.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
commute-compares-scalar-float.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
commute-compares.ll
AMDGPU: Default to selecting frame indexes to SGPRs (#115060)
2024-11-08 19:01:59 -08:00
commute-frame-index-operand.mir
AMDGPU: Fix illegal commute with frame index (#114497)
2024-11-01 10:02:29 -07:00
commute-op-sel.mir
[AMDGPU] Add commute for some VOP3 inst (#121326)
2025-01-22 11:08:26 +07:00
commute-shifts.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
commute-vop3.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
complex-folding.ll
…
computeKnownBits-scalar-to-vector-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
computeNumSignBits-mul.ll
…
concat_vectors.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
constant-address-space-32bit.ll
[SeperateConstOffsetFromGEP] Handle or disjoint flags (#76997)
2024-01-26 09:56:06 -06:00
constant-fold-imm-immreg.mir
AMDGPU: Handle subregister uses in SIFoldOperands constant folding (#127485)
2025-02-18 17:19:53 +07:00
constant-fold-mi-operands.ll
…
constrained-shift.ll
[TableGen][GISel] Import more "multi-level" patterns (#120332)
2024-12-18 14:44:55 +03:00
control-flow-fastregalloc.ll
[AMDGPU] Include WWM register spill into BB Prolog (#111496)
2024-10-08 15:13:12 +05:30
control-flow-optnone.ll
…
convergence-laneops.ll
[AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (#89217)
2024-06-25 14:35:19 +05:30
convergence-tokens.ll
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
convergent-inlineasm.ll
[CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (#126807)
2025-02-25 15:29:12 -08:00
copy_phys_vgpr64.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
copy_to_scc.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
copy-hoist-no-spills.ll
[MachineLICM] Hoist COPY instruction only when user can be hoisted (#81735)
2024-02-27 12:31:29 +00:00
copy-illegal-type.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
copy-overlap-sgpr-kill.mir
…
copy-overlap-vgpr-kill.mir
…
copy-phys-reg-implicit-operand-kills-subregs.mir
…
copy-to-reg-frameindex.ll
[amdgpu][nfc] Post-commit feedback on c39fba209
2025-01-30 20:07:44 +00:00
copy-to-reg-scc-clobber.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
copy-to-reg.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
copy-vgpr-clobber-spill-vgpr.mir
AMDGPU: Infer no-agpr usage in AMDGPUAttributor (#85948)
2024-03-21 14:24:06 +05:30
copyprop_regsequence_with_undef.mir
[CodeGen][NewPM] Port MachineCSE pass to new pass manager. (#106605)
2024-09-04 18:54:07 +05:30
copysign-simplify-demanded-bits.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
couldnt-join-subrange-3.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
cross-block-use-is-not-abi-copy.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
cse-convergent.ll
[AMDGPU] V_SET_INACTIVE optimizations (#98864)
2024-09-05 14:39:28 +09:00
cse-phi-incoming-val.ll
[test] Remove immarg parameter attribute from calls (#97432)
2024-07-03 09:02:31 +01:00
csr-gfx10.ll
…
csr-sgpr-spill-live-ins.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
ctlz_zero_undef.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
ctlz.ll
[AMDGPU] Add commute for some VOP3 inst (#121326)
2025-01-22 11:08:26 +07:00
ctpop16.ll
DAG: Avoid stack usage in bitcast operand promotion to legal vector (#125637)
2025-02-04 16:43:42 +07:00
ctpop64.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
ctpop.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
cttz_zero_undef.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
cttz.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
cube.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
cvt_f32_ubyte.ll
[AMDGPU] Add commute for some VOP3 inst (#121326)
2025-01-22 11:08:26 +07:00
cvt_flr_i32_f32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
cvt_rpi_i32_f32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
dag-divergence-atomic.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
dag-divergence.ll
SelectionDAG: Do not propagate divergence through copy glue (#101210)
2024-07-31 00:04:58 +04:00
dag-preserve-disjoint-flag.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
dagcomb-extract-vec-elt-different-sizes.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
dagcomb-mullohi.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
dagcomb-shuffle-vecextend-non2.ll
[llvm] Remove br i1 undef from some llvm/test/CodeGen tests (#128272)
2025-02-23 09:23:33 +00:00
dagcombine-fma-crash.ll
[SDAG] Intersect poison-generating flags after CSE (#97434)
2024-07-03 20:32:46 +08:00
dagcombine-fma-fmad.ll
[AMDGPU] SIWholeQuadMode: Ensure earliest WQM entry point for PS (#123266)
2025-01-19 15:50:33 +09:00
dagcombine-fmul-sel.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
dagcombine-lshr-and-cmp.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
dagcombine-reassociate-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
dagcombine-select.ll
[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)
2024-09-19 09:00:21 +02:00
dagcombine-setcc-select.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
dagcombine-v1i8-extractvecelt-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
dbg-value-ends-sched-region.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
dce-disjoint-intervals.mir
…
dead_bundle.mir
[AMDGPU] Remove duplicate -mtriple options in tests (#91576)
2024-05-09 10:59:25 +01:00
dead_copy.mir
[CodeGen][NewPM] Port MachineCopyPropagation to NPM (#125202)
2025-02-04 15:45:03 +05:30
dead-lane.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
dead-machine-elim-after-dead-lane.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
debug_frame.ll
…
debug-value2.ll
[LiveDebugVariables] Fix a DBG_VALUE reordering issue (#111124)
2024-10-15 11:36:24 +02:00
debug-value-scheduler-crash.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
debug-value-scheduler-liveins.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
debug-value-scheduler.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
debug-value.ll
…
debug.ll
…
default-flat-work-group-size-overrides-waves-per-eu.ll
…
default-fp-mode.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
detect-dead-lanes.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
direct-indirect-call.ll
[AMDGPU][Attributor] Make AAAMDWavesPerEU honor existing attribute (#114438)
2024-12-11 16:50:06 -05:00
directive-amdgcn-target.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
disable_form_clauses.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
disconnected-predset-break-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
div_i128.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
div_v2i128.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
div-rem-by-constant-64.ll
PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)
2025-01-30 20:42:02 +07:00
diverge-extra-formal-args.ll
…
diverge-interp-mov-lower.ll
…
diverge-switch-default.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
divergence-at-use.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
divergence-driven-abs.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
divergence-driven-bfe-isel.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
divergence-driven-bitreverse.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
divergence-driven-buildvector.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
divergence-driven-ctlz-cttz.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
divergence-driven-ctpop.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
divergence-driven-min-max.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
divergence-driven-negsubinlineconst.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
divergence-driven-not-isel.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
divergence-driven-sext-inreg.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
divergence-driven-trunc-to-i1.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
divergence-driven-xnor.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
divergent-branch-uniform-condition.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
divrem24-assume.ll
…
do-not-unify-divergent-exit-nodes-with-musttail.ll
[AMDGPU] Don't unify divergent exit nodes with musttail calls (#126395)
2025-02-09 21:48:24 -05:00
dpp64_combine.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
dpp64_combine.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
dpp_combine_gfx11.mir
[AMDGPU][True16][MC] VOP3 profile in True16 format (#109031)
2024-10-16 10:27:44 -04:00
dpp_combine.ll
[AMDGPU] Add a negative test for DPP combine into v_mul_lo_u32
2024-05-22 16:08:44 +01:00
dpp_combine.mir
AMDGPU/NewPM Port GCNDPPCombine to NPM (#105816)
2024-08-29 14:49:52 +05:30
drop-mem-operand-move-smrd.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ds_gws_align.ll
[TwoAddressInstruction] Recompute live intervals for partial defs (#74431)
2024-01-12 13:26:01 +09:00
ds_read2_offset_order.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ds_read2_superreg.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ds_read2.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
ds_read2st64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ds_write2.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
ds_write2st64.ll
…
ds-alignment.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
ds-combine-large-stride.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
ds-combine-with-dependence.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
ds-negative-offset-addressing-mode-loop.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ds-sub-offset.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
ds-vectorization-alignment.ll
…
dst-sel-hazard.mir
[AMDGPU] Introduce a new generic target gfx9-4-generic (#115190)
2024-11-12 23:11:05 -05:00
dual-source-blend-export.ll
[test] Remove immarg parameter attribute from calls (#97432)
2024-07-03 09:02:31 +01:00
dummy-regalloc-priority-advisor.mir
RegAllocGreedy: Add dummy priority advisor for writing MIR tests (#121207)
2025-01-02 23:04:44 +07:00
dumpcode.ll
[AMDGPU] Add a regression test for -mattr=dumpcode (#116982)
2025-02-13 11:04:08 +00:00
duplicate-attribute-indirect.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
dwarf-multi-register-use-crash.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
dynamic_stackalloc.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
early-if-convert-cost.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
early-if-convert.ll
[CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (#126807)
2025-02-25 15:29:12 -08:00
early-inline-alias.ll
…
early-inline.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
early-lis-two-address-partial-def.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
early-tailduplicator-nophis.mir
[CodeGen][NewPM] Port TailDuplicate pass to NPM (#113293)
2024-10-30 11:48:40 +05:30
early-tailduplicator-terminator.mir
[CodeGen][NewPM] Port TailDuplicate pass to NPM (#113293)
2024-10-30 11:48:40 +05:30
early-term.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
eh_frame.ll
…
elf-header-flags-mach.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
elf-header-flags-sramecc.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
elf-header-flags-xnack.ll
…
elf-header-osabi.ll
[AMDGPU] Introduce Code Object V6 (#76954)
2024-02-05 08:19:53 +01:00
elf-notes.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
elf.ll
…
elf.metadata.ll
…
elf.r600.ll
…
eliminate-frame-index-s-add-i32.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
eliminate-frame-index-s-mov-b32.mir
[AMDGPU] Optimize the register uses if offset inlinable (#101676)
2024-08-05 12:49:33 +05:30
eliminate-frame-index-scalar-bit-ops.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
eliminate-frame-index-v-add-co-u32-wave32.mir
AMDGPU: Handle v_add* in eliminateFrameIndex (#102346)
2024-10-02 21:19:45 +04:00
eliminate-frame-index-v-add-co-u32.mir
AMDGPU: Correct legal literal operand logic for multiple uses (#127594)
2025-02-18 19:58:42 +07:00
eliminate-frame-index-v-add-u32.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
else.ll
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
empty-function.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
enable-no-signed-zeros-fp-math.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
enable-scratch-only-dynamic-stack.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
endcf-loop-header.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
endpgm-dce.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
enqueue-kernel.ll
[AMDGPU][NewPM] Port AMDGPUOpenCLEnqueuedBlockLowering to NPM (#122434)
2025-01-13 17:52:30 +05:30
exceed-max-sgprs.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
exec-mask-opt-cannot-create-empty-or-backward-segment.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
expand-atomicrmw-syncscope.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
expand-scalar-carry-out-select-user.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
expand-si-indirect.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
expand-variadic-call.ll
CodeGen: Remove redundant REQUIRES registered-target from tests (#111982)
2024-10-11 16:16:12 +04:00
extend-bit-ops-i16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
extend-phi-subrange-not-in-parent.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
extend-wwm-virt-reg-liveness.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
extload-align.ll
…
extload-private.ll
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
2024-02-09 09:20:25 +01:00
extload.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
extra-lds-size.ll
AMDGPU: Increase the LDS size to support to 160 KB for gfx950 (#116309)
2024-11-18 10:48:56 -08:00
extra-sroa-after-unroll.ll
…
extract_subvector_vec4_vec3.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
extract_vector_dynelt.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
extract_vector_elt-f16.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
extract_vector_elt-f64.ll
…
extract_vector_elt-i8.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
extract_vector_elt-i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
extract_vector_elt-i64.ll
…
extract-load-i1.ll
[LegalizeTypes] Handle non byte-sized elt types when splitting INSERT/EXTRACT_VECTOR_ELT (#93357)
2024-06-13 11:09:18 +02:00
extract-lowbits.ll
AMDGPU: Update pattern matching from "x&(-1>>(32-y))" to "bfe x, 0, y" (#116115)
2024-11-14 12:21:34 -08:00
extract-subvector-16bit.ll
[AMDGPU] Reland: Add IR LiveReg type-based optimization
2024-07-03 09:26:19 -07:00
extract-subvector-equal-length.ll
…
extract-subvector.ll
[AMDGPU] Reland: Add IR LiveReg type-based optimization
2024-07-03 09:26:19 -07:00
extract-vector-elt-build-vector-combine.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
extractelt-to-trunc.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fabs-r600.ll
[AMDGPU] Auto-generated some lit test patterns (NFC). (#94310)
2024-06-07 09:07:11 +05:30
fabs.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fabs.f64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fabs.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fadd64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fadd-fma-fmul-combine.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fadd.f16.ll
[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)
2025-02-25 17:09:34 -05:00
fadd.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fast-ra-kills-vcc.mir
[NewPM][CodeGen] Port regallocfast to new pass manager (#94426)
2024-06-07 12:22:42 +08:00
fast-regalloc-bundles.mir
[NewPM][CodeGen] Port regallocfast to new pass manager (#94426)
2024-06-07 12:22:42 +08:00
fast-unaligned-load-store.global.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fast-unaligned-load-store.private.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
fastregalloc-illegal-subreg-physreg.mir
[NewPM][CodeGen] Port regallocfast to new pass manager (#94426)
2024-06-07 12:22:42 +08:00
fastregalloc-self-loop-heuristic.mir
[NewPM][CodeGen] Port regallocfast to new pass manager (#94426)
2024-06-07 12:22:42 +08:00
fastregalloc-sgpr-only.mir
…
fcanonicalize-elimination.ll
[AMDGPU] Fix canonicalization of truncated values. (#83054)
2024-03-13 12:08:39 +00:00
fcanonicalize.f16.ll
[AMDGPU][True16][CodeGen] flat/global/scratch load/store pseudo for true16 (#127945)
2025-02-21 17:06:48 -05:00
fcanonicalize.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fceil64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fceil.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fcmp64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fcmp-cnd.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fcmp-cnde-int-args.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fcmp.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00
fcmp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fconst64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fcopysign.f16.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
fcopysign.f32.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fcopysign.f32.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fcopysign.f64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fdiv32-to-rcp-folding.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fdiv_flags.f32.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
fdiv-nofpexcept.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
fdiv.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fdiv.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fdiv.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fdot2.ll
[AMDGPU] Fix FMA combine (#119217)
2024-12-10 10:11:19 +01:00
fence-barrier.ll
[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)
2023-12-15 12:33:32 +01:00
fence-lds-read2-write2.ll
[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)
2023-12-15 12:33:32 +01:00
fetch-limits.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fetch-limits.r700+.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ffloor.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ffloor.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fix-crash-valu-hazard.ll
[AMDGPU] Fix crash due to missing check for FLAT instructions that dont use vector registers when computing VALU hazard (#123627)
2025-01-21 05:50:58 -08:00
fix-frame-ptr-reg-copy-livein.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fix-frame-reg-in-custom-csr-spills.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
fix-sgpr-copies-f16-fake16.mir
[AMDGPU][True16][MC] VOPC profile fake16 pseudo update (#113175)
2024-11-22 12:12:13 -05:00
fix-sgpr-copies-f16-true16.mir
[AMDGPU][True16][MC] true16 for v_cmp_lt_f16 (#122499)
2025-01-14 10:03:36 -05:00
fix-sgpr-copies-f16.mir
[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)
2025-02-19 11:37:24 -05:00
fix-sgpr-copies-nondeterminism.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
fix-sgpr-copies.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fix-vgpr-copies.mir
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)
2025-01-21 15:27:46 +05:30
fix-wwm-vgpr-copy.ll
[AMDGPU] V_SET_INACTIVE optimizations (#98864)
2024-09-05 14:39:28 +09:00
flat_atomics_i32_system.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
flat_atomics_i64_noprivate.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
flat_atomics_i64_system_noprivate.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
flat_atomics_i64_system.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
flat_atomics_i64.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
flat_atomics.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
flat-address-space.ll
[AMDGPU][True16][CodeGen] reopen "FLAT_load using D16 pseudo instruction" (#127673)
2025-02-18 18:16:23 -05:00
flat-atomic-fadd.f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
flat-atomic-fadd.f64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
flat-atomicrmw-fadd.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
flat-atomicrmw-fmax.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
flat-atomicrmw-fmin.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
flat-atomicrmw-fsub.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
flat-error-unsupported-gpu-hsa.ll
…
flat-for-global-subtarget-feature.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
flat-load-clustering.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
flat-offset-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
flat-scratch-fold-fi.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
flat-scratch-i8-i16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
flat-scratch-init.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
flat-scratch-reg.ll
Reapply "[AMDGPU] Infer amdgpu-no-flat-scratch-init attribute in AMDGPUAttributor (#94647)" (#118907)
2024-12-09 16:44:48 -08:00
flat-scratch-svs.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
flat-scratch.ll
[AMDGPU][True16][CodeGen] flat/global/scratch load/store pseudo for true16 (#127945)
2025-02-21 17:06:48 -05:00
floor.ll
…
fma-combine.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fma.f16.ll
[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)
2025-02-25 17:09:34 -05:00
fma.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fma.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fmac.sdwa.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmad-formation-fmul-distribute-denormal-mode.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmad.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmax3.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmax3.ll
[AMDGPU][True16[MC] true16 for v_max3/min3_num_f16 (#121510)
2025-01-03 08:55:58 +00:00
fmax_legacy.f16.ll
…
fmax_legacy.f64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fmax_legacy.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmax.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmaximum3.ll
AMDGPU: Form v2f16 minimum3/maximum3 on gfx950 (#128123)
2025-02-21 12:11:51 +07:00
fmaximum.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
fmaxnum.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmaxnum.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
fmaxnum.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmed3-cast-combine.ll
[TargetLowering] Be more efficient in fp -> bf16 NaN conversions
2024-02-21 22:47:27 +00:00
fmed3.ll
[AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (#128784)
2025-02-25 20:04:57 -05:00
fmin3.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
fmin_fmax_legacy.amdgcn.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmin_legacy.f16.ll
…
fmin_legacy.f64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fmin_legacy.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmin.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fminimum3.ll
AMDGPU: Form v2f16 minimum3/maximum3 on gfx950 (#128123)
2025-02-21 12:11:51 +07:00
fminimum.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
fminnum.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fminnum.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
fminnum.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmul64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmul-2-combine-multi-use.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fmul-to-ldexp.ll
[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)
2025-01-06 17:42:38 +05:30
fmul.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)
2025-02-26 10:50:49 -05:00
fmul.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
fmuladd.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fmuladd.f32.ll
…
fmuladd.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmuladd.v2f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fnearbyint.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fneg-combines-gfx1200.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fneg-combines.f16.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
fneg-combines.legal.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fneg-combines.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fneg-combines.new.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fneg-combines.si.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fneg-fabs-divergence-driven-isel.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
fneg-fabs-r600.ll
[AMDGPU] Auto-generated some lit test patterns (NFC). (#94310)
2024-06-07 09:07:11 +05:30
fneg-fabs.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fneg-fabs.f64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fneg-fabs.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fneg-fold-legalize-dag-increase-insts.ll
…
fneg-modifier-casting.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
fneg.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fneg.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fneg.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fold_acc_copy_into_valu.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-agpr-phis.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
fold-cndmask-wave32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-cndmask.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-fabs.ll
ValueTracking: Treat poison more aggressively in computeKnownFPClass (#87990)
2024-04-15 12:51:29 +02:00
fold-fi-mubuf.mir
…
fold-fi-operand-shrink.mir
AMDGPU: Handle folding frame indexes into add with immediate (#110738)
2024-10-19 12:33:03 -07:00
fold-fmaak-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-fmul-to-neg-abs.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-imm-copy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-imm-f16-f32.mir
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
fold-immediate-operand-shrink-with-carry.mir
…
fold-immediate-operand-shrink.mir
…
fold-immediate-output-mods.mir
[CodeGen][NewPM] Port PeepholeOptimizer to NPM (#116326)
2024-11-18 11:02:01 +05:30
fold-implicit-operand.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-int-pow2-with-fmul-or-fdiv.ll
[AMDGPU] Adopt new lowering sequence for fdiv16 (#109295)
2024-10-08 09:49:20 -04:00
fold-literal-multiple-gfx10.mir
AMDGPU: Correct legal literal operand logic for multiple uses (#127594)
2025-02-18 19:58:42 +07:00
fold-multiple-commute.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-multiple.mir
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
fold-omod-crash.mir
[AMDGPU] Fix machine verification failure after SIFoldOperandsImpl::tryFoldOMod (#113544)
2024-10-29 14:59:37 +00:00
fold-operands-frame-index.gfx10.mir
AMDGPU: Handle folding frame indexes into add with immediate (#110738)
2024-10-19 12:33:03 -07:00
fold-operands-frame-index.mir
AMDGPU: Handle folding frame indexes into add with immediate (#110738)
2024-10-19 12:33:03 -07:00
fold-operands-order.mir
…
fold-operands-remove-m0-redef.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-operands-s-add-copy-to-vgpr.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
fold-operands-scalar-fmac.mir
AMDGPU: Teach isOperandLegal about SALU literal restrictions (#127626)
2025-02-19 10:53:03 +07:00
fold-over-exec.mir
…
fold-readlane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
fold-reload-into-exec.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
fold-reload-into-m0.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
fold-restore-undef-use.mir
Reapply "Move assertion for AdjustsStack from PEI to MachineVerifier (#85698)"
2024-03-21 20:24:57 -04:00
fold-sgpr-copy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-sgpr-multi-imm.mir
AMDGPU: Teach isOperandLegal about SALU literal restrictions (#127626)
2025-02-19 10:53:03 +07:00
fold-short-64-bit-literals.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fold-vgpr-copy.mir
AMDGPU: Correct legal literal operand logic for multiple uses (#127594)
2025-02-18 19:58:42 +07:00
fold-vgpr-phyreg.mir
…
fold-zero-high-bits-clear-kill-flags.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
folding-of-i32-as-i64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
force-alwaysinline-lds-global-address-codegen.ll
…
force-alwaysinline-lds-global-address.ll
[IR] Remove support for icmp and fcmp constant expressions (#93038)
2024-06-04 08:31:03 +02:00
fp16_to_fp32.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fp16_to_fp64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fp32_to_fp16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fp64-atomics-gfx90a.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
fp64-min-max-buffer-atomics.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fp64-min-max-buffer-ptr-atomics.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fp_to_sint.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fp_to_sint.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fp_to_uint.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fp_to_uint.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fp_trunc_store_fp32_to_bf16.ll
[AMDGPU][ISel] Add more trunc store actions regarding bf16 (#90493)
2024-04-29 18:27:52 -04:00
fp_trunc_store_fp64_to_bf16.ll
[AMDGPU][ISel] Add more trunc store actions regarding bf16 (#90493)
2024-04-29 18:27:52 -04:00
fp-atomic-to-s_denormmode.mir
AMDGPU: Create pseudo to real mapping for flat/buffer atomic fmin/fmax (#95591)
2024-06-18 10:34:09 +02:00
fp-atomics-gfx942.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
fp-atomics-gfx950.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
fp-atomics-gfx1200.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
fp-classify.ll
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00
fp-min-max-buffer-atomics.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fp-min-max-buffer-ptr-atomics.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fp-min-max-image-atomics.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fp-min-max-num-flat-atomics.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
fp-min-max-num-global-atomics.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
fpenv.ll
[AMDGPU] Implement 'llvm.get.fpenv' and 'llvm.set.fpenv' (#83906)
2024-03-06 08:11:54 -06:00
fpext-free.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fpext.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fpext.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fpow.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fptoi.i128.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
fptosi.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fptoui.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fptrunc.f16.ll
AMDGPU: Add support for V_CVT_PK_F16_F32 instruction for gfx950 (#118300)
2024-12-02 16:04:24 -05:00
fptrunc.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
fract-match.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
fract.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fract.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
frame-index-elimination-tied-operand.mir
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
2024-02-09 09:20:25 +01:00
frame-index-elimination.ll
AMDGPU: Fix using illegal VOP3 literal in frame index elimination (#115747)
2024-11-13 08:01:01 -08:00
frame-index.mir
AMDGPU: Handle v_add* in eliminateFrameIndex (#102346)
2024-10-02 21:19:45 +04:00
frame-lowering-entry-all-sgpr-used.mir
…
frame-lowering-fp-adjusted.mir
…
frame-setup-without-sgpr-to-vgpr-spills.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
freeze.ll
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
frem.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
frexp-constant-fold.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fshl.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fshr.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fsqrt.f32.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
fsqrt.f64.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
fsqrt.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fsub64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fsub-as-fneg-src-modifier.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2024-02-05 09:29:31 -05:00
fsub.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fsub.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ftrunc.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ftrunc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
function-args-inreg.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
function-args.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
function-call-relocs.ll
…
function-resource-usage.ll
[AMDGPU] Newly added test modified for recent SGPR use change (#116427)
2024-11-15 14:51:58 -05:00
function-returns.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
fused-bitlogic.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
gds-allocation.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
gds-atomic.ll
[AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (#76955)
2024-02-12 10:18:20 +01:00
gds-unsupported.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
generic-targets-require-v6.ll
[AMDGPU] Introduce a new generic target gfx9-4-generic (#115190)
2024-11-12 23:11:05 -05:00
gep-address-space.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
gep-const-address-space.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
gep-flags-stack-offsets.ll
AMDGPU: Regenerate test checks
2024-10-09 16:39:15 +04:00
gfx10-twoaddr-fma.mir
AMDGPU: Update live intervals in convertToThreeAddress (#104610)
2024-09-06 18:18:27 +04:00
gfx10-vop-literal.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
gfx11-twoaddr-fma.mir
[AMDGPU][True16][MC] true16 for v_fma_f16 (#119477)
2025-01-06 15:02:04 -05:00
gfx11-user-sgpr-init16-bug.ll
[FIX][AMDGPU] Fix test case failures that caused by reapply of #112403
2024-11-08 20:38:42 -05:00
gfx12_scalar_subword_loads.ll
[AMDGPU][AMDGPURegBankInfo] Map S_BUFFER_LOAD_XXX to its corresponding BUFFER_LOAD_XXX (#117574)
2024-12-16 10:24:33 +01:00
gfx90a-enc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
gfx902-without-xnack.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
gfx942-hazards.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
gfx-call-non-gfx-func.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
gfx-callable-argument-types.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
gfx-callable-preserved-registers.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
gfx-callable-return-types.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
global_atomic_optimizer_fp_rtn.ll
AMDGPU: Handle new atomicrmw metadata for fadd case (#96760)
2024-08-02 19:41:33 +04:00
global_atomics_i32_system.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
global_atomics_i64_system.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
global_atomics_i64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
global_atomics_iterative_scan_fp.ll
[AMDGPU] Cleanup bitcast spam in atomic optimizer (#96933)
2024-07-08 10:53:16 +05:30
global_atomics_iterative_scan.ll
[AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (#89217)
2024-06-25 14:35:19 +05:30
global_atomics_optimizer_fp_no_rtn.ll
AMDGPU: Handle new atomicrmw metadata for fadd case (#96760)
2024-08-02 19:41:33 +04:00
global_atomics_scan_fadd.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
global_atomics_scan_fmax.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
global_atomics_scan_fmin.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
global_atomics_scan_fsub.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
global_atomics.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
global_smrd_cfg.ll
…
global_smrd.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
global-alias.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
global-atomic-fadd.f32-no-rtn.ll
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
global-atomic-fadd.f32-rtn.ll
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
global-atomic-fadd.f64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-atomic-fadd.v2f16-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-atomic-scan.ll
[AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (#89217)
2024-06-25 14:35:19 +05:30
global-atomicrmw-fadd-wrong-subtarget.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
global-atomicrmw-fadd.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-atomicrmw-fmax.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
global-atomicrmw-fmin.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
global-atomicrmw-fsub.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-atomics-fp-wrong-subtarget.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
global-constant.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
global-directive.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
global-extload-i16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
global-i16-load-store.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
global-load-saddr-to-vaddr.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
global-saddr-atomics-min-max-system.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
global-saddr-atomics.gfx908.ll
AMDGPU: Remove global/flat atomic fadd intrinics (#97051)
2024-08-22 23:27:33 +04:00
global-saddr-atomics.gfx1030.ll
…
global-saddr-atomics.ll
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
global-saddr-load.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
global-saddr-store.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
global-smrd-unknown.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
global-variable-relocs.ll
…
greedy-alloc-fail-sgpr1024-spill.mir
Reapply "Move assertion for AdjustsStack from PEI to MachineVerifier (#85698)"
2024-03-21 20:24:57 -04:00
greedy-broken-ssa-verifier-error.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
greedy-global-heuristic.mir
Typos: 'maxium', 'minium'
2023-10-23 10:42:28 +02:00
greedy-instruction-split-subrange.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
greedy-liverange-priority.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
greedy-remark-crash-unassigned-reg.mir
…
greedy-reverse-local-assignment.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
group-image-instructions.ll
[AMDGPU] Make max dwords of memory cluster configurable (#119342)
2024-12-18 14:17:27 +08:00
gv-const-addrspace.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
gv-offset-folding.ll
…
gws-hazards.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
half-alloca-promotion.ll
[AMDGPU] Fix a potential wrong return value indicating whether a pass modifies a function (#88197)
2024-04-12 09:34:46 -04:00
half.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
hard-clauses-img-gfx10.mir
[AMDGPU] Fix hard clausing for image instructions on gfx12 (#90221)
2024-04-29 11:42:36 +01:00
hard-clauses-img-gfx11.mir
[AMDGPU] Fix hard clausing for image instructions on gfx12 (#90221)
2024-04-29 11:42:36 +01:00
hard-clauses-img-gfx12.mir
[AMDGPU] Fix hard clausing for image instructions on gfx12 (#90221)
2024-04-29 11:42:36 +01:00
hard-clauses.mir
[AMDGPU] Fix hard clausing for image instructions on gfx12 (#90221)
2024-04-29 11:42:36 +01:00
hazard-buffer-store-v-interp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
hazard-flat-instruction-valu-check.mir
[AMDGPU] Fix crash due to missing check for FLAT instructions that dont use vector registers when computing VALU hazard (#123627)
2025-01-21 05:50:58 -08:00
hazard-hidden-bundle.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
hazard-in-bundle.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
hazard-inlineasm.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
hazard-kill.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
hazard-lds-addtid.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
hazard-pass-ordering.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
hazard-pseudo-machineinstrs.mir
…
hazard-recognizer-meta-insts.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
hazard-recognizer-src-shared-base.ll
[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)
2024-09-04 12:15:20 +09:00
hazard-shift64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
hazard.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
hazards-gfx950.mir
[AMDGPU] Handle hazard in v_scalef32_sr_fp4_* conversions (#118589)
2024-12-11 18:38:10 +05:30
high-bits-zeroed-16-bit-ops.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
high-RP-reschedule.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
hip.extern.shared.array.ll
…
hoist-cond.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
hsa-default-device.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-fp-mode.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-func-align.ll
…
hsa-func.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-generic-target-features.ll
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
hsa-globals.ll
[AMDGPU][MC] Use normal ELF syntax for section switching (#77267)
2024-01-09 14:13:42 -05:00
hsa-group-segment.ll
…
hsa-metadata-agpr-register-count.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
hsa-metadata-agpr-small.ll
…
hsa-metadata-deduced-arg-attr.ll
…
hsa-metadata-dynlds-func-hidden-args-v5.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-enqueue-kernel-.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-from-llvm-ctor-dtor-list.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-from-llvm-ir-full.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-heap-v5.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
hsa-metadata-hidden-args-v4.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-hidden-args-v5.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-hostcall-present-asan.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-hostcall-v4.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
hsa-metadata-hostcall-v5.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
hsa-metadata-images.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-invalid-ocl-version-1.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-invalid-ocl-version-3.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-kernel-code-props.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
hsa-metadata-multigrid-sync-arg-v5.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
hsa-metadata-queue-ptr-v5.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
hsa-metadata-queueptr-v5.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
hsa-metadata-resource-usage-function-ordering.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
hsa-metadata-uniform-workgroup-size-v5.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-metadata-wavefrontsize.ll
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
hsa-metadata-workgroup-processor-mode-v5.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa-note-no-func.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
hsa.ll
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
huge-number-operand-folds.mir
…
huge-private-buffer.ll
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
i1_copy_phi_with_phi_incoming_value.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
i1-copies-rpo.mir
…
i1-copy-from-loop.ll
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
i1-copy-implicit-def.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
i1-copy-phi-uniform-branch.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
i1-copy-phi.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
i8-to-double-to-float.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
icmp64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
icmp-select-sete-reverse-args.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
icmp.i16.ll
[AMDGPU][True16][CodeGen] flat/global/scratch load/store pseudo for true16 (#127945)
2025-02-21 17:06:48 -05:00
idemponent-atomics.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
identical-subrange-spill-infloop.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
idiv-licm.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
idot2.ll
AMDGPU: Use default shouldRewriteCopySrc (#125535)
2025-02-07 12:31:14 +07:00
idot4s.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
idot4u.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
idot8s.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
idot8u.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
iglp-no-clobber.ll
[AMDGPU] NFC: Fix some details for lit test (#127141)
2025-02-16 19:34:20 +07:00
iglp.opt.reentry.ll
[AMDGPU] Do not attempt to fallback to default mutations (#83208)
2024-02-27 18:04:59 -08:00
illegal-eviction-assert.mir
RegAlloc: Use new approach to handling failed allocations (#128469)
2025-02-26 15:34:47 +07:00
illegal-sgpr-to-vgpr-copy.ll
AMDGPU: Explicitly disable verifier in failing tests
2024-09-20 10:26:57 +04:00
image-attributes.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
image-load-d16-tfe.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
image-resource-id.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
image-sample-waterfall.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
image-schedule.ll
…
img-nouse-adjust.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
imm16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
imm.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
immv216.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
implicit-arg-v5-opt.ll
[InstCombine] Infer nusw + nneg -> nuw for getelementptr (#111144)
2024-12-05 14:36:40 +01:00
implicit-def-muse.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
implicit-kernarg-backend-usage.ll
Reapply "[AMDGPU] Infer amdgpu-no-flat-scratch-init attribute in AMDGPUAttributor (#94647)" (#118907)
2024-12-09 16:44:48 -08:00
implicit-kernel-argument-alignment.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
implicitarg-attributes.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
implicitarg-offset-attributes.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
indirect-addressing-si-gfx9.ll
[AMDGPU] Generate checks for vector indexing. NFC. (#105668)
2024-08-22 16:11:12 +01:00
indirect-addressing-si.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
indirect-addressing-term.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
indirect-call-known-callees.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
indirect-call-set-from-other-function.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
indirect-call.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
indirect-private-64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
infer-addrpace-pipeline.ll
…
infer-uniform-load-shader.ll
…
infinite-loop-evergreen.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
infinite-loop.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
inflated-reg-class-snippet-copy-use-after-free.mir
RegAlloc: Use new approach to handling failed allocations (#128469)
2025-02-26 15:34:47 +07:00
infloop-subrange-spill-inspect-subrange.mir
[AMDGPU] Skip non-wwm reg implicit-def from bb prolog (#115834)
2024-11-12 23:30:57 +05:30
infloop-subrange-spill.mir
[AMDGPU] Skip non-wwm reg implicit-def from bb prolog (#115834)
2024-11-12 23:30:57 +05:30
inline-asm-reserved-regs.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
inline-asm.i128.ll
[AMDGPU][MC] Allow null where 128b or larger dst reg is expected (#115200)
2025-01-03 11:49:51 -08:00
inline-asm.ll
SelectionDAG: Do not propagate divergence through copy glue (#101210)
2024-07-31 00:04:58 +04:00
inline-attr.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
inline-calls.ll
…
inline-constraints.ll
[AMDGPU] Replace isInlinableLiteral16 with specific version (#84402)
2024-03-08 14:49:52 -05:00
inline-maxbb.ll
…
inlineasm-16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inlineasm-illegal-type.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inlineasm-mismatched-size-error.ll
[AMDGPU] Reject misaligned SGPR constraints for inline asm (#123590)
2025-01-20 15:47:11 +01:00
inlineasm-mismatched-size.ll
[AMDGPU] Check vector sizes for physical register constraints in inline asm (#109955)
2024-10-01 10:29:35 +02:00
inlineasm-packed.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
inlineasm-v16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
InlineAsmCrash.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
input-mods.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
insert_subreg.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
insert_vector_dynelt.ll
DAG: Avoid forming shufflevector from a single extract_vector_elt (#122672)
2025-01-17 08:44:43 +07:00
insert_vector_elt.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
insert_vector_elt.v2bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
insert_vector_elt.v2i16.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
…
insert_vector_elt.v2i16.subtest-saddr.ll
…
insert_waitcnt_for_precise_memory.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
insert-branch-w32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
insert-delay-alu-bug.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
insert-delay-alu-literal.mir
[AMDGPU][NewPM] Port AMDGPUInsertDelayAlu to NPM (#128003)
2025-02-26 09:50:09 +05:30
insert-delay-alu-parse.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
insert-delay-alu.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
insert-handle-flat-vmem-ds.mir
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
insert-skip-from-vcc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
insert-skips-gfx10.mir
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
insert-skips-gfx12.mir
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
insert-skips-gws.mir
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
insert-skips-ignored-insts.mir
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
insert-subvector-unused-scratch.ll
…
insert-waitcnts-callee.mir
…
insert-waitcnts-crash.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
insert-waitcnts-exp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
insert-waitcnts-hang.mir
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
inserted-wait-states.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
integer-mad-patterns.ll
PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)
2025-01-30 20:42:02 +07:00
internalize.ll
Revert "[Transforms][IPO] Add func suffix in ArgumentPromotion and DeadArgume… (#105742)"
2024-09-19 03:54:13 -07:00
invalid-addrspacecast.ll
AMDGPU: Stop emitting an error on illegal addrspacecasts (#127487)
2025-02-17 21:03:50 +07:00
invalid-cast-load-i1.ll
[AMDGPU] Fix an invalid cast in AMDGPULateCodeGenPrepare::visitLoadInst (#122494)
2025-01-12 23:40:25 -05:00
invalid-hidden-kernarg-in-kernel-signature.ll
[AMDGPU] Fix hidden kernarg preload count inconsistency (#116759)
2024-12-08 10:10:08 -08:00
invalid-inline-asm-constraint-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
invariant-image-load.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
invariant-load-no-alias-store.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
invert-br-undef-vcc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ipra-regmask.ll
[CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM (#113874)
2024-11-15 12:00:09 +05:30
ipra-return-address-save-restore.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
ipra.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
isel-amdgcn-cs-chain-intrinsic-w32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
isel-amdgcn-cs-chain-intrinsic-w64.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
isel-amdgpu-cs-chain-cc.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
isel-amdgpu-cs-chain-preserve-cc.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
issue48473.mir
RegAlloc: Use new approach to handling failed allocations (#128469)
2025-02-26 15:34:47 +07:00
issue92561-restore-undef-scc-verifier-error.ll
PeepholeOpt: Handle subregister compose when looking through reg_sequence (#127051)
2025-02-18 08:07:29 +07:00
issue98474-assigned-physreg-interference.mir
VirtRegRewriter: Add implicit register defs for live out undef lanes (#112679)
2024-10-28 17:33:53 -07:00
issue98474-need-live-out-undef-subregister-def.ll
VirtRegRewriter: Add implicit register defs for live out undef lanes (#112679)
2024-10-28 17:33:53 -07:00
issue98474-virtregrewriter-live-out-undef-subregisters.mir
VirtRegRewriter: Add implicit register defs for live out undef lanes (#112679)
2024-10-28 17:33:53 -07:00
issue120256-annotate-constexpr-addrspacecast.ll
AMDGPU: Fix mishandling of search for constantexpr addrspacecasts (#120346)
2024-12-20 07:37:19 +07:00
issue121601-combine-concat-vectors-assumes-f16.ll
DAG: Fix assuming f16 is the only 16-bit fp type in concat vector combine (#121637)
2025-01-06 10:38:54 +07:00
itofp.i128.bf.ll
[DAG] Always allow folding XOR patterns to ABS pre-legalization (#94601)
2024-06-07 11:02:50 +01:00
itofp.i128.ll
Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
2024-11-08 10:21:46 -08:00
jump-address.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
kcache-fold.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
kernarg-size.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
kernarg-stack-alignment.ll
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
2024-02-09 09:20:25 +01:00
kernel_code_t_recurse.ll
MCExpr-ify amd_kernel_code_t (#91587)
2024-05-22 13:45:45 +01:00
kernel-args.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
kernel-argument-dag-lowering.ll
[DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (#128167)
2025-02-24 11:09:41 +00:00
kernel-mubuf-with-voffset.mir
…
kernel-vgpr-spill-mubuf-with-voffset.ll
[AMDGPU] Skip non-wwm reg implicit-def from bb prolog (#115834)
2024-11-12 23:30:57 +05:30
kill-infinite-loop.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
known-never-nan.ll
…
known-never-snan.ll
…
knownbits-recursion.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
large-alloca-compute.ll
AMDGPU: Default to selecting frame indexes to SGPRs (#115060)
2024-11-08 19:01:59 -08:00
large-alloca-graphics.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
large-constant-initializer.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
large-work-group-promote-alloca.ll
…
lcssa-optnone.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-alignment.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
lds-bounds.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-branch-vmem-hazard.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-direct-hazards-gfx11.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-direct-hazards-gfx12.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-dma-hazards.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
lds-dma-waitcnt.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
lds-dma-waits.ll
[AMDGPU] Use alias info to relax waitcounts for LDS DMA (#74537)
2024-01-17 23:44:15 -08:00
lds-frame-extern.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
lds-global-non-entry-func.ll
[GlobalISel] Fold ptrtoint(undef) and inttoptr(undef) to undef. (#119073)
2024-12-09 08:52:22 +00:00
lds-initializer.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-limit-diagnostics.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
lds-m0-init-in-loop.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-misaligned-bug.ll
[LiveIntervals] repairIntervalsInRange: recompute width changes (#78564)
2024-03-11 15:24:17 +09:00
lds-mixed-absolute-addresses-unused.ll
[AMDGPU][LowerModuleLDS] Refactor partially lowered module detection (#85793)
2024-03-21 11:28:35 +01:00
lds-mixed-absolute-dynlds.ll
[AMDGPU] Fix DynLDS causing crash when LowerLDS is run at fullLTO pipeline (#96038)
2024-06-28 21:05:48 -05:00
lds-no-realign-allocated-variables.ll
[AMDGPU] Don't realign already allocated LDS. Point fix for 106412 (#106421)
2024-08-28 18:30:48 +01:00
lds-oqap-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-output-queue.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-reject-anonymous-kernels.ll
…
lds-reject-mixed-absolute-addresses.ll
[AMDGPU][LowerModuleLDS] Refactor partially lowered module detection (#85793)
2024-03-21 11:28:35 +01:00
lds-relocs.ll
[AMDGPU] Use absolute relocations when compiling for AMDPAL and Mesa3D (#67791)
2023-10-10 09:22:02 +02:00
lds-run-twice-absolute-md.ll
[AIX][tests] Disable failing tests on AIX
2024-03-12 12:11:18 -04:00
lds-run-twice.ll
[AMDGPU] Fix DynLDS causing crash when LowerLDS is run at fullLTO pipeline (#96038)
2024-06-28 21:05:48 -05:00
lds-size-hsa-gfx950.ll
AMDGPU: Increase the LDS size to support to 160 KB for gfx950 (#116309)
2024-11-18 10:48:56 -08:00
lds-size-pal-gfx950.ll
AMDGPU: Increase the LDS size to support to 160 KB for gfx950 (#116309)
2024-11-18 10:48:56 -08:00
lds-size.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
lds-zero-initializer.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
legalize-amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.buffer.load.format.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.buffer.store.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.buffer.store.format.f32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.ptr.buffer.load.format.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.ptr.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.ptr.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.ptr.tbuffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.ptr.tbuffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.tbuffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.tbuffer.store.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-amdgcn.raw.tbuffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalize-fp-load-invariant.ll
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
legalize-soffset-mbuf.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
legalizedag-bug-expand-setcc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
licm-regpressure.mir
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
licm-valu.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
licm-wwm.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
limit-coalesce.mir
[MIR] Serialize virtual register flags (#110228)
2024-10-14 14:19:53 +05:30
limit-soft-clause-reg-pressure.mir
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
lit.local.cfg
…
literal-constant-like-operand-instruction-size.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
literals.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
live-interval-bug-in-rename-independent-subregs.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
liveness.mir
[CodeGen][NewPM] Port LiveIntervals to new pass manager (#98118)
2024-07-10 19:34:48 +08:00
liveout-implicit-def-subreg-redef-blender-verifier-error.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
llc-pipeline.ll
[AMDGPU] Push amdgpu-preload-kern-arg-prolog after livedebugvalues (#126148)
2025-02-17 13:29:56 -05:00
llvm.amdgcn.addrspacecast.nonnull.ll
[AMDGPU] Improve detection of non-null addrspacecast operands (#82311)
2024-03-01 14:01:10 +01:00
llvm.amdgcn.alignbyte.ll
[AMDGPU][True16][MC][CodeGen] true16 for v_alignbyte_b32 (#125706)
2025-02-07 09:54:11 -05:00
llvm.amdgcn.atomic.cond.sub.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.atomic.dec.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.atomic.inc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.ballot.i64.ll
AMDGPU/GlobalISel: Fix inst-selection of ballot (#109986)
2024-10-11 11:40:27 +02:00
llvm.amdgcn.ballot.i64.wave32.ll
AMDGPU/GlobalISel: Fix inst-selection of ballot (#109986)
2024-10-11 11:40:27 +02:00
llvm.amdgcn.bitop3.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
llvm.amdgcn.bitreplicate.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.buffer.load-last-use.ll
[AMDGPU] Update tests for last-use in global/scratch/flat/buffer load… (#94975)
2024-06-11 06:30:13 +02:00
llvm.amdgcn.buffer.load.dwordx3.ll
[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (#93801)
2024-06-10 12:14:51 +01:00
llvm.amdgcn.buffer.store.dwordx3.ll
[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (#93801)
2024-06-10 12:14:51 +01:00
llvm.amdgcn.class.f16.ll
…
llvm.amdgcn.class.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.cos.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.cos.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.cubeid.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.cubema.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.cubesc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.cubetc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.cvt.f32.fp8.err.ll
AMDGPU: Fix incorrectly selecting fp8/bf8 conversion intrinsics (#107291)
2024-10-09 21:38:47 +04:00
llvm.amdgcn.cvt.fp8.dpp.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.cvt.fp8.dpp.mir
AMDGPU/NewPM Port GCNDPPCombine to NPM (#105816)
2024-08-29 14:49:52 +05:30
llvm.amdgcn.cvt.fp8.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.cvt.pk.i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.cvt.pk.u16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.cvt.pknorm.i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.cvt.pknorm.u16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.cvt.pkrtz.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
AMDGPU: Restrict src0 to VGPRs only for certain cvt scale opcodes. (#127464)
2025-02-21 07:27:25 +05:30
llvm.amdgcn.cvt.scalef32.pk.ll
AMDGPU: Restrict src0 to VGPRs only for certain cvt scale opcodes. (#127464)
2025-02-21 07:27:25 +05:30
llvm.amdgcn.cvt.scalef32.sr.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.cvt.scalef32.sr.pk.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.cvt.sr.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.dead.ll
[AMDGPU] Add llvm.amdgcn.dead intrinsic (#123190)
2025-02-20 09:25:48 +01:00
llvm.amdgcn.dispatch.id.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.dispatch.ptr.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
llvm.amdgcn.div.fixup.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.div.fixup.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.div.fmas.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.div.scale.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.dot4.f32.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
llvm.amdgcn.ds.add.gs.reg.rtn.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.ds.append.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.ds.bpermute.fi.b32.ll
[LLVM][AMDGPU] Add Intrinsic and Builtin for ds_bpermute_fi_b32 (#124616)
2025-01-29 14:04:10 +01:00
llvm.amdgcn.ds.bpermute.ll
…
llvm.amdgcn.ds.bvh.stack.rtn.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.ds.consume.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.ds.gws.barrier.ll
[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)
2023-12-15 12:33:32 +01:00
llvm.amdgcn.ds.gws.init.ll
…
llvm.amdgcn.ds.gws.sema.br.ll
…
llvm.amdgcn.ds.gws.sema.p.ll
…
llvm.amdgcn.ds.gws.sema.release.all.ll
…
llvm.amdgcn.ds.gws.sema.v.ll
…
llvm.amdgcn.ds.ordered.add.gfx10.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.ds.ordered.add.gfx11.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.ds.ordered.add.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.ds.ordered.swap.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.read.tr.gfx950.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.ds.sub.gs.reg.rtn.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.ds.swizzle.ll
…
llvm.amdgcn.exp2.ll
…
llvm.amdgcn.exp.compr.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.exp.ll
[AMDGPU] Add GFX12 test coverage for export instructions (#100415)
2024-07-25 10:55:07 +01:00
llvm.amdgcn.exp.prim.ll
[AMDGPU] Add GFX12 test coverage for export instructions (#100415)
2024-07-25 10:55:07 +01:00
llvm.amdgcn.exp.row.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.fcmp.w32.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.fcmp.w64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.fdiv.fast.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.fdot2.bf16.bf16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.fdot2.f16.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.fdot2.f32.bf16.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.fdot2.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.fma.legacy.ll
…
llvm.amdgcn.fmad.ftz.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.fmad.ftz.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.fmed3.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.fmed3.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.fmul.legacy.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.fract.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.fract.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.frexp.exp.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.frexp.exp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.frexp.mant.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.frexp.mant.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.global.atomic.csub.ll
[AMDGPU][SILoadStoreOptimizer] Merge constrained sloads (#96162)
2024-07-23 13:50:42 +05:30
llvm.amdgcn.global.atomic.ordered.add.b64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.global.load.lds.gfx950.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.global.load.lds.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.global.load.tr-w32.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.global.load.tr-w64.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.groupstaticsize.ll
…
llvm.amdgcn.icmp.w32.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.icmp.w64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.iglp.opt.exp.large.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.iglp.opt.exp.simple.ll
[AMDGPU] Add iglp_opt(3) for simple mfma / exp interleaving (#117269)
2024-12-06 15:19:07 -08:00
llvm.amdgcn.iglp.opt.exp.small.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.iglp.opt.ll
[AMDGPU] Add target hook to isGlobalMemoryObject (#112781)
2025-01-11 09:57:57 -08:00
llvm.amdgcn.iglp.opt.single.2b.mir
[AMDGPU] Use correct VGPR threshold for flagging ExcessRP regions in unified register file case (#85860)
2024-03-25 13:11:58 -07:00
llvm.amdgcn.iglp.opt.single.2c.mir
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
llvm.amdgcn.image.a16.dim.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.image.a16.encode.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.image.atomic.dim.ll
[AMDGPU] Overload image atomic swap to allow float as well. (#107283)
2024-09-09 17:54:30 +02:00
llvm.amdgcn.image.atomic.flt.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.atomic.pk.add.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.image.d16.dim.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.dim.gfx90a.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.dim.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll
[AMDGPU] Replace '.' with '-' in generic target names (#81718)
2024-02-14 15:19:04 +01:00
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.gather4.o.dim.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.getlod.dim.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.2dmsaa.ll
[AMDGPU] Overload resource descriptor in image intrinsics. (#107255)
2024-09-27 15:33:52 +02:00
llvm.amdgcn.image.load.a16.d16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.load.a16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.msaa.load.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
llvm.amdgcn.image.msaa.load.x.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.nsa.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
llvm.amdgcn.image.sample.a16.dim.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
llvm.amdgcn.image.sample.cd.a16.dim.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.sample.cd.dim.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.sample.cd.g16.encode.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.sample.cd.g16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.sample.d16.dim.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
llvm.amdgcn.image.sample.dim.gfx90a.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.sample.dim.ll
[AMDGPU] Replace '.' with '-' in generic target names (#81718)
2024-02-14 15:19:04 +01:00
llvm.amdgcn.image.sample.g16.a16.dim.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.sample.g16.encode.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.sample.g16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.sample.noret.ll
[AMDGPU] Add no return image_sample intrinsics and instructions (#97542)
2024-07-20 17:26:58 +09:00
llvm.amdgcn.image.sample.o.dim.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.store.a16.d16.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.image.store.a16.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.implicit.ptr.buffer.hsa.ll
…
llvm.amdgcn.implicit.ptr.buffer.ll
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
2024-02-09 09:20:25 +01:00
llvm.amdgcn.implicitarg.ptr.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.init.exec.ll
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
llvm.amdgcn.init.exec.wave32.ll
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
llvm.amdgcn.init.whole.wave-w32.ll
[AMDGPU] Add llvm.amdgcn.dead intrinsic (#123190)
2025-02-20 09:25:48 +01:00
llvm.amdgcn.init.whole.wave-w64.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.interp.f16.ll
…
llvm.amdgcn.interp.inreg.ll
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
llvm.amdgcn.interp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.intersect_ray.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.inverse.ballot.i32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.inverse.ballot.i64.ll
[AMDGPU] Move GCNPreRAOptimizations after MachineScheduler (#116211)
2024-11-16 09:40:46 +00:00
llvm.amdgcn.is.private.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.is.shared.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.kernarg.segment.ptr.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.kill.ll
[AMDGPU] Fix computed kill mask (#122736)
2025-01-14 10:00:40 +01:00
llvm.amdgcn.lds.direct.load.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.lds.kernel.id.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.lds.param.load.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.lerp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.log.clamp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.log.ll
…
llvm.amdgcn.make.buffer.rsrc.ll
[AMDGPU] Generalize amdgcn.make.buffer.rsrc to fat pointers (#126828)
2025-02-18 14:15:28 -06:00
llvm.amdgcn.mbcnt.ll
[AMDGPU] Simplify, fix and improve known bits for mbcnt (#104768)
2024-08-19 18:22:06 +01:00
llvm.amdgcn.mfma.bf16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.mfma.gfx90a.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.mfma.gfx942.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.mfma.gfx950.bf16.ll
AMDGPU: Handle gfx950 XDL-write-VGPR-VALU-Mem-Exp wait state change (#126727)
2025-02-12 01:30:53 +07:00
llvm.amdgcn.mfma.gfx950.ll
AMDGPU: Handle gfx950 XDL-write-VGPR-VALU-Mem-Exp wait state change (#126727)
2025-02-12 01:30:53 +07:00
llvm.amdgcn.mfma.i8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.mfma.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
AMDGPU: Handle gfx950 XDL-write-VGPR-VALU-Mem-Exp wait state change (#126727)
2025-02-12 01:30:53 +07:00
llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
AMDGPU: Handle gfx950 XDL-write-VGPR-VALU-Mem-Exp wait state change (#126727)
2025-02-12 01:30:53 +07:00
llvm.amdgcn.mfma.xf32.gfx942.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.mov.dpp8.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.mqsad.pk.u16.u8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.mqsad.u32.u8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.msad.u8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.mul.i24.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.mul.u24.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.mulhi.i24.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.mulhi.u24.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.perm.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.permlane16.swap.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.permlane16.var.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.permlane32.swap.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.permlane64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.permlane64.ptr.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.permlane.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.permlane.ptr.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.pops.exiting.wave.id.ll
[AMDGPU] Handle llvm.amdgcn.pops.exiting.wave.id with calls (#98614)
2024-07-12 21:00:26 +01:00
llvm.amdgcn.prng.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
llvm.amdgcn.ps.live.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.qsad.pk.u16.u8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.quadmask.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.queue.ptr.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.raw.atomic.buffer.load.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.raw.buffer.atomic.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.raw.buffer.load.format.d16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.raw.buffer.load.format.ll
[AMDGPU] llvm.amdgcn.raw.buffer.load.format intrinsic supports v4i32 as return type. (#116067)
2024-11-14 06:21:58 +01:00
llvm.amdgcn.raw.buffer.load.lds.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] Fix some cache policy checks for GFX12+ (#116396)
2024-11-21 08:22:59 +00:00
llvm.amdgcn.raw.buffer.load.tfe.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
…
llvm.amdgcn.raw.buffer.store.format.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Fix some cache policy checks for GFX12+ (#116396)
2024-11-21 08:22:59 +00:00
llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.raw.ptr.buffer.atomic.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.raw.ptr.buffer.load.bf16.xfail.ll
AMDGPU: Do not assert on v6x16 buffer load intrinsics (#94966)
2024-06-10 16:38:06 +02:00
llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
[AMDGPU] Regenerate buffer intrinsic tests with update_llc_test_checks. NFC.
2024-09-11 11:06:55 +01:00
llvm.amdgcn.raw.ptr.buffer.load.format.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.raw.ptr.buffer.load.lds.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.raw.ptr.buffer.load.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.raw.ptr.buffer.store.bf16.xfail.ll
AMDGPU: Do not assert on v6x16 buffer load intrinsics (#94966)
2024-06-10 16:38:06 +02:00
llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
…
llvm.amdgcn.raw.ptr.buffer.store.format.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.raw.ptr.buffer.store.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
Reapply "[AMDGPU] Handle natively unsupported types in addrspace(7) lowering" (#123660)
2025-01-20 16:12:17 -06:00
llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.raw.ptr.tbuffer.load.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.raw.ptr.tbuffer.store.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.raw.tbuffer.load.d16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.rcp.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)
2025-02-26 10:50:49 -05:00
llvm.amdgcn.rcp.legacy.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.rcp.ll
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
llvm.amdgcn.readfirstlane.ll
AMDGPU: Add more codegen tests for readfirstlane
2025-02-25 14:45:26 +07:00
llvm.amdgcn.readfirstlane.m0.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.readfirstlane.ptr.ll
[AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (#89217)
2024-06-25 14:35:19 +05:30
llvm.amdgcn.readlane.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.readlane.ptr.ll
[AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (#89217)
2024-06-25 14:35:19 +05:30
llvm.amdgcn.reduce.umax.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.reduce.umin.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.rsq.clamp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.rsq.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)
2025-02-26 10:50:49 -05:00
llvm.amdgcn.rsq.legacy.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.rsq.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.barrier.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.s.buffer.load.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.s.buffer.prefetch.data.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
llvm.amdgcn.s.dcache.inv.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.dcache.inv.vol.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.dcache.wb.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.dcache.wb.vol.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.decperflevel.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.get.waveid.in.workgroup.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.getpc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.getreg.ll
…
llvm.amdgcn.s.incperflevel.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.memrealtime.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.memtime.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.nop.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.prefetch.data.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
llvm.amdgcn.s.sethalt.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.setprio.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.setreg.ll
[AMDGPU] Reapply 'Sign extend simm16 in setreg intrinsic' (#78492)
2024-01-17 17:23:46 -08:00
llvm.amdgcn.s.sleep.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.sleep.var.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.s.ttracedata.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.s.wait.event.ll
[AMDGPU] Fix GFX12 encoding of s_wait_event export_ready (#89622)
2024-04-23 14:38:45 +01:00
llvm.amdgcn.s.wait.gfx12.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
llvm.amdgcn.s.waitcnt.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sad.hi.u8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sad.u8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sad.u16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sbfe.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sched.barrier.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sched.group.barrier.gfx11.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.sched.group.barrier.gfx12.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.sched.group.barrier.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
llvm.amdgcn.sdot2.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sdot4.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sdot8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sendmsg.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sendmsg.rtn.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.set.inactive.chain.arg.ll
[AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive (#107889)
2024-09-11 17:16:06 +01:00
llvm.amdgcn.set.inactive.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.sffbh.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sin.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sin.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.smfmac.gfx950.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
llvm.amdgcn.softwqm.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sqrt.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)
2025-02-26 10:50:49 -05:00
llvm.amdgcn.sqrt.ll
…
llvm.amdgcn.struct.atomic.buffer.load.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.struct.buffer.atomic.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.buffer.load.format.d16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] Extend zero initialization of return values for TFE (#85759)
2024-03-25 09:01:46 +00:00
llvm.amdgcn.struct.buffer.load.format.v3f16.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.struct.buffer.load.lds.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.buffer.load.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.buffer.load.tfe.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.struct.buffer.store.format.d16.ll
…
llvm.amdgcn.struct.buffer.store.format.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
[AMDGPU] Regenerate buffer intrinsic tests with update_llc_test_checks. NFC.
2024-09-11 11:06:55 +01:00
llvm.amdgcn.struct.ptr.buffer.load.format.ll
[AMDGPU] Extend zero initialization of return values for TFE (#85759)
2024-03-25 09:01:46 +00:00
llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
…
llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.struct.ptr.buffer.load.lds.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.ptr.buffer.load.ll
[AMDGPU] Regenerate buffer intrinsic tests with update_llc_test_checks. NFC.
2024-09-11 11:06:55 +01:00
llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.struct.ptr.buffer.store.format.ll
[AMDGPU] Regenerate buffer intrinsic tests with update_llc_test_checks. NFC.
2024-09-11 11:06:55 +01:00
llvm.amdgcn.struct.ptr.buffer.store.ll
[AMDGPU] Regenerate buffer intrinsic tests with update_llc_test_checks. NFC.
2024-09-11 11:06:55 +01:00
llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.ptr.tbuffer.load.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.struct.ptr.tbuffer.store.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.struct.tbuffer.load.d16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.struct.tbuffer.store.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.sudot4.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sudot8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.tbuffer.load.dwordx3.ll
[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (#93801)
2024-06-10 12:14:51 +01:00
llvm.amdgcn.tbuffer.store.dwordx3.ll
[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (#93801)
2024-06-10 12:14:51 +01:00
llvm.amdgcn.trig.preop.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.ubfe.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.udot2.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.udot4.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.udot8.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.unreachable.ll
…
llvm.amdgcn.update.dpp.gfx90a.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.update.dpp.ll
[AMDGPU] Extend type support for update_dpp intrinsic (#114597)
2024-11-05 13:59:14 -08:00
llvm.amdgcn.wave.barrier.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.wave.id.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.wave.reduce.umax.mir
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
llvm.amdgcn.wave.reduce.umin.mir
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
llvm.amdgcn.wavefrontsize.ll
[llvm][AMDGPU] Fold llvm.amdgcn.wavefrontsize early (#114481)
2024-11-25 10:29:50 +00:00
llvm.amdgcn.wmma_32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.wmma_64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.workgroup.id.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
[AMDGPU] Fix llvm.amdgcn.workitem.id-unsupported-calling-convention.ll (#127041)
2025-02-13 22:23:47 +07:00
llvm.amdgcn.workitem.id.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.wqm.demote.ll
[AMDGPU] Fix computed kill mask (#122736)
2025-01-14 10:00:40 +01:00
llvm.amdgcn.wqm.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.wqm.vote.ll
[AMDGPU] Fix computed kill mask (#122736)
2025-01-14 10:00:40 +01:00
llvm.amdgcn.writelane.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.writelane.ptr.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.ceil.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen pattern for v_pack_b32_f16 (#121988)
2025-01-13 12:26:36 -05:00
llvm.cos.f16.ll
[AMDGPU][True16][MC] true16 for v_cos_f16 (#120639)
2025-01-03 15:46:41 -05:00
llvm.cos.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.dbg.value.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.exp2.ll
[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)
2025-01-06 17:42:38 +05:30
llvm.exp10.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
llvm.exp.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
llvm.floor.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen pattern for v_pack_b32_f16 (#121988)
2025-01-13 12:26:36 -05:00
llvm.fma.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.fmuladd.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.fptrunc.round.err.ll
AMDGPU: Add f64 to f32 support for llvm.fptrunc.round (#107481)
2024-09-05 22:57:27 -07:00
llvm.fptrunc.round.ll
AMDGPU: Add f64 to f32 support for llvm.fptrunc.round (#107481)
2024-09-05 22:57:27 -07:00
llvm.frexp.ll
[AMDGPU][True16][MC] true16 for v_frexp_mant_f16 (#120653)
2025-01-03 14:42:39 -05:00
llvm.get.fpmode.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.get.rounding.ll
[AMDGPU] Move GCNPreRAOptimizations after MachineScheduler (#116211)
2024-11-16 09:40:46 +00:00
llvm.is.fpclass.bf16.ll
[AMDGPU] Add commute for some VOP3 inst (#121326)
2025-01-22 11:08:26 +07:00
llvm.is.fpclass.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.is.fpclass.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.ldexp.ll
[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)
2025-02-25 17:09:34 -05:00
llvm.log2.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
llvm.log10.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
llvm.log.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
llvm.maximum.f16.ll
AMDGPU: Widen f16 minimum/maximum to v2f16 on gfx950 (#128121)
2025-02-21 12:08:49 +07:00
llvm.maximum.f32.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
llvm.maximum.f64.ll
AMDGPU: Add gfx950 subtarget definitions (#116307)
2024-11-18 10:41:14 -08:00
llvm.maxnum.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)
2025-02-26 10:50:49 -05:00
llvm.memcpy.ll
[AMDGPU] Stop combining arbitrary offsets into PAL relocs (#80034)
2024-01-31 10:28:23 +00:00
llvm.minimum.f16.ll
AMDGPU: Widen f16 minimum/maximum to v2f16 on gfx950 (#128121)
2025-02-21 12:08:49 +07:00
llvm.minimum.f32.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
llvm.minimum.f64.ll
AMDGPU: Add gfx950 subtarget definitions (#116307)
2024-11-18 10:41:14 -08:00
llvm.minnum.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.mulo.ll
PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)
2025-01-30 20:42:02 +07:00
llvm.pow-gfx9.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.pow.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.powi.ll
…
llvm.prefetch.ll
[AMDGPU] Fix negative immediate offset for unbuffered smem loads (#89165)
2024-06-24 14:18:23 -07:00
llvm.r600.cube.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.r600.dot4.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.r600.group.barrier.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.r600.read.local.size.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.r600.recipsqrt.clamped.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.r600.recipsqrt.ieee.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.r600.tex.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.rint.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)
2025-02-26 10:50:49 -05:00
llvm.rint.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.rint.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.round.f64.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
llvm.round.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.set.rounding.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
llvm.sin.f16.ll
[AMDGPU][True16][MC] true16 for v_sin_f16 (#120692)
2025-01-03 14:11:25 -05:00
llvm.sin.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.sqrt.f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.trunc.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)
2025-02-26 10:50:49 -05:00
lo16-hi16-illegal-copy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lo16-hi16-physreg-copy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lo16-lo16-physreg-copy-agpr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lo16-lo16-physreg-copy-sgpr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
load-constant-always-uniform.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
load-constant-f32.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
load-constant-f64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
load-constant-i1.ll
PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)
2025-01-30 20:42:02 +07:00
load-constant-i8.ll
DAG: Avoid stack usage in bitcast operand promotion to legal vector (#125637)
2025-02-04 16:43:42 +07:00
load-constant-i16.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
load-constant-i32.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
load-constant-i64.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
load-global-f32.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
load-global-f64.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
load-global-i1.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
load-global-i8.ll
DAG: Avoid stack usage in bitcast operand promotion to legal vector (#125637)
2025-02-04 16:43:42 +07:00
load-global-i16.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
load-global-i32.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
load-global-i64.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
load-hi16.ll
[AMDGPU] Accept arbitrary sized sources in CalculateByteProvider (#70240)
2024-02-07 11:34:50 -08:00
load-input-fold.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
load-lo16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
load-local-f32-no-ds128.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
load-local-f32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
load-local-f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
load-local-i1.ll
[AMDGPU] Fix crash in allowsMisalignedMemoryAccesses with i1 (#105794)
2024-08-23 11:51:37 -07:00
load-local-i8.ll
[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)
2024-09-19 09:00:21 +02:00
load-local-i16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
load-local-i32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
load-local-i64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
load-local-redundant-copies.ll
[test] Remove immarg parameter attribute from calls (#97432)
2024-07-03 09:02:31 +01:00
load-local.96.ll
…
load-local.128.ll
…
load-range-metadata-assert.ll
…
load-range-metadata-sign-bits.ll
GlobalISel: ComputeNumSignBits from load range metadata
2024-07-01 15:26:50 +02:00
load-select-ptr.ll
…
load-store-cnt.ll
[AMDGPU] Create new option for force flush load counter (#124974)
2025-01-30 11:14:38 -08:00
load-store-opt-addc0.mir
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
load-store-opt-dlc.mir
AMDGPU/NewPM Port SILoadStoreOptimizer to NPM (#106362)
2024-09-02 11:41:56 +05:30
load-store-opt-scc.mir
AMDGPU/NewPM Port SILoadStoreOptimizer to NPM (#106362)
2024-09-02 11:41:56 +05:30
load-weird-sizes.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
local-64.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
local-atomicrmw-fadd.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
local-atomicrmw-fmax.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
local-atomicrmw-fmin.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
local-atomicrmw-fsub.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
local-atomics64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
local-atomics.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
local-memory.amdgcn.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
local-memory.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
local-memory.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
local-stack-alloc-add-references.gfx8.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
local-stack-alloc-add-references.gfx9.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
local-stack-alloc-add-references.gfx10.mir
AMDGPU: Support VALU add instructions in localstackalloc (#101692)
2024-08-08 23:22:48 +04:00
local-stack-alloc-block-sp-reference.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
local-stack-slot-offset.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
long-branch-reserve-register.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
loop_break.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
loop_exit_with_xor.ll
…
loop_header_nopred.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
loop-address.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
loop-idiom.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
loop-live-out-copy-undef-subrange.ll
[AMDGPU] Enable GCNRewritePartialRegUses pass by default. (#72975)
2023-12-14 14:10:27 +01:00
loop-on-function-argument.ll
…
loop-prefetch-data.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
loop-prefetch.ll
…
lower-buffer-fat-pointers-calls.ll
Reapply "[AMDGPU] Handle natively unsupported types in addrspace(7) lowering" (#123660)
2025-01-20 16:12:17 -06:00
lower-buffer-fat-pointers-constants.ll
[IR] Mark shl constant expression as undesirable (#95940)
2024-06-19 09:10:28 +02:00
lower-buffer-fat-pointers-contents-legalization.ll
Reapply "[AMDGPU] Handle natively unsupported types in addrspace(7) lowering" (#123660)
2025-01-20 16:12:17 -06:00
lower-buffer-fat-pointers-control-flow.ll
[AMDGPU] Add IR-level pass to rewrite away address space 7 (#77952)
2024-03-06 09:49:58 -06:00
lower-buffer-fat-pointers-lastuse-metadata.ll
DAG: Avoid introducing stack usage in vector->int bitcast int op promotion
2025-02-04 16:32:47 +07:00
lower-buffer-fat-pointers-mem-transfer.ll
[AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621)
2025-02-26 16:03:32 -06:00
lower-buffer-fat-pointers-memops.ll
[AMDGPU] Handle nontemporal and amdgpu.last.use metadata in amdgpu-lower-buffer-fat-pointers (#120139)
2025-01-14 11:22:20 +01:00
lower-buffer-fat-pointers-nontemporal-metadata.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
lower-buffer-fat-pointers-p7-in-memory.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
lower-buffer-fat-pointers-pointer-ops.ll
[AMDGPU] Generalize amdgcn.make.buffer.rsrc to fat pointers (#126828)
2025-02-18 14:15:28 -06:00
lower-buffer-fat-pointers-unoptimized-debug-data.ll
Reapply "[AMDGPU] Handle natively unsupported types in addrspace(7) lowering" (#123660)
2025-01-20 16:12:17 -06:00
lower-control-flow-live-intervals.mir
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
lower-control-flow-live-variables-update.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
lower-control-flow-live-variables-update.xfail.mir
…
lower-control-flow-other-terminators.mir
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
lower-ctor-dtor-constexpr-alias.ll
AMDGPU: Add instruction flags when lowering ctor/dtor (#111652)
2024-10-09 18:03:35 +04:00
lower-ctor-dtor-declaration.ll
…
lower-ctor-dtor-existing.ll
…
lower-ctor-dtor.ll
AMDGPU: Add instruction flags when lowering ctor/dtor (#111652)
2024-10-09 18:03:35 +04:00
lower-empty-ctor-dtor.ll
…
lower-i1-copies-clear-kills.mir
…
lower-i1-copies-implicit-def-unstructured-loop.mir
…
lower-indirect-lds-references.ll
[llvm][amdgpu] Handle indirect refs to LDS GVs during LDS lowering (#124089)
2025-01-23 14:53:11 +01:00
lower-kernargs.ll
[AMDGPU] Preserve noundef and range during kernel argument loads (#118395)
2024-12-04 11:04:03 -06:00
lower-kernel-and-module-lds.ll
[opt] Infer DataLayout from triple if not specified
2023-10-26 12:07:37 -07:00
lower-kernel-lds-constexpr.ll
…
lower-kernel-lds-super-align.ll
[opt] Infer DataLayout from triple if not specified
2023-10-26 12:07:37 -07:00
lower-kernel-lds.ll
[opt] Infer DataLayout from triple if not specified
2023-10-26 12:07:37 -07:00
lower-lds-struct-aa-memcpy.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
lower-lds-struct-aa-merge.ll
[opt] Infer DataLayout from triple if not specified
2023-10-26 12:07:37 -07:00
lower-lds-struct-aa.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
lower-mem-intrinsics-threshold.ll
[Pass] Add pre-isel-intrinsic-lowering to pass registry (#90851)
2024-05-02 21:57:46 +08:00
lower-mem-intrinsics.ll
[AMDGPU] Remove special cases in TTI::getMemcpyLoop(Residual)LoweringType (#125507)
2025-02-04 08:18:24 +01:00
lower-module-lds-all-indirect-accesses.ll
…
lower-module-lds-check-metadata.ll
…
lower-module-lds-constantexpr-phi.ll
…
lower-module-lds-constantexpr.ll
…
lower-module-lds-inactive.ll
…
lower-module-lds-indirect-extern-uses-max-reachable-alignment.ll
[AMDGPU] Strengthen preload intrinsics to noundef and nonnull (#92801)
2024-06-03 16:37:08 -05:00
lower-module-lds-offsets.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
lower-module-lds-single-var-ambiguous.ll
…
lower-module-lds-single-var-unambiguous.ll
…
lower-module-lds-used-list.ll
[opt] Infer DataLayout from triple if not specified
2023-10-26 12:07:37 -07:00
lower-module-lds-via-hybrid.ll
Reapply "[AMDGPU] Infer amdgpu-no-flat-scratch-init attribute in AMDGPUAttributor (#94647)" (#118907)
2024-12-09 16:44:48 -08:00
lower-module-lds-via-table.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
lower-module-lds-zero-size-arr.ll
[AMDGPU][LDS] Fix dynamic LDS interaction with "amdgpu-no-lds-kernel-id" (#107092)
2024-09-04 16:41:43 +02:00
lower-module-lds.ll
…
lower-multiple-ctor-dtor.ll
AMDGPU: Add instruction flags when lowering ctor/dtor (#111652)
2024-10-09 18:03:35 +04:00
lower-range-metadata-intrinsic-call.ll
…
lower-term-opcodes.mir
[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)
2025-01-20 16:34:01 +05:30
lower-work-group-id-intrinsics-hsa.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
lower-work-group-id-intrinsics-pal.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
lrint.ll
[AMDGPU] Implement llvm.lrint intrinsic lowering (#98931)
2024-07-24 23:34:31 +04:00
lround.ll
Scalarize the vector inputs to llvm.lround intrinsic by default. (#101054)
2024-08-21 12:13:56 -05:00
lshl64-to-32.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
lshl-add-u64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
lshr.v2i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
lto-lower-module-lds.ll
(Reland) [AMDGPU] Run LowerLDS at the end of the fullLTO pipeline (#85626)
2024-03-21 11:44:47 +01:00
machine-cse-commute-target-flags.mir
…
machine-cse-ssa.mir
[CodeGen][NewPM] Port MachineCSE pass to new pass manager. (#106605)
2024-09-04 18:54:07 +05:30
machine-scheduler-sink-trivial-remats-debug.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
machine-scheduler-sink-trivial-remats.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
machine-sink-cycle.mir
[MachineSink] Extend loop sinking capability (#117247)
2025-01-23 17:08:23 -08:00
machine-sink-ignorable-exec-use.mir
[MachineSink] Extend loop sinking capability (#117247)
2025-01-23 17:08:23 -08:00
machine-sink-lane-mask.mir
[MachineSink] Extend loop sinking capability (#117247)
2025-01-23 17:08:23 -08:00
machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
Revert "MachineSink: Fix sinking VGPR def out of a divergent loop"
2023-10-06 15:00:08 +02:00
machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
Revert "MachineSink: Fix sinking VGPR def out of a divergent loop"
2023-10-06 15:00:08 +02:00
machine-sink-temporal-divergence-swdev407790.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
machine-sink-temporal-divergence-swdev407790.mir
AMDGPU: Fix temporal divergence introduced by machine-sink (#67456)
2023-10-06 15:00:08 +02:00
machinelicm-convergent.mir
[NewPM][CodeGen] Port MachineLICM to NPM (#107376)
2024-09-20 11:34:18 +05:30
machinelicm-copy-like-instrs.mir
[NewPM][CodeGen] Port MachineLICM to NPM (#107376)
2024-09-20 11:34:18 +05:30
machinelicm-undef-use.mir
[NewPM][CodeGen] Port MachineLICM to NPM (#107376)
2024-09-20 11:34:18 +05:30
macro-fusion-cluster-vcc-uses.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
mad24-get-global-id.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
mad_64_32.ll
PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)
2025-01-30 20:42:02 +07:00
mad_int24.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mad_u64_u32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mad_uint24.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mad-combine.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mad-mix-hi.ll
[AMDGPU][True16][CodeGen] true16 codegen for MadFmaMixPat (#124892)
2025-02-11 17:36:44 -05:00
mad-mix-lo.ll
[AMDGPU][True16][CodeGen] build_vector pattern in true16 (#118904)
2025-02-21 14:02:12 -05:00
mad-mix.ll
[AMDGPU][True16][CodeGen] true16 codegen for MadFmaMixPat (#124892)
2025-02-11 17:36:44 -05:00
mad.u16.ll
[AMDGPU][True16][CodeGen] flat/global/scratch load/store pseudo for true16 (#127945)
2025-02-21 17:06:48 -05:00
madak-inline-constant.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
madak.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
madmk.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mai-hazards-gfx90a.mir
[AMDGPU][MC] Disallow op_sel in some VOP3P dot instructions (#100485)
2024-12-18 10:50:47 -08:00
mai-hazards-gfx942.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
mai-hazards-mfma-scale.gfx950.mir
AMDGPU: Handle gfx950 XDL-write-VGPR-Overlap-Src-AB wait state (#126732)
2025-02-11 22:30:16 +07:00
mai-hazards.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mai-inline.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
make-buffer-rsrc-lds-fails.ll
[AMDGPU] Generalize amdgcn.make.buffer.rsrc to fat pointers (#126828)
2025-02-18 14:15:28 -06:00
match-perm-extract-vector-elt-bug.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
materialize-frame-index-sgpr.gfx10.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
materialize-frame-index-sgpr.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
max3.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
max-hard-clause-length.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
max-literals.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
max-sgprs.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
max.i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
max.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
maximumnum.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
mcexpr-knownbits-assign-crash-gh-issue-110930.ll
[AMDGPU] Create local KnownBits in case DenseMap gets invalidated (#111568)
2024-10-22 16:05:07 +01:00
mcp-aligned-vgprs.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mcp-implicit-clobber.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mcp-overlap-after-propagation.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mcp-use-before-def.mir
…
mdt-preserving-crash.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
med3-knownbits.ll
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
med3-no-simplify.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mem-builtins.ll
[SelectionDAG] Preserve volatile undef stores. (#99918)
2024-07-24 08:41:56 -04:00
memcpy-crash-issue63986.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
memcpy-fixed-align.ll
AMDGPU: Default to selecting frame indexes to SGPRs (#115060)
2024-11-08 19:01:59 -08:00
memcpy-inline-fails.ll
…
memcpy-libcall.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
memcpy-param-combinations.ll
[AMDGPU] Enable unaligned scratch accesses (#110219)
2024-10-11 08:50:49 +02:00
memcpy-scalar-load.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
memcpy-scoped-aa.ll
…
memintrinsic-unroll.ll
[AMDGPU] Use wider loop lowering type for LowerMemIntrinsics (#112332)
2024-10-28 09:04:19 +01:00
memmove-param-combinations.ll
[AMDGPU] Enable unaligned scratch accesses (#110219)
2024-10-11 08:50:49 +02:00
memmove-scalar-load.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
memmove-var-size.ll
[AMDGPU] Remove special cases in TTI::getMemcpyLoop(Residual)LoweringType (#125507)
2025-02-04 08:18:24 +01:00
memory_clause.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
memory_clause.mir
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
memory-legalizer-atomic-insert-end.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
memory-legalizer-fence-mmra-global.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-fence-mmra-local.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-fence.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-flat-agent.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-flat-lastuse.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
memory-legalizer-flat-nontemporal.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-flat-singlethread.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-flat-system.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-flat-volatile.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
memory-legalizer-flat-wavefront.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-flat-workgroup.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-global-agent.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-global-lastuse.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
memory-legalizer-global-nontemporal.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-global-singlethread.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-global-system.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-global-volatile.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
memory-legalizer-global-wavefront.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-global-workgroup.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-invalid-addrspace.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
memory-legalizer-invalid-syncscope.ll
[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)
2024-09-04 12:15:20 +09:00
memory-legalizer-local-agent.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-local-nontemporal.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-local-singlethread.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-local-system.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-local-volatile.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
memory-legalizer-local-wavefront.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-local-workgroup.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
memory-legalizer-multiple-mem-operands-atomics.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
memory-legalizer-private-lastuse.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
memory-legalizer-private-nontemporal.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
memory-legalizer-private-volatile.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
memory-legalizer-region.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
memory-legalizer-store-infinite-loop.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
merge-buffer-gfx12.mir
[AMDPU] Add support for idxen and bothen buffer load/store merging in SILoadStoreOptimizer (#86285)
2024-03-25 14:44:22 +00:00
merge-buffer.mir
[AMDPU] Add support for idxen and bothen buffer load/store merging in SILoadStoreOptimizer (#86285)
2024-03-25 14:44:22 +00:00
merge-flat-load-store.mir
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
merge-flat-with-global-load-store.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
merge-global-load-store.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
merge-image-load-gfx10.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-image-load-gfx11.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-image-load-gfx12.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-image-load.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-image-sample-gfx10.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-image-sample-gfx11.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-image-sample-gfx12.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-image-sample.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-load-store-agpr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-load-store-physreg.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
merge-load-store-vreg.mir
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
merge-load-store.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-m0.mir
[AMDGPU] Skip non-wwm reg implicit-def from bb prolog (#115834)
2024-11-12 23:30:57 +05:30
merge-out-of-order-ldst.ll
…
merge-out-of-order-ldst.mir
…
merge-s-load.mir
[AMDGPU][SILoadStoreOptimizer] Merge constrained sloads (#96162)
2024-07-23 13:50:42 +05:30
merge-sbuffer-load.mir
[AMDGPU][SILoadStoreOptimizer] Include constrained buffer load variants (#101619)
2024-08-06 11:27:04 +05:30
merge-store-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-store-usedef.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-stores.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-tbuffer-gfx12.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
merge-tbuffer.mir
[AMDPU] Add support for idxen and bothen buffer load/store merging in SILoadStoreOptimizer (#86285)
2024-03-25 14:44:22 +00:00
mesa3d.ll
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
mesa_regression.ll
…
mfma-bf16-vgpr-cd-select.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
mfma-cd-select.ll
AMDGPU: Respect amdgpu-no-agpr in functions and with calls (#128147)
2025-02-23 09:00:37 +07:00
mfma-loop.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
mfma-no-register-aliasing.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
mfma-vgpr-cd-select-gfx942.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
mfma-vgpr-cd-select.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
min3.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
min-waves-per-eu-not-respected.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
min.ll
DAG: Avoid stack usage in bitcast operand promotion to legal vector (#125637)
2025-02-04 16:43:42 +07:00
minimummaximum.ll
[AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (#128784)
2025-02-25 20:04:57 -05:00
minimumnum.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
minmax.ll
[AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (#128784)
2025-02-25 20:04:57 -05:00
mir-print-dead-csr-fi.mir
…
misched-killflags.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
missing-store.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mixed_wave32_wave64.ll
…
mixed-vmem-types.ll
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
mixed-wave32-wave64.ll
…
mmo-target-flags-folding.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mmra.ll
[DAGISel] Fix MMRA Handling in copyExtraInfo (#124730)
2025-01-28 13:27:26 +01:00
mode-register-fpconstrain.ll
[AMDGPU] Fix mode register pass for constrained FP operations (#90085)
2024-05-03 19:47:15 +02:00
mode-register-fptrunc.gfx11plus-fake16.mir
[AMDGPU][True16][CodeGen] true16 codegen pat for fptrunc_round (#124044)
2025-01-30 18:31:52 -05:00
mode-register-fptrunc.gfx11plus.mir
[AMDGPU][True16][CodeGen] true16 codegen pat for fptrunc_round (#124044)
2025-01-30 18:31:52 -05:00
mode-register-fptrunc.mir
[AMDGPU][True16][CodeGen] true16 codegen pat for fptrunc_round (#124044)
2025-01-30 18:31:52 -05:00
mode-register.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
module-lds-false-sharing.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
move-addr64-rsrc-dead-subreg-writes.ll
…
move-load-addr-to-valu.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
move-to-valu-addsubu64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
move-to-valu-atomicrmw-system.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
move-to-valu-atomicrmw.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
move-to-valu-ctlz-cttz.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
move-to-valu-lshlrev.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
move-to-valu-pseudo-scalar-trans.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
move-to-valu-vimage-vsample.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
move-to-valu-worklist.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
movreld-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
movrels-bug.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
mubuf-legalize-operands-non-ptr-intrinsics.ll
[AMDGPU] Include WWM register spill into BB Prolog (#111496)
2024-10-08 15:13:12 +05:30
mubuf-legalize-operands.ll
[AMDGPU] Include WWM register spill into BB Prolog (#111496)
2024-10-08 15:13:12 +05:30
mubuf-legalize-operands.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
mubuf-offset-private.ll
AMDGPU: Handle v_add* in eliminateFrameIndex (#102346)
2024-10-02 21:19:45 +04:00
mubuf-shader-vgpr-non-ptr-intrinsics.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mubuf-shader-vgpr.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mubuf.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mul24-pass-ordering.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
mul_int24.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
mul_uint24-amdgcn.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
mul_uint24-r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mul.i16.ll
[AMDGPU][True16][CodeGen] V_MUL_LO_U16 true16 test (#118118)
2024-12-02 10:09:02 -05:00
mul.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
multi-call-resource-usage-mcexpr.ll
Reapply [AMDGPU] Avoid resource propagation for recursion through multiple functions (#112251)
2024-11-15 18:40:05 +00:00
multi-divergent-exit-region.ll
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
multi-dword-vgpr-spill.ll
…
multilevel-break.ll
[AMDGPU] Emit amdgcn.if.break in the same BB as amdgcn.loop (#118081)
2024-12-04 08:42:04 +01:00
naked-fn-with-frame-pointer.ll
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
nand.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
need-fp-from-vgpr-spills.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
neighboring-mfma-padding.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
nested-calls.ll
[NFC][AMDGPU] Autogenerating test cases (#124507)
2025-01-28 13:41:59 +05:30
nested-loop-conditions.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
no-bundle-asm.ll
…
no-corresponding-integer-type.ll
[AMDGPU] Introduce a new generic target gfx9-4-generic (#115190)
2024-11-12 23:11:05 -05:00
no-dup-inst-prefetch.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
no-fold-accvgpr-mov.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
no-fold-accvgpr-mov.mir
[AMDGPU] Do not fold into v_accvpr_mov/write/read (#120475)
2025-01-07 09:25:01 -06:00
no-fold-accvgpr-read.mir
[AMDGPU] Do not fold into v_accvpr_mov/write/read (#120475)
2025-01-07 09:25:01 -06:00
no-hsa-graphics-shaders.ll
[AMDGPU] Change handling of unsupported non-compute shaders with HSA (#126798)
2025-02-13 22:23:08 +07:00
no-initializer-constant-addrspace.ll
…
no-remat-indirect-mov.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
no-shrink-extloads.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
no-source-locations-in-prologue.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
noclobber-barrier.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
non-entry-alloca.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
noop-shader-O0.ll
…
nop-data.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
nor.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
not-scalarize-volatile-load.ll
…
nsa-reassign.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
nsa-reassign.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
nsa-vmem-hazard.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
nullptr-long-address-spaces.ll
[AMDGPU] Remove duplicate -mtriple options in tests (#91576)
2024-05-09 10:59:25 +01:00
nullptr.ll
[AMDGPU] Remove duplicate -mtriple options in tests (#91576)
2024-05-09 10:59:25 +01:00
occupancy-levels.ll
[AMDGPU] Add a new target for gfx1153 (#113138)
2024-10-23 12:56:58 +09:00
offset-split-flat.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
offset-split-global.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
omod-nsz-flag.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
omod.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
opencl-image-metadata.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
opencl-printf-and-hostcall.ll
…
opencl-printf-pipeline.ll
…
opencl-printf-unsupported.ll
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
opencl-printf.ll
[ConstantFold] Remove notional over-indexing fold (#93697)
2024-05-30 08:36:44 +02:00
operand-folding.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
operand-spacing.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
opt_exec_copy_fold.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
opt-exec-masking-pre-ra-update-liveness-wave32.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
opt-exec-masking-pre-ra-update-liveness.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
opt-sgpr-to-vgpr-copy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
opt-vgpr-live-range-verifier-error.mir
[AMDGPU][NewPM] Port SIOptimizeVGPRLiveRange pass to NPM. (#117686)
2024-11-29 09:11:24 +05:30
optimize-compare.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
optimize-compare.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
optimize-exec-copies-extra-insts-after-copy.mir
[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)
2025-01-20 16:34:01 +05:30
optimize-exec-mask-pre-ra-alloc-failure.mir
…
optimize-exec-mask-pre-ra-def-after-use.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
optimize-exec-mask-pre-ra-loop-phi.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
optimize-exec-masking-pre-ra.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
optimize-exec-masking-strip-terminator-bits.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
optimize-if-exec-masking.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
optimize-negated-cond-exec-masking-wave32.mir
[AMDGPU] Fix implicit $vcc operands after parsing MIR (#87781)
2024-04-09 09:10:45 +01:00
optimize-negated-cond-exec-masking.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
optimize-negated-cond.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
or3.ll
…
or.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
overlapping-tuple-copy-implicit-op-failure.ll
…
pack.v2f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
pack.v2i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
packed-fp32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
packed-op-sel.ll
[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)
2024-07-23 13:59:15 +05:30
packetizer.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
pal-metadata-3.0-callable.ll
Reapply "[AMDGPU] Add pal metadata 3.0 support to callable pal funcs (#67104)"
2024-03-14 10:56:43 +09:00
pal-metadata-3.0.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
pal-simple-indirect-call.ll
AMDGPU: Port AMDGPUAttributor to new pass manager (#71349)
2023-11-07 15:40:40 +09:00
pal-userdata-regs.ll
[Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763)
2024-04-29 15:37:42 +02:00
parallelandifcollapse.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
parallelorifcollapse.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
partial-forwarding-hazards.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
partial-regcopy-and-spill-missed-at-regalloc.ll
Reapply "[AMDGPU] Infer amdgpu-no-flat-scratch-init attribute in AMDGPUAttributor (#94647)" (#118907)
2024-12-09 16:44:48 -08:00
partial-sgpr-to-vgpr-spills.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
partial-shift-shrink.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
partially-dead-super-register-immediate.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
peephole-fold-imm.mir
AMDGPU: Handle brev and not cases in getConstValDefinedInReg (#127483)
2025-02-18 11:23:49 +07:00
peephole-opt-fold-reg-sequence-subreg.mir
PeepholeOpt: Handle subregister compose when looking through reg_sequence (#127051)
2025-02-18 08:07:29 +07:00
peephole-opt-regseq-removal.mir
AMDGPU: Use default shouldRewriteCopySrc (#125535)
2025-02-07 12:31:14 +07:00
pei-amdgpu-cs-chain-preserve.mir
[AMDGPU] Fix restores in chain functions (#116193)
2024-11-20 10:43:59 +01:00
pei-amdgpu-cs-chain.mir
[AMDGPU] Fix restores in chain functions (#116193)
2024-11-20 10:43:59 +01:00
pei-build-av-spill.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
pei-build-spill-partial-agpr.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
pei-build-spill.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
pei-reg-scavenger-position.mir
…
pei-scavenge-sgpr-carry-out.mir
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
pei-scavenge-sgpr-gfx9.mir
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
pei-scavenge-sgpr.mir
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
pei-scavenge-vgpr-spill.mir
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
perfhint.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
permlane16_opsel.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
permlane16_var-op-sel.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
permlane-op-sel.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
permute_i8.ll
[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#124131)
2025-01-24 09:12:32 +01:00
permute.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
phi-elimination-assertion.mir
[CodeGen][NewPM] Port phi-node-elimination to new pass manager (#98867)
2024-07-17 11:26:56 +08:00
phi-elimination-end-cf.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
phi-vgpr-input-moveimm.mir
[AMDGPU] Add MachineVerifier check to detect illegal copies from vector register to SGPR (#105494)
2024-09-19 13:57:44 +05:30
phys-partial-liveness.mir
[CodeGen][NewPM] Port LiveIntervals to new pass manager (#98118)
2024-07-10 19:34:48 +08:00
pk_max_f16_literal.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
post-ra-sched-kill-bundle-use-inst.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
post-ra-sched-reset.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
post-ra-soft-clause-dbg-info.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
postra-bundle-memops.mir
[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)
2025-02-21 16:05:58 +05:30
postra-machine-sink.mir
[CodeGen] Simplify updateLiveIn in MachineSink (#79831)
2024-02-15 10:39:05 +00:00
postra-norename.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
postra-sink-update-dependency.mir
[MachineSink] Update register dependency correctly (#109763)
2024-09-25 08:42:40 +08:00
power-sched-no-instr-sunit.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
pr51516.mir
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
predicate-dp4.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
predicates.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
preload-implicit-kernargs-debug-info.ll
[AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (#126763)
2025-02-19 10:20:48 +01:00
preload-implicit-kernargs-IR-lowering.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
preload-implicit-kernargs.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
preload-kernarg-header.ll
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
2025-01-10 11:39:02 -08:00
preload-kernargs-inreg-hints.ll
AMDGPU: Infer no-agpr usage in AMDGPUAttributor (#85948)
2024-03-21 14:24:06 +05:30
preload-kernargs-IR-lowering.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
preload-kernargs.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
preserve-hi16.ll
[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)
2025-02-19 11:37:24 -05:00
preserve-only-inactive-lane.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
preserve-user-waitcnt.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
preserve-wwm-copy-dst-reg.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
prevent-fmul-hoist-ir.ll
[AMDGPU] Implement IR variant of isFMAFasterThanFMulAndFAdd (#121465)
2025-01-10 09:05:41 +05:30
print-pipeline-passes.ll
[AMDGPU] Only run AMDGPUPrintfRuntimeBindingPass at non-prelink phase (#125162)
2025-02-10 08:24:50 -05:00
printf_builtin.ll
…
printf_nobuiltin.ll
…
printf-defined.ll
…
printf-existing-format-strings.ll
…
private-access-no-objects.ll
…
private-memory-atomics.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
private-memory-r600.ll
[AMDGPU] Swap range metadata to attribute for workitem id. (#94871)
2024-06-09 10:29:50 -04:00
prologue-epilogue-markers.ll
…
promote-alloca-addrspacecast.ll
AMDGPU: Stop promoting allocas with addrspacecast users (#104051)
2024-08-14 21:53:38 +04:00
promote-alloca-array-aggregate.ll
[AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. (#122342)
2025-02-24 13:36:30 -06:00
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
…
promote-alloca-budget-exhausted.ll
[AMDGPU][PromoteAlloca] Don't stop when an alloca is too big to promote (#93466)
2024-05-28 08:05:50 +02:00
promote-alloca-calling-conv.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
promote-alloca-globals.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
promote-alloca-invariant-markers.ll
[NFC][AMDGPU] Improve code introduced in #124607 (#124672)
2025-01-27 22:57:16 -05:00
promote-alloca-lifetime.ll
…
promote-alloca-loadstores.ll
[AMDGPU] PromoteAlloca: Handle load/store subvectors using non-constant indexes (#71505)
2023-11-07 15:29:41 +01:00
promote-alloca-mem-intrinsics.ll
[AMDGPU] Handle object size and bail if assume-like intrinsic is used in PromoteAllocaToVector (#68744)
2023-12-20 07:47:49 +01:00
promote-alloca-memset.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
promote-alloca-no-opts.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
promote-alloca-non-constant-index.ll
SSAUpdater: use poison instead of undef in phi entries for unreachable predecessors
2024-06-30 11:51:30 +01:00
promote-alloca-padding-size-estimate.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
promote-alloca-pointer-array.ll
[IRBuilder] Migrate most casts to folding API
2023-09-29 12:40:38 +02:00
promote-alloca-scoring.ll
[AMDGPU][PromoteAlloca] Whole-function alloca promotion to vector (#84735)
2024-03-19 11:49:22 +01:00
promote-alloca-stored-pointer-value.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
promote-alloca-strip-abi-opt-attributes.ll
[AMDGPU] Swap range metadata to attribute for workitem id. (#94871)
2024-06-09 10:29:50 -04:00
promote-alloca-subvecs.ll
[AMDGPU] Fix PromoteAlloca size check of alloca for store (#72528)
2023-11-20 07:57:48 -06:00
promote-alloca-to-lds-constantexpr-use.ll
…
promote-alloca-to-lds-icmp.ll
[AMDGPU] Swap range metadata to attribute for workitem id. (#94871)
2024-06-09 10:29:50 -04:00
promote-alloca-to-lds-phi.ll
…
promote-alloca-to-lds-select.ll
…
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-vector-gep.ll
ValueTracking: Allow getUnderlyingObject to look at vectors (#114311)
2024-11-06 17:14:44 -08:00
promote-alloca-vector-to-vector.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
promote-alloca-volatile.ll
[AMDGPU] PromoteAlloca - bail always if load/store is volatile (#73228)
2023-11-28 12:01:35 +01:00
promote-constOffset-to-imm-gfx10.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
promote-constOffset-to-imm-gfx90a.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
promote-constOffset-to-imm.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
promote-constOffset-to-imm.mir
[AMDGPU] add missing checks in processBaseWithConstOffset (#102310)
2024-08-12 11:54:02 +04:00
promote-kernel-arguments.ll
AMDGPU: Regenerate baseline test checks
2024-08-05 21:27:40 +04:00
promote-vect3-load.ll
[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)
2024-07-23 13:59:15 +05:30
propagate-attributes-bitcast-function.ll
…
propagate-flat-work-group-size.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
propagate-waves-per-eu.ll
[AMDGPU][Attributor] Make AAAMDWavesPerEU honor existing attribute (#114438)
2024-12-11 16:50:06 -05:00
ps-shader-arg-count.ll
…
pseudo-scalar-transcendental.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
pseudo-scalar-transcendental.mir
[AMDGPU] Disable inline constants for pseudo scalar transcendentals (#104395)
2024-08-17 16:52:38 +09:00
ptr-arg-dbg-value.ll
[AMDGPU] NFC. Run auto-update on a few tests
2023-11-21 13:52:02 -05:00
ptr-buffer-alias-scheduling.ll
[AMDGPU] Generalize amdgcn.make.buffer.rsrc to fat pointers (#126828)
2025-02-18 14:15:28 -06:00
ptrmask.ll
AtomicExpand: Fix creating invalid ptrmask for fat pointers (#94955)
2024-06-12 10:45:42 +02:00
pv-packing.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
pv.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600-constant-array-fixup.ll
…
r600-encoding.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600-export-fix.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600-legalize-umax-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600.add.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600.alu-limits.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600.amdgpu-alias-analysis.ll
…
r600.bitcast.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600.extract-lowbits.ll
…
r600.func-alignment.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600.global_atomics.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600.private-memory.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600.sub.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600.work-item-intrinsics.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
r600cfg.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ra-inserted-scalar-instructions.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
ran-out-of-registers-error-all-regs-reserved.ll
RegAllocFast: Fix verifier errors after assigning to reserved registers (#128281)
2025-02-26 13:22:53 +07:00
ran-out-of-registers-errors.ll
RegAllocFast: Avoid using temporary DiagnosticInfo (#120184)
2024-12-17 16:19:26 +07:00
ran-out-of-sgprs-allocation-failure.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
rcp_iflag.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
rcp-pattern.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
read_register.ll
…
read-register-invalid-subtarget.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
read-register-invalid-type-i32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
read-register-invalid-type-i64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
readcyclecounter.ll
[AMDGPU] Prefer s_memtime for readcyclecounter on GFX10 (#80211)
2024-02-01 07:19:57 -06:00
readlane_exec0.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
README
…
readsteadycounter.ll
[LLVM] Add __builtin_readsteadycounter intrinsic and builtin for realtime clocks (#81331)
2024-02-13 10:06:25 -06:00
reassoc-mul-add-1-to-mad.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
reassoc-scalar.ll
…
recursion.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
recursive_global_initializer.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
recursive-resource-usage-mcexpr.ll
Reapply [AMDGPU] Avoid resource propagation for recursion through multiple functions (#112251)
2024-11-15 18:40:05 +00:00
reduce-build-vec-ext-to-ext-build-vec.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
reduce-load-width-alignment.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
reduce-saveexec.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
reduce-store-width-alignment.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
reduction.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
reg-coalescer-sched-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
reg-sequence-like-v-pk-mov-b32.mir
AMDGPU: Add baseline test for treating v_pk_mov_b32 like reg_sequence (#125656)
2025-02-13 18:12:09 +07:00
regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
…
regalloc-failure-overlapping-insert-assert.mir
VirtRegRewriter: Fix verifier errors after regalloc failures (#128280)
2025-02-26 13:19:49 +07:00
regalloc-fast-dont-drop-subreg-index-issue61134.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
regalloc-illegal-eviction-assert.ll
RegAlloc: Do not fatal error if there are no registers in the alloc order (#119640)
2024-12-16 10:52:49 +09:00
regalloc-introduces-copy-sgpr-to-agpr.mir
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
2024-02-09 09:20:25 +01:00
regcoal-subrange-join-seg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regcoal-subrange-join.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regcoalesce-cannot-join-failures.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
regcoalesce-dbg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
regcoalesce-prune.mir
…
regcoalescer-resolve-lane-conflict-by-subranges.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
regcoalescing-remove-partial-redundancy-assert.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
register-coalescer--set-undef-full-reg-use-implicit-def-erase-issue109249.mir
RegisterCoalescer: Set undef on full register uses when coalescing implicit_def (#118321)
2024-12-02 14:43:04 -05:00
register-count-comments.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
register-killed-error-after-alloc-failure0.mir
RegAlloc: Use new approach to handling failed allocations (#128469)
2025-02-26 15:34:47 +07:00
register-killed-error-after-alloc-failure1.ll
Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" (#128400)
2025-02-26 15:31:48 +07:00
regpressure_printer.mir
[AMDGPU] Fix GCNUpwardRPTracker: max register pressure on defs. (#74422)
2023-12-08 11:27:08 +01:00
reject-agpr-usage-before-gfx908.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
rel32.ll
[AMDGPU] Stop combining arbitrary offsets into PAL relocs (#80034)
2024-01-31 10:28:23 +00:00
release-vgprs-dbg-loc.mir
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
release-vgprs.mir
[AMDGPU][MC] Fix disassembler problem for image_atomic with TFE (#112622)
2024-10-24 16:19:18 -07:00
rem_i128.ll
PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)
2025-01-30 20:42:02 +07:00
remaining-virtual-register-operands.ll
Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" (#128400)
2025-02-26 15:31:48 +07:00
remat-dead-subreg.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
remat-fp64-constants.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
RegisterCoalescer: Fix assert on remat to copy-to-physreg with subregs (#121734)
2025-01-07 12:22:23 +07:00
remat-smrd.mir
[AMDGPU] Rematerialize scalar loads (#68778)
2023-10-26 11:34:33 +02:00
remat-sop.mir
AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (#128677)
2025-02-25 18:22:32 +07:00
remat-vop.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
remove-incompatible-extended-image-insts.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
remove-incompatible-functions.ll
[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)
2025-01-13 10:11:40 +05:30
remove-incompatible-gws.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
remove-incompatible-s-time.ll
[CodeGen][NewPM] Port MachineCopyPropagation to NPM (#125202)
2025-02-04 15:45:03 +05:30
remove-incompatible-wave32-feature.ll
[CodeGen][NewPM] Port MachineCopyPropagation to NPM (#125202)
2025-02-04 15:45:03 +05:30
remove-no-kernel-id-attribute.ll
[llvm][amdgpu] Handle indirect refs to LDS GVs during LDS lowering (#124089)
2025-01-23 14:53:11 +01:00
remove-not-short-exec-branch-on-unconditional-jump.mir
[AMDGPU][SIPreEmitPeephole] Fix mustRetainExeczBranch (#120121)
2024-12-17 11:47:38 +01:00
remove-short-exec-branches-gpr-idx-mode.mir
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
remove-short-exec-branches-special-instructions.mir
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
rename-disconnected-bug.ll
…
rename-independent-subregs-mac-operands.mir
[CodeGen][NewPM] Port RenameIndependentSubregs to NPM (#125192)
2025-02-05 17:54:57 +05:30
rename-independent-subregs.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
reorder-stores.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
repeated-divisor.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
replace-store-of-insert-load.ll
…
reqd-work-group-size.ll
[InstCombine] Infer nusw + nneg -> nuw for getelementptr (#111144)
2024-12-05 14:36:40 +01:00
required-export-priority.ll
AMDGPU: Default to selecting frame indexes to SGPRs (#115060)
2024-11-08 19:01:59 -08:00
required-export-priority.mir
[AMDGPU] Implement workaround for GFX11.5 export priority (#99273)
2024-07-23 17:03:21 +09:00
reserved-reg-in-clause.mir
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
resource-optimization-remarks.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
resource-usage-crash-unhandled-reg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
resource-usage-dead-function.ll
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
resource-usage-pal.ll
…
ret_jump.ll
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
ret.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
return-with-successors.mir
[CodeGen][NewPM] Port LiveIntervals to new pass manager (#98118)
2024-07-10 19:34:48 +08:00
returnaddress.ll
…
rewrite-out-arguments-address-space.ll
…
rewrite-out-arguments.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
rewrite-partial-reg-uses-dbg.mir
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
2025-02-12 11:21:40 +05:30
rewrite-partial-reg-uses-gen.mir
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
2025-02-12 11:21:40 +05:30
rewrite-partial-reg-uses.mir
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
2025-02-12 11:21:40 +05:30
rewrite-undef-for-phi.ll
…
rotl.i64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
rotl.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
rotr.i64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
rotr.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
roundeven.ll
[AMDGPU] Move GCNPreRAOptimizations after MachineScheduler (#116211)
2024-11-16 09:40:46 +00:00
rsq.f32.ll
[CodeGen] [AMDGPU] Attempt DAGCombine for fmul with select to ldexp (#111109)
2024-12-09 12:52:04 +05:30
rsq.f64.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
rv7x0_count3.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
s_add_co_pseudo_lowering.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
s_addk_i32.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
s_code_end.ll
…
s_movk_i32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
s_mulk_i32.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
s_or_saveexec_xor_combine.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
s-barrier-lowering.ll
[AMDGPU] modify named barrier builtins and intrinsics (#114550)
2024-11-06 10:37:22 -08:00
s-barrier.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
s-getpc-b64-remat.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
sad.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
saddo.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
saddsat.ll
[AMDGPU][True16][CodeGen] saddsat/ssubsat sdag for true16 format (#118245)
2024-12-02 14:20:59 -05:00
salu-to-valu.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
same-slot-agpr-sgpr.mir
[AMDGPU] Add pseudo instructions for SGPR spill to VGPR (#69923)
2023-10-27 17:24:10 +05:30
sampler-resource-id.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
save-fp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
scalar_to_vector_v2x16.ll
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
scalar_to_vector.ll
DAG: Fold bitcast of scalar_to_vector to anyext (#122660)
2025-01-13 19:38:58 +07:00
scalar_to_vector.v8i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
scalar-branch-missing-and-exec.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
scalar-float-sop1.ll
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
scalar-float-sop2.ll
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
scalar-float-sopc.ll
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
scalar-store-cache-flush.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
scalarize-insert-subvector.ll
[LegalizeTypes][AMDGPU]: Allow for scalarization of insert_subvector (#104236)
2024-08-15 08:07:05 -07:00
scc-clobbered-sgpr-to-vmem-spill.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
sched-assert-dead-def-subreg-use-other-subreg.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
sched-assert-onlydbg-value-empty-region.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
sched-barrier-hang-weak-dep.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
sched-barrier-post-RA.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sched-barrier-pre-RA.mir
[AMDGPU] Add target hook to isGlobalMemoryObject (#112781)
2025-01-11 09:57:57 -08:00
sched-crash-dbg-value.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
sched-group-barrier-pipeline-solver.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
sched-group-barrier-pre-RA.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
sched-handleMoveUp-subreg-def-across-subreg-def.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
sched-prefer-non-mfma.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sched-setprio.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sched.barrier.inverted.mask.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-addrspaces.ll
Revert "Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on targets using scratch instructions for stack #78226" (#86273)
2024-03-26 11:01:08 +01:00
schedule-amdgpu-tracker-physreg-crash.ll
[AMDGPU] Optionally Use GCNRPTrackers during scheduling (#93090)
2024-10-09 09:54:11 -07:00
schedule-amdgpu-tracker-physreg.ll
[AMDGPU] Remove some lit check lines
2024-10-09 16:12:31 -07:00
schedule-amdgpu-trackers.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
schedule-avoid-spills.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-barrier-fpmode.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
schedule-barrier.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
schedule-fs-loop-nested-if.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-fs-loop-nested.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-fs-loop.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-global-loads.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-if-2.ll
…
schedule-if.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-ilp-liveness-tracking.mir
[AMDGPU] Add MaxMemoryClauseSchedStrategy (#114957)
2024-12-09 10:07:27 +08:00
schedule-ilp.ll
[AMDGPU] Add MaxMemoryClauseSchedStrategy (#114957)
2024-12-09 10:07:27 +08:00
schedule-ilp.mir
…
schedule-kernel-arg-loads.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-physregdeps.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-regpressure-ilp-metric-spills.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
schedule-regpressure-lds.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-regpressure-limit2.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-regpressure-limit3.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-regpressure-limit-clustering.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
schedule-regpressure-limit.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-regpressure-misched-max-waves.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-regpressure.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-relaxed-occupancy.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
schedule-vs-if-nested-loop-failure.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-vs-if-nested-loop.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
schedule-xdl-resource.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
scheduler-handle-move-bundle.mir
…
scheduler-rp-calc-one-successor-two-predecessors-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
scheduler-subrange-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
scratch-buffer.ll
AMDGPU: Default to selecting frame indexes to SGPRs (#115060)
2024-11-08 19:01:59 -08:00
scratch-pointer-sink.ll
Revert "Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on targets using scratch instructions for stack #78226" (#86273)
2024-03-26 11:01:08 +01:00
scratch-simple.ll
AMDGPU: Default to selecting frame indexes to SGPRs (#115060)
2024-11-08 19:01:59 -08:00
sdag-print-divergence.ll
SelectionDAG: Do not propagate divergence through copy glue (#101210)
2024-07-31 00:04:58 +04:00
sdiv64.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
sdiv.ll
PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)
2025-01-30 20:42:02 +07:00
sdivrem24.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sdivrem64.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sdwa-commute.ll
[AMDGPU] Enable unaligned scratch accesses (#110219)
2024-10-11 08:50:49 +02:00
sdwa-cse.mir
[AMDGPU] Fix SDWA commuting (#106920)
2024-10-04 15:53:40 -04:00
sdwa-gfx9.mir
[AMDGPU][NewPM] Port SIPeepholeSDWA pass to NPM (#107049)
2024-09-11 14:30:16 +04:00
sdwa-op64-test.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sdwa-ops.mir
[AMDGPU][NewPM] Port SIPeepholeSDWA pass to NPM (#107049)
2024-09-11 14:30:16 +04:00
sdwa-peephole-instr-combine-sel.ll
[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#124131)
2025-01-24 09:12:32 +01:00
sdwa-peephole-instr-combine-sel.mir
[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#124131)
2025-01-24 09:12:32 +01:00
sdwa-peephole-instr-gfx10.mir
[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#124131)
2025-01-24 09:12:32 +01:00
sdwa-peephole-instr.mir
[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#124131)
2025-01-24 09:12:32 +01:00
sdwa-peephole.ll
[CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (#126807)
2025-02-25 15:29:12 -08:00
sdwa-preserve.mir
[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#124131)
2025-01-24 09:12:32 +01:00
sdwa-scalar-ops.mir
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
sdwa-stack.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sdwa-vop2-64bit.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
select64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
select-constant-cttz.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
select-constant-xor.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
select-fabs-fneg-extract-legacy.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
select-fabs-fneg-extract.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
select-fabs-fneg-extract.legal.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
select-fabs-fneg-extract.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
select-fabs-fneg-extract.v2f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
select-flags-to-fmin-fmax.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
select-i1.ll
[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)
2024-09-19 09:00:21 +02:00
select-opt.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
select-phi-s16-fp.ll
[SDISel][Combine] Constant fold FP16_TO_FP (#94790)
2024-06-08 11:31:13 +02:00
select-undef.ll
AMDGPU: Make v4bf16 a legal type (#76217)
2024-01-05 08:35:07 +07:00
select-vectors.ll
[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)
2024-09-19 09:00:21 +02:00
select.f16.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
select.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
selectcc-cnd.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
selectcc-cnde-int.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
selectcc-icmp-select-float.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
selectcc-opt.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
selectcc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sendmsg-m0-hazard.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
set_kill_i1_for_floation_point_comparison.ll
[AMDGPU] Always emit SI_KILL_I1_PSEUDO for uniform floating point branches. (#124028)
2025-01-29 09:00:40 -08:00
set-dx10.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
set-gpr-idx-peephole.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
set-inactive-wwm-overwrite.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
set-wave-priority.ll
…
setcc64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
setcc-equivalent.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
setcc-fneg-constant.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
setcc-limit-load-shrink.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
setcc-multiple-use.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
setcc-opt.ll
[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)
2024-09-19 09:00:21 +02:00
setcc-sext.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
setcc.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
seto.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
setuo.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sext-divergence-driven-isel.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
sext-eliminate.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sext-in-reg-failure-r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sext-in-reg.ll
[AMDGPU] Remove duplicate -mtriple options in tests (#91576)
2024-05-09 10:59:25 +01:00
sgpr-control-flow.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
sgpr-copy-duplicate-operand.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sgpr-copy-local-cse.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
sgpr-copy.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sgpr-phys-copy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sgpr-regalloc-flags.ll
Revert "[AMDGPU][CodeGen] Do not backtrace invalid -regalloc param (#119687)"
2024-12-14 03:47:53 +00:00
sgpr-spill-dead-frame-in-dbg-value.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
[AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. (#109685)
2024-09-24 14:41:45 +05:30
sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
[AMDGPU][NewPM] Port SILowerSGPRSpills to NPM (#108934)
2024-09-21 09:59:36 +05:30
sgpr-spill-incorrect-fi-bookkeeping-bug.ll
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
sgpr-spill-no-vgprs.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
sgpr-spill-overlap-wwm-reserve.mir
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
sgpr-spill-partially-undef.mir
AMDGPU: Delete spills of undef values (#119684)
2024-12-17 13:08:38 +07:00
sgpr-spill-to-vmem-scc-clobber-unhandled.mir
Reapply "DiagnosticInfo: Clean up usage of DiagnosticInfoInlineAsm" (#119575) (#119634)
2024-12-11 16:01:48 -08:00
sgpr-spill-to-vmem-scc-clobber.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
sgpr-spill-update-only-slot-indexes.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
sgpr-spill-vmem-large-frame.mir
[AMDGPU] Add pseudo instructions for SGPR spill to VGPR (#69923)
2023-10-27 17:24:10 +05:30
sgpr-spill-wrong-stack-id.mir
Reapply "Move assertion for AdjustsStack from PEI to MachineVerifier (#85698)"
2024-03-21 20:24:57 -04:00
sgpr-spill.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
sgpr-spills-empty-prolog-block.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
sgpr-spills-split-regalloc.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
sgprcopies.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shader-addr64-nonuniform.ll
…
shared-op-cycle.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shift-and-i64-ubfe.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
shift-and-i128-ubfe.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
shift-i64-opts.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shift-i128.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
shift-select.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shl64_reduce_flags.ll
AMDGPU: Reduce shl64 to shl32 if shift range is [63-32] (#125574)
2025-02-13 13:40:25 -06:00
shl64_reduce.ll
DAG: Preserve range metadata when load is narrowed (#128144)
2025-02-26 15:40:49 +07:00
shl_add_constant.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shl_add_ptr_csub.ll
…
shl_add_ptr_global.ll
AMDGPU: Remove global/flat atomic fadd intrinics (#97051)
2024-08-22 23:27:33 +04:00
shl_add_ptr.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shl_add.ll
…
shl_or.ll
…
shl-add-to-add-shl.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shl.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
shl.v2i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
should-not-hoist-set-inactive.ll
AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)
2024-09-23 13:20:21 +04:00
shrink-add-sub-constant.ll
[AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (#128784)
2025-02-25 20:04:57 -05:00
shrink-carry.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shrink-i32-kimm.mir
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
shrink-instructions-flags.mir
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
shrink-instructions-illegal-fold.mir
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
shrink-instructions-implicit-vcclo.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shrink-insts-scalar-bit-ops.mir
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
shrink-mad-fma-fake16.mir
[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)
2025-02-19 11:37:24 -05:00
shrink-mad-fma-gfx10.mir
[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)
2025-02-19 11:37:24 -05:00
shrink-mad-fma.mir
[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)
2025-02-19 11:37:24 -05:00
shrink-true16.mir
[AMDGPU][True16][MC] VOPC profile fake16 pseudo update (#113175)
2024-11-22 12:12:13 -05:00
shrink-v-cmp-wave32-dead-vcc-lo.mir
AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)
2024-09-23 13:20:21 +04:00
shrink-vop3-carry-out.mir
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
shufflevector.v2bf16.v2bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2bf16.v3bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2bf16.v4bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2bf16.v8bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f16.v2f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f16.v3f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f16.v4f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f16.v8f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f32.v2f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f32.v3f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f32.v4f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f32.v8f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i16.v2i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i16.v3i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i16.v4i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i16.v8i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i32.v2i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i32.v3i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i32.v4i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i32.v8i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i64.v2i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i64.v3i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i64.v4i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i64.v8i64.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
shufflevector.v2p0.v2p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p0.v3p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p0.v4p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p3.v2p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p3.v3p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p3.v4p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p3.v8p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3bf16.v2bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3bf16.v3bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3bf16.v4bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3f16.v2f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3f16.v3f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3f16.v4f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3f32.v2f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3f32.v3f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3f32.v4f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i16.v2i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i16.v3i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i16.v4i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i32.v2i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i32.v3i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i32.v4i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i64.v2i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i64.v3i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i64.v4i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p0.v2p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p0.v3p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p0.v4p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p3.v2p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p3.v3p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p3.v4p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4bf16.v2bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4bf16.v3bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4bf16.v4bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f16.v2f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f16.v3f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f16.v4f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f32.v2f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f32.v3f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f32.v4f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i16.v2i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i16.v3i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i16.v4i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i32.v2i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i32.v3i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i32.v4i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i64.v2i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i64.v3i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i64.v4i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p0.v2p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p0.v3p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p0.v4p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p3.v2p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p3.v3p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p3.v4p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
si-annotate-cf-kill.ll
[AMDGPU] Fix computed kill mask (#122736)
2025-01-14 10:00:40 +01:00
si-annotate-cf-noloop.ll
AMDGPU/NewPM: Port SIAnnotateControlFlow to new pass manager (#102653)
2024-08-10 07:02:21 +04:00
si-annotate-cf-unreachable.ll
AMDGPU/NewPM: Port SIAnnotateControlFlow to new pass manager (#102653)
2024-08-10 07:02:21 +04:00
si-annotate-cf.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
si-annotate-cfg-loop-assert.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
si-annotate-dbg-info.ll
[RemoveDIs] Print IR with debug records by default (#91724)
2024-06-14 15:07:27 +01:00
si-annotate-nested-control-flows.ll
…
si-annotatecfg-multiple-backedges.ll
…
si-fix-sgpr-copies-copy-to-sgpr.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
si-fix-sgpr-copies.mir
AMDGPU/NewPM: Port SIFixSGPRCopies to new pass manager (#102614)
2024-08-09 17:52:41 +04:00
si-fold-aligned-agprs.mir
…
si-fold-aligned-vgprs.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
si-fold-copy-kills.mir
…
si-fold-kimm.mir
…
si-fold-operands-commute-same-operands-assert.mir
AMDGPU: More consistently use the fold list instead of direct mutation (#127612)
2025-02-25 12:02:03 +07:00
si-fold-reg-sequence.mir
[AMDGPU] Prevent hang in SIFoldOperands by caching uses (#82099)
2024-02-27 09:13:59 -06:00
si-fold-scalar-clamp.mir
AMDGPU/NewPM: Port SIFoldOperands to new pass manager (#105801)
2024-08-29 11:34:54 +05:30
si-i1-copies.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
si-init-whole-wave.mir
[CodeGen][NewPM] Port SIWholeQuadMode to NPM. (#125833)
2025-02-05 18:44:57 +05:30
si-instr-info-correct-implicit-operands.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
si-lower-control-flow-kill.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
si-lower-control-flow-unreachable-block.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
si-lower-control-flow.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
si-lower-i1-copies-order-of-phi-incomings.mir
[AMDGPU] Fix implicit $vcc operands after parsing MIR (#87781)
2024-04-09 09:10:45 +01:00
si-lower-i1-copies.mir
AMDGPU/NewPM: Port SILowerI1Copies to new pass manager (#102663)
2024-08-10 07:08:22 +04:00
si-lower-sgpr-spills-vgpr-lanes-usage.mir
Reapply "[AMDGPU]Optimize SGPR spills (#93668)"
2024-10-03 09:47:15 +00:00
si-lower-sgpr-spills.mir
[AMDGPU] Add pseudo instructions for SGPR spill to VGPR (#69923)
2023-10-27 17:24:10 +05:30
si-lower-wwm-copies.mir
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)
2025-01-22 14:54:01 +05:30
si-opt-vgpr-liverange-bug-deadlanes.mir
[AMDGPU][NewPM] Port SIOptimizeVGPRLiveRange pass to NPM. (#117686)
2024-11-29 09:11:24 +05:30
si-optimize-vgpr-live-range-dbg-instr.ll
…
si-optimize-vgpr-live-range-dbg-instr.mir
[AMDGPU][NewPM] Port SIOptimizeVGPRLiveRange pass to NPM. (#117686)
2024-11-29 09:11:24 +05:30
si-pre-allocate-wwm-regs.mir
[NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (#109939)
2024-10-22 15:37:08 +05:30
si-scheduler-exports.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
si-scheduler.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
si-sgpr-spill.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
si-spill-cf.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
si-triv-disjoint-mem-access.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
si-unify-exit-multiple-unreachables.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
si-unify-exit-return-unreachable.ll
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
si-vector-hang.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sibling-call.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
sign_extend.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
simple-indirect-call-2.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
simple-indirect-call.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
simplify-libcall-nobuiltin-def.ll
…
simplify-libcalls2.ll
…
simplify-libcalls.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
simplifydemandedbits-recursion.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sink-after-control-flow-postra.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
sink-after-control-flow.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sink-image-sample.ll
[AMDGPU] Set Convergent property for image.(getlod/sample*) intrinsics which uses WQM (#122908)
2025-01-15 10:23:28 +01:00
sint_to_fp.f64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
sint_to_fp.i64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
sint_to_fp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sitofp.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen pattern for v_pack_b32_f16 (#121988)
2025-01-13 12:26:36 -05:00
skip-branch-taildup-ret.mir
[AMDGPU][SIPreEmitPeephole] mustRetainExeczBranch: use BranchProbability and TargetSchedmodel (#109818)
2024-10-11 17:45:59 +02:00
skip-branch-trap.ll
…
skip-fold-regsequence.mir
AMDGPU/NewPM: Port SIFoldOperands to new pass manager (#105801)
2024-08-29 11:34:54 +05:30
skip-if-dead.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
skip-promote-alloca-vector-users.ll
…
smed3.ll
[AMDGPU][True16][CodeGen] true16 codegen pattern for v_med3_u/i16 (#121850)
2025-01-07 13:18:28 -05:00
smem-no-clause-coalesced.mir
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
smem-war-hazard.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
smfmac_no_agprs.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
sminmax.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sminmax.v2i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
smrd_vmem_war.ll
…
smrd-fold-offset.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
smrd-gfx10.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
smrd-vccz-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
smrd.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
snippet-copy-bundle-regression.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
soft-clause-dbg-value.mir
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
soft-clause-exceeds-register-budget.ll
…
sopk-compares.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
sopk-no-literal.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
speculative-execution-freecasts.ll
…
spill192.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill224.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill288.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill320.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill352.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill384.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill_kill_v16.mir
[AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (#128060)
2025-02-26 16:17:20 -05:00
spill_more_than_wavesize_csr_sgprs.ll
[NFC][AMDGPU] Auto generate check lines for three test cases (#127352)
2025-02-17 11:22:08 -05:00
spill-agpr-partially-undef.mir
AMDGPU: Delete spills of undef values (#119684)
2024-12-17 13:08:38 +07:00
spill-agpr.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
spill-agpr.mir
[NewPM][CodeGen] Port regallocfast to new pass manager (#94426)
2024-06-07 12:22:42 +08:00
spill-alloc-sgpr-init-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
spill-before-exec.mir
…
spill-cfg-position.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
spill-csr-frame-ptr-reg-copy.ll
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill-empty-live-interval.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill-m0.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
spill-offset-calculation.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
spill-partial-csr-sgpr-live-ins.mir
[AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (#126696)
2025-02-25 14:32:37 +05:30
spill-reg-tuple-super-reg-use.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill-regpressure-less.mir
AMDGPU: Respect amdgpu-no-agpr in functions and with calls (#128147)
2025-02-23 09:00:37 +07:00
spill-scavenge-offset.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
spill-sgpr-csr-live-ins.mir
[AMDGPU] Pick available high VGPR for CSR SGPR spilling (#78669)
2024-01-24 07:08:43 +05:30
spill-sgpr-stack-no-sgpr.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
spill-sgpr-to-virtual-vgpr.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill-sgpr-used-for-exec-copy.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill-special-sgpr.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
spill-to-agpr-partial.mir
…
spill-vector-superclass.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
spill-vgpr-to-agpr-update-regscavenger.ll
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
spill-vgpr-to-agpr.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
spill-vgpr.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
spill-wait.mir
[AMDGPU] Do not count implicit VGPRs in SIInsertWaitcnts (#109049)
2024-09-25 00:41:49 -07:00
spill-wide-sgpr.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
spill-writelane-vgprs.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
spillv16.ll
[AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (#128060)
2025-02-26 16:17:20 -05:00
spillv16.mir
[AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (#128060)
2025-02-26 16:17:20 -05:00
split-arg-dbg-value.ll
…
split-liverange-overlapping-copies.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
split-mbb-lis-subrange.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
split-scalar-i64-add.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
split-smrd.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
split-vector-memoperand-offsets.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
splitkit-copy-bundle.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
splitkit-copy-live-lanes.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
splitkit-getsubrangeformask.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
splitkit-nolivesubranges.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
splitkit.mir
…
sra.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
sram-ecc-default.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sramecc-subtarget-feature-any.ll
[AMDGPU] Split GCNSubtarget into its own file. NFC. (#105525)
2024-08-21 19:11:02 +01:00
sramecc-subtarget-feature-disabled.ll
[AMDGPU] Split GCNSubtarget into its own file. NFC. (#105525)
2024-08-21 19:11:02 +01:00
sramecc-subtarget-feature-enabled.ll
[AMDGPU] Split GCNSubtarget into its own file. NFC. (#105525)
2024-08-21 19:11:02 +01:00
sreg-xnull-regclass-bitwidth.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
srem64.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
srem-seteq-illegal-types.ll
[TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (#101751)
2024-08-14 08:44:57 -07:00
srem.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
srl.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
sroa-before-unroll.ll
…
SRSRC-GIT-clobber-check.mir
…
ssubo.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
ssubsat.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
stack-pointer-offset-relative-frameindex.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
stack-realign-kernel.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
stack-realign.ll
[NFC][AMDGPU] Auto generate check lines for three test cases (#127352)
2025-02-17 11:22:08 -05:00
stack-size-overflow.ll
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
2024-02-09 09:20:25 +01:00
stack-slot-color-sgpr-vgpr-spills.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
stacksave_stackrestore.invalid.ll
…
stacksave_stackrestore.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
stale-livevar-in-twoaddr-pass.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
stop-tail-duplicate-cfg-intrinsic.mir
[CodeGen][NewPM] Port TailDuplicate pass to NPM (#113293)
2024-10-30 11:48:40 +05:30
store_typed.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
store-barrier.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
store-clobbers-load.ll
…
store-global.ll
[AMDGPU] Remove duplicate -mtriple options in tests (#91576)
2024-05-09 10:59:25 +01:00
store-hi16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
store-local.96.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
store-local.128.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
store-local.ll
[AMDGPU] Remove duplicate -mtriple options in tests (#91576)
2024-05-09 10:59:25 +01:00
store-private.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
store-to-constant-error.ll
…
store-v3i64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
store-vector-ptrs.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
store-weird-sizes.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
stress-calls.ll
…
strict_fadd.f16.ll
…
strict_fadd.f32.ll
…
strict_fadd.f64.ll
…
strict_fma.f16.ll
…
strict_fma.f32.ll
…
strict_fma.f64.ll
…
strict_fmul.f16.ll
…
strict_fmul.f32.ll
…
strict_fmul.f64.ll
…
strict_fpext.ll
DAG: Fix ABI lowering with FP promote in strictfp functions (#74405)
2024-01-18 10:57:53 +07:00
strict_fptrunc.ll
[AMDGPU][True16][CodeGen] build_vector pattern in true16 (#118904)
2025-02-21 14:02:12 -05:00
strict_fsub.f16.ll
…
strict_fsub.f32.ll
…
strict_fsub.f64.ll
…
strict_ldexp.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
strict_ldexp.f32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
strict_ldexp.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
strictfp_f16_abi_promote.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
structurize1.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
structurize.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
sub64-low-32-bits-known-zero.ll
AMDGPU: Reduce 64-bit add width if low bits are known 0 (#122049)
2025-01-08 22:33:54 +07:00
sub_i1.ll
[DAG] getNode - convert scalar i1 arithmetic calls to bitwise instructions (#125486)
2025-02-03 16:36:01 +00:00
sub-zext-cc-zext-cc.ll
…
sub.i16.ll
…
sub.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
sub.v2i16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
subreg_interference.mir
…
subreg-coalescer-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
subreg-coalescer-undef-use.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
subreg-eliminate-dead.ll
…
subreg-intervals.mir
[CodeGen][NewPM] Port LiveIntervals to new pass manager (#98118)
2024-07-10 19:34:48 +08:00
subreg-split-live-in-error.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
subreg-undef-def-with-other-subreg-defs.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
subvector-test.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
swdev282079.ll
…
swdev282079.mir
…
swdev373493.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
swdev380865.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
RegAllocGreedy: Un-disable test in expensive_checks builds
2025-01-07 12:21:21 +07:00
swdev503538-move-to-valu-stack-srd-physreg.ll
AMDGPU: Forcibly disable verifier in test
2025-01-07 22:46:46 +07:00
switch-default-block-unreachable.ll
…
switch-unreachable.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
swizzle-export.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
swizzle.bit.extract.ll
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
syncscopes.ll
…
tail-call-amdgpu-gfx.ll
[AMDGPU] Use absolute relocations when compiling for AMDPAL and Mesa3D (#67791)
2023-10-10 09:22:02 +02:00
tail-call-cgp.ll
…
tail-call-inreg-arguments.convergencetokens.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
tail-call-inreg-arguments.error.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
tail-call-inreg-arguments.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
tail-call-uniform-target-in-vgprs-issue110930.ll
AMDGPU: Work around machine verifier failure with convergence tokens
2024-10-04 16:59:23 +04:00
tail-dup-bundle.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
tail-duplication-convergent.ll
…
target-cpu.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
target-mem-intrinsic-metadata.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
tex-clause-antidep.ll
…
texture-input-merge.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
tgsplit.ll
…
threeaddr-wmma.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
tid-kd-xnack-any.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
tid-kd-xnack-off.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
tid-kd-xnack-on.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
tid-mul-func-xnack-all-any.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-mul-func-xnack-all-not-supported.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-mul-func-xnack-all-off.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-mul-func-xnack-all-on.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-mul-func-xnack-any-off-1.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-mul-func-xnack-any-off-2.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-mul-func-xnack-any-on-1.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-mul-func-xnack-any-on-2.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-mul-func-xnack-invalid-any-off-on.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-one-func-xnack-any.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-one-func-xnack-not-supported.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-one-func-xnack-off.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tid-one-func-xnack-on.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
tied-op-for-wwm-scratch-reg-spill-restore.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
token-factor-inline-limit-test.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
track-spilled-vgpr-liveness.mir
[AMDGPU] Add pseudo instructions for SGPR spill to VGPR (#69923)
2023-10-27 17:24:10 +05:30
trans-forwarding-hazards.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
transform-block-with-return-to-epilog.ll
[AMDGPU] Combine or remove redundant waitcnts at the end of each MBB (#87539)
2024-04-04 10:14:16 +01:00
trap-abis.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
trap.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
triv-disjoint-mem-access-neg-offset.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
true16-ra-pre-gfx11-regression-test.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
trunc-bitcast-vector.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
trunc-cmp-constant.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
trunc-combine.ll
AMDGPU: Implement isExtractVecEltCheap (#122460)
2025-01-17 08:38:01 +07:00
trunc-store-f64-to-f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
trunc-store-i1.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
trunc-store-i64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
trunc-store-vec-i16-to-i8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
trunc-store.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
trunc-vector-store-assertion-failure.ll
[AMDGPU] Remove duplicate -mtriple options in tests (#91576)
2024-05-09 10:59:25 +01:00
trunc.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
truncate-lshr-cast-build-vector-combine.ll
AMDGPU: Generalize truncate of shift of cast build_vector combine (#125617)
2025-02-04 11:46:30 +07:00
tti-unroll-prefs.ll
…
tuple-allocation-failure.ll
AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (#128677)
2025-02-25 18:22:32 +07:00
twoaddr-constrain.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
twoaddr-fma-f64.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
twoaddr-fma.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
twoaddr-mad.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
twoaddr-regsequence.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
twoaddr-wmma.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
uaddo.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
uaddsat.ll
[AMDGPU][True16][CodeGen] Update and/or/xor codegen pattern for i16 (#121835)
2025-01-13 16:48:00 -05:00
udiv64.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
udiv.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
udivrem24.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
udivrem64.r600.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
udivrem.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
uint_to_fp.f64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
uint_to_fp.i64.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
uint_to_fp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
uitofp.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen pattern for v_pack_b32_f16 (#121988)
2025-01-13 12:26:36 -05:00
umed3.ll
[AMDGPU][True16][CodeGen] true16 codegen pattern for v_med3_u/i16 (#121850)
2025-01-07 13:18:28 -05:00
unaligned-load-store.ll
[AMDGPU] Enable unaligned scratch accesses (#110219)
2024-10-11 08:50:49 +02:00
unallocatable-bundle-regression.mir
…
undef-build-vector.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
undef-copy-propagation.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
undef-subreg-use-after-coalesce.mir
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
undefined-physreg-sgpr-spill.mir
…
undefined-subreg-liverange.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
unexpected-reg-unit-state.mir
[NewPM][CodeGen] Port regallocfast to new pass manager (#94426)
2024-06-07 12:22:42 +08:00
unhandled-loop-condition-assertion.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
uniform_branch_with_floating_point_cond.ll
[AMDGPU] Emit S_CBRANCH_SCC for floating-point conditions. (#120588)
2024-12-19 11:20:43 -08:00
uniform-branch-intrinsic-cond.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
uniform-cfg.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
uniform-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
uniform-load-from-tid.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
uniform-loop-inside-nonuniform.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
uniform-phi-with-undef.ll
[DAG] Fold fdiv X, c2 -> fmul X, 1/c2 without AllowReciprocal if exact (#93882)
2024-06-09 12:28:20 +01:00
uniform-select.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
uniform-work-group-attribute-missing.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
uniform-work-group-multistep.ll
[AMDGPU][Attributor] Make AAAMDWavesPerEU honor existing attribute (#114438)
2024-12-11 16:50:06 -05:00
uniform-work-group-nested-function-calls.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
uniform-work-group-prevent-attribute-propagation.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
uniform-work-group-propagate-attribute.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
uniform-work-group-recursion-test.ll
[AMDGPU][Attributor] Make AAAMDWavesPerEU honor existing attribute (#114438)
2024-12-11 16:50:06 -05:00
uniform-work-group-test.ll
[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute (#114357)
2024-12-11 16:47:51 -05:00
unify-metadata.ll
…
unigine-liveness-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
unknown-processor.ll
[AMDGPU] Remove wavefrontsize feature from GFX10+ (#98400)
2024-07-16 01:02:25 -07:00
unnamed-function-resource-info.ll
[AMDGPU] Fix resource usage information for unnamed functions (#115320)
2024-11-07 18:24:54 +00:00
unpack-half.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
unroll.ll
…
unstructured-cfg-def-use-issue.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
unsupported-calls.ll
AMDGPU: Explicitly disable verifier in failing tests
2024-09-20 10:26:57 +04:00
unsupported-cc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
unsupported-code-object-version.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
unsupported-image-a16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
unsupported-image-g16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
unsupported-image-sample.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
update-lds-alignment.ll
…
update-phi.ll
…
urem64.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
urem-seteq-illegal-types.ll
…
urem.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
use_restore_frame_reg.mir
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
use-sgpr-multiple-times.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
usubo.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
usubsat.ll
[AMDGPU][True16][CodeGen] Update and/or/xor codegen pattern for i16 (#121835)
2025-01-13 16:48:00 -05:00
v1i64-kernel-arg.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
v1024.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
v_add_u64_pseudo_sdwa.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
v_ashr_pk.ll
AMDGPU: Add codegen support for gfx950 v_ashr_pk_i8/u8_i32 (#118304)
2024-12-02 19:23:12 -05:00
v_cmp_gfx11.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
v_cndmask.ll
PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)
2025-01-30 20:42:02 +07:00
v_cvt_pk_u8_f32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
v_mac_f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
v_mac.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
v_madak_f16.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
v_mov_b64_expand_and_shrink.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
v_mov_b64_expansion.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
v_pack.ll
[AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (#128784)
2025-02-25 20:04:57 -05:00
v_sat_pk_u8_i16.ll
[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#124131)
2025-01-24 09:12:32 +01:00
v_sub_u64_pseudo_sdwa.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
v_swap_b16.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
v_swap_b32.mir
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
valu-i1.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
valu-mask-write-hazard.mir
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
valu-read-sgpr-hazard-attrs.mir
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
valu-read-sgpr-hazard.mir
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
vccz-corrupt-bug-workaround.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
vcmp-saveexec-to-vcmpx-set-kill.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vcmp-saveexec-to-vcmpx.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vcmp-saveexec-to-vcmpx.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
vcmpx-exec-war-hazard.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
vcmpx-permlane16var-hazard.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vcmpx-permlane-hazard-sdwa.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vcmpx-permlane-hazard.mir
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
vector_rebroadcast.ll
[AMDGPU] Add tests for vector rebroadcast. (#91322)
2024-05-13 19:39:26 +01:00
vector_shuffle.packed.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
vector-alloca-addrspacecast.ll
…
vector-alloca-atomic.ll
…
vector-alloca-bitcast.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
vector-alloca-limits.ll
…
vector-alloca.ll
[AMDGPU] Remove duplicate -mtriple options in tests (#91576)
2024-05-09 10:59:25 +01:00
vector-extract-insert.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
vector-legalizer-divergence.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vector-spill-restore-to-other-vector-type.mir
…
vectorize-buffer-fat-pointer.ll
[AMDGPU] - Add address space for strided buffers (#74471)
2023-12-15 15:49:25 +01:00
vectorize-global-local.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vectorize-loads.ll
…
vectorize-unroll-metadata.ll
…
verifier-sdwa-cvt.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
verify-constant-bus-violations.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
verify-ds-gws-align.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
verify-duplicate-literal.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
verify-gfx12-gds.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
verify-gfx90a-aligned-vgprs.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
verify-image-vaddr-align.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
verify-image.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
verify-scalar-store.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
verify-sop.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
verify-vimage-vsample.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
verify-vopd-gfx12.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
verify-vopd.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
vertex-fetch-encoding.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vgpr_constant64_to_sgpr.mir
…
vgpr_constant_to_sgpr.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
vgpr-agpr-limit-gfx90a.ll
AMDGPU: Respect amdgpu-no-agpr in functions and with calls (#128147)
2025-02-23 09:00:37 +07:00
vgpr-descriptor-waterfall-loop-idom-update.ll
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
vgpr-large-tuple-alloc-error.ll
[AMDGPU] Pick available high VGPR for CSR SGPR spilling (#78669)
2024-01-24 07:08:43 +05:30
vgpr-liverange-ir.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
vgpr-liverange.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
vgpr-mark-last-scratch-load.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
vgpr-mark-last-scratch-load.mir
[AMDGPU] Fix test for expensive-checks build (#78687)
2024-01-19 11:32:02 +01:00
vgpr-remat-v_pk_mov_b32.mir
[AMDGPU] Add isAsCheapAsAMove for v_pk_mov_b32 (#127632)
2025-02-19 00:51:57 -05:00
vgpr-remat.mir
AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (#128677)
2025-02-25 18:22:32 +07:00
vgpr-spill-dead-frame-in-dbg-value.mir
…
vgpr-spill-emergency-stack-slot-compute.ll
…
vgpr-spill-emergency-stack-slot.ll
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
2024-02-09 09:20:25 +01:00
vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
[AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. (#109685)
2024-09-24 14:41:45 +05:30
vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
…
vgpr-spill-placement-issue61083.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
vgpr-spill-scc-clobber.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
vgpr-spill.mir
AMDGPU: Delete spills of undef values (#119684)
2024-12-17 13:08:38 +07:00
vgpr-tuple-allocation.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
vi-removed-intrinsics.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
virtregrewrite-undef-identity-copy.mir
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
visit-physreg-vgpr-imm-folding-bug.ll
…
vmem-to-salu-hazard.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vmem-vcc-hazard.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vni8-across-blocks.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
vni8-live-reg-opt.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
vop-shrink-frame-index.mir
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
vop-shrink-non-ssa.mir
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
vop-shrink.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vopc_dpp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vopc_dpp.mir
[AMDGPU][True16][MC] VOPC profile fake16 pseudo update (#113175)
2024-11-22 12:12:13 -05:00
vopd-combine.mir
[AMDGPU] Add VOPD combine dependency tests. NFC. (#104841)
2024-08-19 15:43:27 -07:00
vopd-src2acc-delay.mir
[AMDGPU] Introduce a pseudo mnemonic for S_DELAY_ALU in MIR. (#96004)
2024-06-20 15:59:08 -04:00
vselect64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vselect.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
vtx-fetch-branch.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
vtx-schedule.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
wait-before-stores-with-scope_sys.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wait-before-stores-with-scope_sys.mir
AMDGPU/GFX12: Insert waitcnts before stores with scope_sys (#82996)
2024-02-28 16:18:04 +01:00
wait.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
waitcnt-agpr.mir
[AMDGPU] Do not count implicit VGPRs in SIInsertWaitcnts (#109049)
2024-09-25 00:41:49 -07:00
waitcnt-back-edge-loop.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
waitcnt-bvh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
waitcnt-debug-non-first-terminators.mir
[AMDGPU] Skip terminators when forcing emit zero flag (#112116)
2024-10-14 11:46:18 -04:00
waitcnt-debug.mir
[DebugCounter] Add support for non-continous ranges. (#89470)
2024-05-28 12:40:39 +02:00
waitcnt-flat.ll
…
waitcnt-global-inv-wb.mir
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
waitcnt-loop-irreducible.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
waitcnt-loop-single-basic-block.mir
[llvm-project] Fix typo "propogate" (#114795)
2024-11-04 15:33:19 +00:00
waitcnt-looptest.ll
…
waitcnt-meta-instructions.mir
[AMDGPU] Remove Dwarf encodings for subregisters (#117891)
2025-01-06 14:51:16 -05:00
waitcnt-multiple-funcs.mir
[AMDGPU] Clear load addresses between functions (#102515)
2024-08-08 21:26:17 +02:00
waitcnt-no-redundant.mir
[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)
2023-12-15 12:33:32 +01:00
waitcnt-overflow.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
waitcnt-permute.mir
…
waitcnt-preexisting-vscnt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
waitcnt-preexisting.mir
AMDGPU/gfx12: avoid crashing on legacy waitcnt intrinsics (#92306)
2024-05-15 22:23:18 +02:00
waitcnt-sample-waw.mir
[AMDGPU] Fix image_msaa_load waitcnt insertion for pre-gfx12 (#90710)
2024-05-01 11:37:57 +01:00
waitcnt-skip-meta.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
waitcnt-vinterp.mir
[AMDGPU][True16][MC] VINTERP instructions supporting true16/fake16 (#113634)
2024-11-14 18:22:37 -05:00
waitcnt-vmcnt-loop.mir
[AMDGPU] Remove one case of vmcnt loop header flushing for GFX12 (#105550)
2024-08-23 10:31:33 +01:00
waitcnt-vmem-waw.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
waitcnt-vscnt.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
waitcnt-vscnt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
waitcnt.mir
[AMDGPU] Do not count implicit VGPRs in SIInsertWaitcnts (#109049)
2024-09-25 00:41:49 -07:00
waterfall_kills_scc.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
wave32.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
wave_dispatch_regs.ll
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
2025-02-04 08:19:05 +00:00
while-break.ll
Reapply "StructurizeCFG: Optimize phi insertion during ssa reconstruction (#101301)" (#114347)
2024-11-01 08:29:59 +08:00
whole-wave-register-copy.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
whole-wave-register-spill.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
widen_extending_scalar_loads.ll
…
widen-smrd-loads.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
widen-vselect-and-mask.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
wmma_modifiers.ll
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
wmma_multiple_32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma_multiple_64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-imm.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-iu-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-swmmac-index_key.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-imm.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-iu-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-swmmac-index_key.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-hazards-gfx12-w32.mir
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
wmma-hazards-gfx12-w64.mir
[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711)
2024-07-26 00:42:24 -07:00
wmma-hazards.mir
AMDGPU: update GFX11 wmma hazards (#76143)
2024-01-24 12:00:35 +01:00
workgroup-id-in-arch-sgprs.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
wqm-gfx11.ll
[test] Remove immarg parameter attribute from calls (#97432)
2024-07-03 09:02:31 +01:00
wqm-terminators.mir
[CodeGen][NewPM] Port SIWholeQuadMode to NPM. (#125833)
2025-02-05 18:44:57 +05:30
wqm.ll
[AMDGPU] SIWholeQuadMode: Ensure earliest WQM entry point for PS (#123266)
2025-01-19 15:50:33 +09:00
wqm.mir
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
write_register.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
write-register-vgpr-into-sgpr.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
wrong-transalu-pos-fix.ll
[AMDGPU] Remove duplicate -mtriple options in tests (#91576)
2024-05-09 10:59:25 +01:00
wwm-regalloc-error.ll
[AMDGPU] Split vgpr regalloc pipeline (#93526)
2024-09-30 19:55:42 +05:30
wwm-reserved-spill.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
wwm-reserved.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
wwm-spill-superclass-pseudo.mir
…
xfail.r600.bitcast.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
xnack-subtarget-feature-any.ll
[AMDGPU] Split GCNSubtarget into its own file. NFC. (#105525)
2024-08-21 19:11:02 +01:00
xnack-subtarget-feature-disabled.ll
[AMDGPU] Split GCNSubtarget into its own file. NFC. (#105525)
2024-08-21 19:11:02 +01:00
xnack-subtarget-feature-enabled.ll
[AMDGPU] Split GCNSubtarget into its own file. NFC. (#105525)
2024-08-21 19:11:02 +01:00
xnor.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
xor3-i1-const.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
xor3.ll
…
xor_add.ll
…
xor-r600.ll
[AMDGPU] Auto-generated some lit test patterns (NFC). (#94310)
2024-06-07 09:07:11 +05:30
xor.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
zero_extend.ll
[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)
2024-07-23 13:59:15 +05:30
zext-divergence-driven-isel.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
zext-i64-bit-operand.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
zext-lid.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.