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llvm-project/llvm/lib/Target/AMDGPU
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vporpo 494bc4ca12
[AMDGPU][SIInsertWaitcnts][NFC] Clean up loop (#179572) 
After merging https://github.com/llvm/llvm-project/pull/181760 this loop
no longer erases instructions while iterating. So this patch moves the
iteration increment inside the for statement.

Note: Replacing the loop with a range loop like `for (MachineInstr
&Instr : Block)` is not an NFC.
2026-02-20 10:34:50 -08:00
..
AsmParser
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
Disassembler
[AMDGPU][NFC] Use range-based for loops in KD reserved bytes checks (#182340)
2026-02-20 07:53:36 -08:00
MCA
Reapply "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321) (#180954)
2026-02-12 09:17:02 +01:00
MCTargetDesc
AMDGPU: Add syntax for s_wait_event values (#180272)
2026-02-09 08:29:55 +00:00
TargetInfo
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
Utils
[AMDGPU] Add VEXPORT encoding for gfx13 (#181788)
2026-02-19 08:46:50 +01:00
AMDGPU.h
[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)
2025-12-08 20:38:00 +05:30
AMDGPU.td
[AMDGPU] Add target features to guard DPP controls (#182391)
2026-02-20 07:59:10 -07:00
AMDGPUAliasAnalysis.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
AMDGPUAnnotateUniformValues.cpp
…
AMDGPUArgumentUsageInfo.cpp
[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)
2025-12-08 20:38:00 +05:30
AMDGPUArgumentUsageInfo.h
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
AMDGPUAsanInstrumentation.cpp
[llvm] Use ConstantInt::getAllOnesValue()
2025-12-09 12:02:39 +01:00
AMDGPUAsanInstrumentation.h
…
AMDGPUAsmPrinter.cpp
[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)
2026-01-26 14:16:36 +01:00
AMDGPUAsmPrinter.h
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
AMDGPUAtomicOptimizer.cpp
[llvm] Use ConstantInt::getAllOnesValue()
2025-12-09 12:02:39 +01:00
AMDGPUAttributes.def
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
AMDGPUAttributor.cpp
[NFC][AMDGPU] Remove unused getLDSSize (#181133)
2026-02-12 13:13:50 +00:00
AMDGPUBarrierLatency.cpp
[AMDGPU] Pre-GFX10 does not need added latency for workgroup fences (#177157)
2026-01-27 10:24:05 +09:00
AMDGPUBarrierLatency.h
[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutation (#168500)
2025-11-19 17:49:14 +09:00
AMDGPUCallingConv.td
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
AMDGPUCallLowering.cpp
[GISel][CallLowering] Keep IR types longer (#179946)
2026-02-05 16:37:08 +01:00
AMDGPUCallLowering.h
[AMDGPU] ISel & PEI for whole wave functions (#145858)
2025-07-21 10:39:09 +02:00
AMDGPUCodeGenPrepare.cpp
AMDGPU: Use fpmath metadata on f16 log/log10 intrinsics (#180489)
2026-02-17 09:58:43 +01:00
AMDGPUCombine.td
[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)
2025-10-24 17:25:00 +02:00
AMDGPUCombinerHelper.cpp
[AMDGPU] Remove NoSignedZerosFPMath uses (#178343)
2026-01-30 09:18:40 +08:00
AMDGPUCombinerHelper.h
[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)
2025-08-20 17:32:29 +02:00
AMDGPUCtorDtorLowering.cpp
…
AMDGPUCtorDtorLowering.h
…
AMDGPUExportClustering.cpp
[AMDGPU] Remove unused includes (NFC) (#141376)
2025-05-24 14:48:46 -07:00
AMDGPUExportClustering.h
…
AMDGPUExportKernelRuntimeHandles.cpp
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUExportKernelRuntimeHandles.h
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUFeatures.td
[NFCI][AMDGPU] Convert more SubtargetFeatures to use AMDGPUSubtargetFeature and X-macros (#177256)
2026-01-21 18:03:32 -05:00
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
…
AMDGPUGISel.td
[AMDGPU][GFX12.5] Reimplement monitor load as an atomic operation (#177343)
2026-02-09 09:57:27 +01:00
AMDGPUGlobalISelDivergenceLowering.cpp
[AMDGPU][GlobalISel][NFC] Filter getCandidatesForLowering to only process G_PHI (#181814)
2026-02-19 11:08:44 +05:30
AMDGPUGlobalISelUtils.cpp
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
AMDGPUGlobalISelUtils.h
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
AMDGPUHazardLatency.cpp
[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)
2026-02-03 11:10:28 +09:00
AMDGPUHazardLatency.h
[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)
2026-02-03 11:10:28 +09:00
AMDGPUHSAMetadataStreamer.cpp
[AMDGPU] Add the support for .cluster_dims code object metadata (#158721)
2025-09-15 16:13:07 -04:00
AMDGPUHSAMetadataStreamer.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
AMDGPUIGroupLP.cpp
Try To Guess SGMasks for Inline Asm Instructions (#155491)
2026-01-23 12:43:53 -06:00
AMDGPUIGroupLP.h
Remove unused <vector> inclusion (#166997)
2025-11-08 20:42:00 +00:00
AMDGPUImageIntrinsicOptimizer.cpp
[AMDGPU] Change placeholder from undef to poison (#130853)
2025-03-12 12:52:38 +00:00
AMDGPUInsertDelayAlu.cpp
[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180940)
2026-02-11 19:14:54 +00:00
AMDGPUInstCombineIntrinsic.cpp
AMDGPU: Strip sign bit operations on llvm.amdgcn.trig.preop uses (#179712)
2026-02-19 18:44:33 +01:00
AMDGPUInstrInfo.cpp
AMDGPU: Fix treating unknown mem operands as uniform (#170309)
2025-12-02 16:19:46 +00:00
AMDGPUInstrInfo.h
[AMDGPU] Support image atomic no return instructions (#150742)
2025-10-29 10:42:15 +08:00
AMDGPUInstrInfo.td
[AMDGPU][GFX12.5] Reimplement monitor load as an atomic operation (#177343)
2026-02-09 09:57:27 +01:00
AMDGPUInstructions.td
[AMDGPU] Fix and simplify patterns selecting fsub to v_fma_mix_f32 (#180169)
2026-02-06 14:39:13 +00:00
AMDGPUInstructionSelector.cpp
[AMDGPU] Fix opcode comparison logic for G_INTRINSIC (#156008)
2026-02-18 11:05:36 +00:00
AMDGPUInstructionSelector.h
[AMDGPU] Fix and simplify patterns selecting fsub to v_fma_mix_f32 (#180169)
2026-02-06 14:39:13 +00:00
AMDGPUISelDAGToDAG.cpp
[AMDGPU] Fix and simplify patterns selecting fsub to v_fma_mix_f32 (#180169)
2026-02-06 14:39:13 +00:00
AMDGPUISelDAGToDAG.h
[AMDGPU] Fix and simplify patterns selecting fsub to v_fma_mix_f32 (#180169)
2026-02-06 14:39:13 +00:00
AMDGPUISelLowering.cpp
AMDGPU: Use promotion to f32 path for log/log10 for f16 by default (#180240)
2026-02-16 20:25:45 +01:00
AMDGPUISelLowering.h
[AMDGPU] Implement llvm.fptosi.sat and llvm.fptoui.sat (#174726)
2026-01-30 17:07:40 +09:00
AMDGPULaneMaskUtils.h
[AMDGPU] Add CmpLG and OrN2 operators to LaneMaskConstants (#179493)
2026-02-04 10:55:56 +00:00
AMDGPULateCodeGenPrepare.cpp
[AMDGPU] LiveRegOptimizer: consider i8/i16 binops on SDWA (#155800)
2025-12-15 12:04:33 -05:00
AMDGPULegalizerInfo.cpp
AMDGPU: Use promotion to f32 path for log/log10 for f16 by default (#180240)
2026-02-16 20:25:45 +01:00
AMDGPULegalizerInfo.h
AMDGPU/GlobalISel: Fix broken exp10 lowering for f16 (#170708)
2025-12-08 10:35:40 +01:00
AMDGPULibCalls.cpp
Fix MSVC "not all control paths return a value" warning. NFC. (#182262)
2026-02-19 14:17:24 +00:00
AMDGPULibFunc.cpp
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135)
2026-02-19 11:49:32 +01:00
AMDGPULibFunc.h
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135)
2026-02-19 11:49:32 +01:00
AMDGPULowerBufferFatPointers.cpp
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
AMDGPULowerExecSync.cpp
[NFCI] replace getValueType with new getGlobalSize query (#177186)
2026-01-22 13:55:53 -05:00
AMDGPULowerIntrinsics.cpp
[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)
2025-09-16 14:49:48 -07:00
AMDGPULowerKernelArguments.cpp
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
AMDGPULowerKernelAttributes.cpp
[AMDGPU] Fix AMDGPULowerKernelAttributes not invalidating analysis (#175256)
2026-01-09 23:03:15 +00:00
AMDGPULowerModuleLDSPass.cpp
[AMDGPULowerLDS] Avoid unnecessary ptrtoint/inttoptr roundtrip (#181671)
2026-02-17 09:28:01 +01:00
AMDGPULowerVGPREncoding.cpp
[AMDGPU] Commute instructions to avoid VGPR MSB changes (#181918)
2026-02-18 19:44:50 -08:00
AMDGPULowerVGPREncoding.h
[AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (#156971)
2025-09-05 00:07:47 -07:00
AMDGPUMachineFunction.cpp
[AMDGPU] Remove NoSignedZerosFPMath uses (#178343)
2026-01-30 09:18:40 +08:00
AMDGPUMachineFunction.h
[AMDGPU] Remove NoSignedZerosFPMath uses (#178343)
2026-01-30 09:18:40 +08:00
AMDGPUMachineModuleInfo.cpp
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
AMDGPUMachineModuleInfo.h
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
…
AMDGPUMarkLastScratchLoad.cpp
Revert "[NFC][LiveStacks] Use vectors instead of map and unordred_map" (#180421)
2026-02-08 16:54:51 +00:00
AMDGPUMCInstLower.cpp
[AMDGPU] Introduce asyncmark/wait intrinsics (#180467)
2026-02-11 07:15:51 +00:00
AMDGPUMCInstLower.h
[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)
2025-09-24 11:27:26 -04:00
AMDGPUMCResourceInfo.cpp
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUMCResourceInfo.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUMemoryUtils.cpp
[NFCI] replace getValueType with new getGlobalSize query (#177186)
2026-01-22 13:55:53 -05:00
AMDGPUMemoryUtils.h
[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)
2025-11-25 15:43:18 +00:00
AMDGPUMIRFormatter.cpp
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
AMDGPUMIRFormatter.h
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
AMDGPUPassRegistry.def
[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)
2025-12-08 20:38:00 +05:30
AMDGPUPerfHintAnalysis.cpp
[llvm] Remove unused includes of SmallSet.h (NFC) (#154893)
2025-08-22 10:33:46 -07:00
AMDGPUPerfHintAnalysis.h
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
AMDGPUPostLegalizerCombiner.cpp
Fix typos and spelling errors across codebase (#156270)
2026-01-13 11:52:46 -05:00
AMDGPUPredicateControl.td
…
AMDGPUPreLegalizerCombiner.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
AMDGPUPreloadKernArgProlog.cpp
[AMDGPU] Enable kernarg preload on gfx1250 (#153686)
2025-08-14 16:29:53 -07:00
AMDGPUPreloadKernArgProlog.h
…
AMDGPUPreloadKernelArguments.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
AMDGPUPrepareAGPRAlloc.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
AMDGPUPrepareAGPRAlloc.h
AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)
2025-07-18 17:15:38 +09:00
AMDGPUPrintfRuntimeBinding.cpp
[AMDGPU] Skip printf runtime binding if function signature is unexpected (#177573)
2026-01-28 10:22:32 +00:00
AMDGPUPromoteAlloca.cpp
[RFC][IR] Remove Constant::isZeroValue (#181521)
2026-02-15 12:06:42 -05:00
AMDGPUPromoteKernelArguments.cpp
…
AMDGPUPTNote.h
…
AMDGPURegBankCombiner.cpp
[AMDGPU] Fix legacy index in fmed3 optimization (#177426)
2026-01-28 10:22:22 +00:00
AMDGPURegBankLegalize.cpp
AMDGPU/GlobalISel: Regbanklegalize rules for G_FREEZE (#179796)
2026-02-06 11:05:47 +01:00
AMDGPURegBankLegalizeHelper.cpp
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
AMDGPURegBankLegalizeHelper.h
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
AMDGPURegBankLegalizeRules.cpp
AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)
2026-02-20 09:44:58 -08:00
AMDGPURegBankLegalizeRules.h
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
AMDGPURegBankSelect.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
AMDGPURegisterBankInfo.cpp
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
AMDGPURegisterBankInfo.h
…
AMDGPURegisterBanks.td
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
AMDGPURemoveIncompatibleFunctions.cpp
[AMDGPU] Add target features to guard DPP controls (#182391)
2026-02-20 07:59:10 -07:00
AMDGPURemoveIncompatibleFunctions.h
…
AMDGPUReserveWWMRegs.cpp
[AMDGPU] Remove unused includes (NFC) (#141376)
2025-05-24 14:48:46 -07:00
AMDGPUReserveWWMRegs.h
[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM (#123722)
2025-03-10 17:36:35 +05:30
AMDGPUResourceUsageAnalysis.cpp
AMDGPU: Avoid crashing on statepoint-like pseudoinstructions (#170657)
2025-12-29 19:08:08 +01:00
AMDGPUResourceUsageAnalysis.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPURewriteAGPRCopyMFMA.cpp
Revert "[NFC][LiveStacks] Use vectors instead of map and unordred_map" (#180421)
2026-02-08 16:54:51 +00:00
AMDGPURewriteOutArguments.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
AMDGPURewriteUndefForPHI.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUSearchableTables.td
[AMDGPU] Add intrinsic exposing s_alloc_vgpr (#163951)
2026-02-10 09:28:31 +01:00
AMDGPUSelectionDAGInfo.cpp
[AMDGPU] TableGen-erate SDNode descriptions (#168248)
2025-11-17 00:10:07 +00:00
AMDGPUSelectionDAGInfo.h
[AMDGPU] TableGen-erate SDNode descriptions (#168248)
2025-11-17 00:10:07 +00:00
AMDGPUSetWavePriority.cpp
[llvm] Replace SmallSet with SmallPtrSet (NFC) (#154068)
2025-08-18 07:01:29 -07:00
AMDGPUSplitModule.cpp
[NFC] Implicit container copy cleanup (#174702)
2026-01-14 11:16:32 +01:00
AMDGPUSplitModule.h
…
AMDGPUSubtarget.cpp
[NFCI][AMDGPU] Use GET_SUBTARGETINFO_MACRO in GCNSubtarget.h and R600Subtarget.h (#177402)
2026-01-25 09:38:42 -05:00
AMDGPUSubtarget.h
[NFC][AMDGPU] Remove unused/unimplemented getWavesPerEU variants (#181131)
2026-02-12 14:07:35 +01:00
AMDGPUSwLowerLDS.cpp
[AMDGPU] Avoid unnecessary zero-index GEPs
2026-02-13 15:10:42 +01:00
AMDGPUTargetMachine.cpp
[AMDGPU][NPM] Add target-specific register allocation options (#178889)
2026-02-04 11:27:47 +05:30
AMDGPUTargetMachine.h
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[AMDGPU] Enable sinking of free vector ops that will be folded into their uses (#162580)
2026-02-09 14:14:31 -05:00
AMDGPUTargetTransformInfo.h
[TTI] Add VectorInstrContext for context-aware insert/extract costs. (#175982)
2026-01-27 16:30:29 +00:00
AMDGPUUniformIntrinsicCombine.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
AMDGPUUnifyDivergentExitNodes.cpp
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
AMDGPUUnifyDivergentExitNodes.h
…
AMDGPUWaitSGPRHazards.cpp
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
AMDGPUWaitSGPRHazards.h
…
AMDKernelCodeT.h
…
BUFInstructions.td
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
CaymanInstructions.td
…
CMakeLists.txt
[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)
2026-02-03 11:10:28 +09:00
DSDIRInstructions.td
[AMDGPU] Add VDSDIR encoding to gfx13 (#181620)
2026-02-17 09:25:14 +01:00
DSInstructions.td
[AMDGPU][NFC] Use RegisterOperand instead of RegisterClass (#180574)
2026-02-10 16:47:46 +00:00
EvergreenInstructions.td
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
EXPInstructions.td
[AMDGPU] Add VEXPORT encoding for gfx13 (#181788)
2026-02-19 08:46:50 +01:00
FLATInstructions.td
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
GCNCreateVOPD.cpp
[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)
2026-01-30 15:13:33 +00:00
GCNDPPCombine.cpp
[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)
2026-01-23 00:19:03 -08:00
GCNDPPCombine.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
GCNHazardRecognizer.cpp
[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)
2026-01-26 14:16:36 +01:00
GCNHazardRecognizer.h
[AMDGPU] Refactor hazard recognizer for VALU-pipeline hazards. NFCI. (#168801)
2025-12-01 10:59:52 -08:00
GCNILPSched.cpp
…
GCNIterativeScheduler.cpp
[AMDGPU] Iterative scheduling must behave the same with/without debug (#178460)
2026-02-02 09:15:48 -06:00
GCNIterativeScheduler.h
[AMDGPU] Teach iterative schedulers about IGLP (#134953)
2025-04-11 15:34:49 -07:00
GCNMinRegStrategy.cpp
…
GCNNSAReassign.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
GCNNSAReassign.h
…
GCNPreRALongBranchReg.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
GCNPreRALongBranchReg.h
…
GCNPreRAOptimizations.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
GCNPreRAOptimizations.h
…
GCNProcessors.td
[AMDGPU] Define new target gfx1170 (#180185)
2026-02-06 14:38:50 +01:00
GCNRegPressure.cpp
[AMDGPU] Rematerialize VGPR candidates when SGPR spills results in VGPR Excess (#168079)
2026-01-16 09:08:55 +01:00
GCNRegPressure.h
[AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR (#170335)
2026-01-22 12:22:39 +01:00
GCNRewritePartialRegUses.cpp
[NFC][CodeGen] Add helper function to check SubReg validity (#181489)
2026-02-19 12:39:11 -08:00
GCNRewritePartialRegUses.h
…
GCNSchedStrategy.cpp
[AMDGPU] Fix handling of setting register classes in MFMA scheduler rewrite stage (#181047)
2026-02-19 21:01:03 +01:00
GCNSchedStrategy.h
[AMDGPU][Scheduler] Fix inconsistent MI slots after rematerialization revert (#180646)
2026-02-12 01:42:04 +01:00
GCNSubtarget.cpp
[NFCI][AMDGPU] Final touch before moving to GET_SUBTARGETINFO_MACRO (#177401)
2026-01-22 17:33:17 +00:00
GCNSubtarget.h
[AMDGPU] Add target features to guard DPP controls (#182391)
2026-02-20 07:59:10 -07:00
GCNVOPDUtils.cpp
[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)
2026-01-30 15:13:33 +00:00
GCNVOPDUtils.h
[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)
2025-07-10 14:15:01 -07:00
MIMGInstructions.td
[AMDGPU] Limit tensor load/store to gfx1250 only. NFC (#179737)
2026-02-05 14:04:47 -08:00
R600.h
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
R600.td
CodeGen: Make all targets override pseudos with pointers (#159881)
2025-11-26 14:57:14 +00:00
R600AsmPrinter.cpp
…
R600AsmPrinter.h
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
[NFCI][AMDGPU] Use GET_SUBTARGETINFO_MACRO in GCNSubtarget.h and R600Subtarget.h (#177402)
2026-01-25 09:38:42 -05:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
R600ExpandSpecialInstrs.cpp
[CodeGen] Remove FinalizeMachineBundles pass (#149806)
2025-07-23 11:36:49 +01:00
R600FrameLowering.cpp
…
R600FrameLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
R600InstrInfo.h
[TableGen] Return int32_t from InstrMapping table lookup functions. NFC. (#182079)
2026-02-18 18:49:58 +00:00
R600InstrInfo.td
…
R600Instructions.td
[AMDGPU] Use FPImmLeaf for float constants, fix build_vector patterns (#178018)
2026-01-28 10:51:42 +01:00
R600ISelDAGToDAG.cpp
[AMDGPU] Remove unused includes (NFC) (#141376)
2025-05-24 14:48:46 -07:00
R600ISelLowering.cpp
Reapply "R600: Remove softPromoteHalfType (#177420)" (#178013)
2026-01-26 18:49:26 +00:00
R600ISelLowering.h
R600: Really remove softPromoteHalfType (#178040)
2026-01-26 20:46:37 +00:00
R600MachineCFGStructurizer.cpp
Reland "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176277)
2026-01-16 13:05:06 -08:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600MCInstLower.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
R600OpenCLImageTypeLoweringPass.cpp
…
R600OptimizeVectorRegisters.cpp
[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)
2026-02-03 14:24:31 +00:00
R600Packetizer.cpp
[TableGen] Add mapping from processor ID to resource index for packetizer (#158182)
2025-09-17 09:12:37 +08:00
R600Processors.td
[NFCI][AMDGPU] Use GET_SUBTARGETINFO_MACRO in GCNSubtarget.h and R600Subtarget.h (#177402)
2026-01-25 09:38:42 -05:00
R600RegisterInfo.cpp
…
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
…
R600Subtarget.h
[NFCI][AMDGPU] Use GET_SUBTARGETINFO_MACRO in GCNSubtarget.h and R600Subtarget.h (#177402)
2026-01-25 09:38:42 -05:00
R600TargetMachine.cpp
[Codegen][NewPM] Explicitly Nest Passes in CodegenPassBuilder (#169867)
2025-12-16 15:42:28 -08:00
R600TargetMachine.h
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
R600TargetTransformInfo.cpp
[TTI] Add VectorInstrContext for context-aware insert/extract costs. (#175982)
2026-01-27 16:30:29 +00:00
R600TargetTransformInfo.h
[TTI] Add VectorInstrContext for context-aware insert/extract costs. (#175982)
2026-01-27 16:30:29 +00:00
R700Instructions.td
…
SIAnnotateControlFlow.cpp
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
SIDefines.h
AMDGPU: Add syntax for s_wait_event values (#180272)
2026-02-09 08:29:55 +00:00
SIFixSGPRCopies.cpp
[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)
2026-02-03 14:24:31 +00:00
SIFixSGPRCopies.h
…
SIFixVGPRCopies.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
SIFixVGPRCopies.h
…
SIFoldOperands.cpp
[AMDGPU] Clear no convergence flag on operand folding. NFCI (#179438)
2026-02-03 10:46:26 -08:00
SIFoldOperands.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SIFormMemoryClauses.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
SIFormMemoryClauses.h
…
SIFrameLowering.cpp
[AMDGPU] Implement llvm.sponentry (#176357)
2026-02-03 15:02:07 +01:00
SIFrameLowering.h
[CodeGen] Replace (Min,Max)CSFrameIndex with flag on frame object [NFCI] (#170905)
2025-12-06 14:00:55 -08:00
SIInsertHardClauses.cpp
[AMDGPU] Adjust hard clause rules for gfx1250 (#152592)
2025-08-07 14:59:31 -07:00
SIInsertWaitcnts.cpp
[AMDGPU][SIInsertWaitcnts][NFC] Clean up loop (#179572)
2026-02-20 10:34:50 -08:00
SIInstrFormats.td
CodeGen: Add RegisterClass by HwMode (#158269)
2025-09-19 20:08:51 +09:00
SIInstrInfo.cpp
[AMDGPU] Add target features to guard DPP controls (#182391)
2026-02-20 07:59:10 -07:00
SIInstrInfo.h
[TableGen] Return int32_t from InstrMapping table lookup functions. NFC. (#182079)
2026-02-18 18:49:58 +00:00
SIInstrInfo.td
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
SIInstructions.td
[AMDGPU][GFX12.5] Reimplement monitor load as an atomic operation (#177343)
2026-02-09 09:57:27 +01:00
SIISelLowering.cpp
[AMDGPU] Align loop headers to prevent instruction fetch split on GFX950 (#181999)
2026-02-19 14:18:44 -05:00
SIISelLowering.h
[AMDGPU] Align loop headers to prevent instruction fetch split on GFX950 (#181999)
2026-02-19 14:18:44 -05:00
SILateBranchLowering.cpp
[AMDGPU] Teach SILateBranchLowering pass to preserve MachineLoopInfo (#178276)
2026-01-29 22:23:00 +05:30
SILoadStoreOptimizer.cpp
[AMDGPU] Fix LDS address correction in promoteConstantOffsetToImm for async stores (#180220)
2026-02-10 13:53:51 -08:00
SILoadStoreOptimizer.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SILowerControlFlow.cpp
[AMDGPU] Fix DomTree preservation in SILowerControlFlow when nodes are removed (#176691)
2026-01-25 09:45:44 +05:30
SILowerControlFlow.h
…
SILowerI1Copies.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
SILowerI1Copies.h
AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)
2025-03-12 12:09:37 +01:00
SILowerSGPRSpills.cpp
CodeGen: Remove TRI arguments from stack load/store hooks (#158240)
2025-11-10 16:24:39 -08:00
SILowerSGPRSpills.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SILowerWWMCopies.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
SILowerWWMCopies.h
…
SIMachineFunctionInfo.cpp
[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)
2026-02-03 14:24:31 +00:00
SIMachineFunctionInfo.h
[AMDGPU] Remove NoSignedZerosFPMath uses (#178343)
2026-01-30 09:18:40 +08:00
SIMachineScheduler.cpp
[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)
2026-02-03 14:24:31 +00:00
SIMachineScheduler.h
[CodeGen] Use VirtRegOrUnit where appropriate (NFCI) (#167730)
2025-11-13 10:26:58 +00:00
SIMemoryLegalizer.cpp
[AMDGPU][GFX12.5] Add support for emitting memory operations with nv bit set (#179413)
2026-02-06 11:35:46 +01:00
SIModeRegister.cpp
…
SIModeRegisterDefaults.cpp
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
SIModeRegisterDefaults.h
…
SIOptimizeExecMasking.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
SIOptimizeExecMasking.h
…
SIOptimizeExecMaskingPreRA.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
SIOptimizeExecMaskingPreRA.h
…
SIOptimizeVGPRLiveRange.cpp
[LLVM][CodeGen] Remove pass initialization calls from pass constructors (#173061)
2026-01-21 08:44:51 -08:00
SIOptimizeVGPRLiveRange.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SIPeepholeSDWA.cpp
Reland "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176277)
2026-01-16 13:05:06 -08:00
SIPeepholeSDWA.h
…
SIPostRABundler.cpp
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149)
2026-02-06 09:05:14 -08:00
SIPostRABundler.h
…
SIPreAllocateWWMRegs.cpp
[regalloc][LiveRegMatrix][AMDGPU] Fix LiveInterval dangling pointers in LiveRegMatrix. (#168556)
2026-01-27 16:08:58 +01:00
SIPreAllocateWWMRegs.h
…
SIPreEmitPeephole.cpp
[AMDGPU] Teach SIPreEmitPeephole pass to preserve MachineLoopInfo (#178868)
2026-02-17 20:57:47 +05:30
SIProgramInfo.cpp
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
SIProgramInfo.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
SIRegisterInfo.cpp
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
SIRegisterInfo.h
[RegAlloc] Change the computation of CSRCost (#177226)
2026-02-04 10:08:57 -08:00
SIRegisterInfo.td
[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)
2026-01-20 19:14:59 -05:00
SISchedule.td
AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)
2025-07-21 10:09:42 -07:00
SIShrinkInstructions.cpp
[AMDGPU] Optimize S_OR_B32 to S_ADDK_I32 where possible (#177949)
2026-02-07 09:10:12 +00:00
SIShrinkInstructions.h
…
SIWholeQuadMode.cpp
[AMDGPU] Fix crash in SIWholeQuadMode with debug instructions. (#178282)
2026-01-30 02:11:07 +01:00
SIWholeQuadMode.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SMInstructions.td
[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)
2026-01-26 14:16:36 +01:00
SOPInstructions.td
[AMDGPU] Introduce asyncmark/wait intrinsics (#180467)
2026-02-11 07:15:51 +00:00
VIInstrFormats.td
…
VINTERPInstructions.td
[AMDGPU] Simplify class VINTERPe. NFC. (#175006)
2026-01-08 16:18:42 +00:00
VOP1Instructions.td
[AMDGPU] Ensure all PERMLANE instructions are marked as convergent (#182162)
2026-02-20 07:02:47 -06:00
VOP2Instructions.td
[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)
2026-01-20 19:14:59 -05:00
VOP3Instructions.td
[AMDGPU] Ensure all PERMLANE instructions are marked as convergent (#182162)
2026-02-20 07:02:47 -06:00
VOP3PInstructions.td
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
VOPCInstructions.td
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
VOPDInstructions.td
[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516)
2025-09-09 10:54:18 -04:00
VOPInstructions.td
[AMDGPU] Add fp8/bf8 conversion instructions for gfx1170 (#180191)
2026-02-09 13:56:43 +01:00