Alexander Weinrauch 3b16468814

[AMDGPU] Global and Buffer loads to LDS should not increase lgkmcnt (#179305) ...

`global_load_lds` and `buffer_load to lds` do only increment `vmcnt` and
not touch `lgkmcnt`. This causes invalid `waitcnts` for some Triton
kernels, similar to the added lit tests.

Note that the change for buffer ops is not necesssary, i.e. the lit test
passes even before this PR, because it seems like `SIInsertWaitcnts`
does not use `LGKM_CNT` for buffer ops. But this change might prevent a
bug in the future.

2026-02-05 09:36:00 -08:00

..

AsmParser

[AMDGPU][MC] Allow nodone etc. in exp instructions (#172749)

2026-02-04 10:29:07 -08:00

Disassembler

[AMDGPU] Add VOP1 support for gfx13 (#177603)

2026-01-27 13:40:10 +01:00

MCA

[Target] Add "override" where appropriate (NFC) (#165083)

2025-10-25 06:23:43 -07:00

MCTargetDesc

[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)

2026-02-03 14:24:31 +00:00

TargetInfo

[llvm] annotate interfaces in llvm/Target for DLL export (#143615)

2025-06-17 13:28:45 -07:00

Utils

[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)

2026-01-31 10:46:59 -08:00

AMDGPU.h

[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)

2025-12-08 20:38:00 +05:30

AMDGPU.td

[NFC][AMDGPU] Reorganize gfx125x features (#179843)

2026-02-04 20:46:08 -08:00

AMDGPUAliasAnalysis.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUAliasAnalysis.h

…

AMDGPUAlwaysInlinePass.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPUAnnotateUniformValues.cpp

…

AMDGPUArgumentUsageInfo.cpp

[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)

2025-12-08 20:38:00 +05:30

AMDGPUArgumentUsageInfo.h

[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)

2025-12-08 20:38:00 +05:30

AMDGPUAsanInstrumentation.cpp

[llvm] Use ConstantInt::getAllOnesValue()

2025-12-09 12:02:39 +01:00

AMDGPUAsanInstrumentation.h

…

AMDGPUAsmPrinter.cpp

[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)

2026-01-26 14:16:36 +01:00

AMDGPUAsmPrinter.h

AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)

2025-08-15 16:33:06 +01:00

AMDGPUAtomicOptimizer.cpp

[llvm] Use ConstantInt::getAllOnesValue()

2025-12-09 12:02:39 +01:00

AMDGPUAttributes.def

[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)

2025-09-15 15:04:33 -04:00

AMDGPUAttributor.cpp

AMDGPU: Add support for llvm.trap to handling of intrinsics with !nocallback (#175230)

2026-01-30 08:26:40 -06:00

AMDGPUBarrierLatency.cpp

[AMDGPU] Pre-GFX10 does not need added latency for workgroup fences (#177157)

2026-01-27 10:24:05 +09:00

AMDGPUBarrierLatency.h

[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutation (#168500)

2025-11-19 17:49:14 +09:00

AMDGPUCallingConv.td

AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)

2026-01-22 18:34:06 +00:00

AMDGPUCallLowering.cpp

[GISel][CallLowering] Keep IR types longer (#179946)

2026-02-05 16:37:08 +01:00

AMDGPUCallLowering.h

[AMDGPU] ISel & PEI for whole wave functions (#145858)

2025-07-21 10:39:09 +02:00

AMDGPUCodeGenPrepare.cpp

AMDGPU: Use SimplifyQuery in AMDGPUCodeGenPrepare (#179133)

2026-02-02 09:33:16 +01:00

AMDGPUCombine.td

[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)

2025-10-24 17:25:00 +02:00

AMDGPUCombinerHelper.cpp

[AMDGPU] Remove NoSignedZerosFPMath uses (#178343)

2026-01-30 09:18:40 +08:00

AMDGPUCombinerHelper.h

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

AMDGPUCtorDtorLowering.cpp

…

AMDGPUCtorDtorLowering.h

…

AMDGPUExportClustering.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUExportClustering.h

…

AMDGPUExportKernelRuntimeHandles.cpp

AMDGPU: Move enqueued block handling into clang (#128519)

2025-03-10 19:54:04 +07:00

AMDGPUExportKernelRuntimeHandles.h

AMDGPU: Move enqueued block handling into clang (#128519)

2025-03-10 19:54:04 +07:00

AMDGPUFeatures.td

[NFCI][AMDGPU] Convert more SubtargetFeatures to use AMDGPUSubtargetFeature and X-macros (#177256)

2026-01-21 18:03:32 -05:00

AMDGPUFrameLowering.cpp

…

AMDGPUFrameLowering.h

…

AMDGPUGenRegisterBankInfo.def

…

AMDGPUGISel.td

[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)

2026-02-05 11:51:25 +01:00

AMDGPUGlobalISelDivergenceLowering.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUGlobalISelUtils.cpp

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

AMDGPUGlobalISelUtils.h

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

AMDGPUHazardLatency.cpp

[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)

2026-02-03 11:10:28 +09:00

AMDGPUHazardLatency.h

[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)

2026-02-03 11:10:28 +09:00

AMDGPUHSAMetadataStreamer.cpp

[AMDGPU] Add the support for .cluster_dims code object metadata (#158721)

2025-09-15 16:13:07 -04:00

AMDGPUHSAMetadataStreamer.h

[Target] Add "override" where appropriate (NFC) (#165083)

2025-10-25 06:23:43 -07:00

AMDGPUIGroupLP.cpp

Try To Guess SGMasks for Inline Asm Instructions (#155491)

2026-01-23 12:43:53 -06:00

AMDGPUIGroupLP.h

Remove unused <vector> inclusion (#166997)

2025-11-08 20:42:00 +00:00

AMDGPUImageIntrinsicOptimizer.cpp

[AMDGPU] Change placeholder from undef to poison (#130853)

2025-03-12 12:52:38 +00:00

AMDGPUInsertDelayAlu.cpp

[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)

2026-01-26 14:16:36 +01:00

AMDGPUInstCombineIntrinsic.cpp

AMDGPU: Fix incorrect fold of undef for llvm.amdgcn.trig.preop (#179025)

2026-02-04 17:56:55 +01:00

AMDGPUInstrInfo.cpp

AMDGPU: Fix treating unknown mem operands as uniform (#170309)

2025-12-02 16:19:46 +00:00

AMDGPUInstrInfo.h

[AMDGPU] Support image atomic no return instructions (#150742)

2025-10-29 10:42:15 +08:00

AMDGPUInstrInfo.td

Revert "[AMDGPU] Replace AMDGPUISD::FFBH_I32 with ISD::CTLS" (#178837)

2026-01-29 21:19:15 -08:00

AMDGPUInstructions.td

[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)

2026-02-05 11:51:25 +01:00

AMDGPUInstructionSelector.cpp

[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)

2026-02-05 11:51:25 +01:00

AMDGPUInstructionSelector.h

[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)

2026-02-05 11:51:25 +01:00

AMDGPUISelDAGToDAG.cpp

[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)

2026-02-05 11:51:25 +01:00

AMDGPUISelDAGToDAG.h

[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)

2026-02-05 11:51:25 +01:00

AMDGPUISelLowering.cpp

[AMDGPU] Implement llvm.fptosi.sat and llvm.fptoui.sat (#174726)

2026-01-30 17:07:40 +09:00

AMDGPUISelLowering.h

[AMDGPU] Implement llvm.fptosi.sat and llvm.fptoui.sat (#174726)

2026-01-30 17:07:40 +09:00

AMDGPULaneMaskUtils.h

[AMDGPU] Add CmpLG and OrN2 operators to LaneMaskConstants (#179493)

2026-02-04 10:55:56 +00:00

AMDGPULateCodeGenPrepare.cpp

[AMDGPU] LiveRegOptimizer: consider i8/i16 binops on SDWA (#155800)

2025-12-15 12:04:33 -05:00

AMDGPULegalizerInfo.cpp

[AMDGPU] Implement llvm.sponentry (#176357)

2026-02-03 15:02:07 +01:00

AMDGPULegalizerInfo.h

AMDGPU/GlobalISel: Fix broken exp10 lowering for f16 (#170708)

2025-12-08 10:35:40 +01:00

AMDGPULibCalls.cpp

AMDGPU: Add nofpclass when expanding pow (#177933)

2026-02-05 07:40:21 +01:00

AMDGPULibFunc.cpp

…

AMDGPULibFunc.h

…

AMDGPULowerBufferFatPointers.cpp

[LowerMemIntrinsics] Optimize memset lowering (#169040)

2026-02-04 13:35:13 +01:00

AMDGPULowerExecSync.cpp

[NFCI] replace getValueType with new getGlobalSize query (#177186)

2026-01-22 13:55:53 -05:00

AMDGPULowerIntrinsics.cpp

[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)

2025-09-16 14:49:48 -07:00

AMDGPULowerKernelArguments.cpp

Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)

2026-01-20 16:39:08 +00:00

AMDGPULowerKernelAttributes.cpp

[AMDGPU] Fix AMDGPULowerKernelAttributes not invalidating analysis (#175256)

2026-01-09 23:03:15 +00:00

AMDGPULowerModuleLDSPass.cpp

[NFCI] replace getValueType with new getGlobalSize query (#177186)

2026-01-22 13:55:53 -05:00

AMDGPULowerVGPREncoding.cpp

[AMDGPU][NFC] Refine the representation of MODE register values. (#177574)

2026-01-26 13:10:24 +00:00

AMDGPULowerVGPREncoding.h

[AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (#156971)

2025-09-05 00:07:47 -07:00

AMDGPUMachineFunction.cpp

[AMDGPU] Remove NoSignedZerosFPMath uses (#178343)

2026-01-30 09:18:40 +08:00

AMDGPUMachineFunction.h

[AMDGPU] Remove NoSignedZerosFPMath uses (#178343)

2026-01-30 09:18:40 +08:00

AMDGPUMachineModuleInfo.cpp

[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)

2025-09-10 11:41:43 +02:00

AMDGPUMachineModuleInfo.h

[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)

2025-09-10 11:41:43 +02:00

AMDGPUMacroFusion.cpp

…

AMDGPUMacroFusion.h

…

AMDGPUMarkLastScratchLoad.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUMCInstLower.cpp

AMDGPU: Avoid crashing on statepoint-like pseudoinstructions (#170657)

2025-12-29 19:08:08 +01:00

AMDGPUMCInstLower.h

[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)

2025-09-24 11:27:26 -04:00

AMDGPUMCResourceInfo.cpp

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUMCResourceInfo.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUMemoryUtils.cpp

[NFCI] replace getValueType with new getGlobalSize query (#177186)

2026-01-22 13:55:53 -05:00

AMDGPUMemoryUtils.h

[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)

2025-11-25 15:43:18 +00:00

AMDGPUMIRFormatter.cpp

[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)

2026-01-31 10:46:59 -08:00

AMDGPUMIRFormatter.h

[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)

2026-01-31 10:46:59 -08:00

AMDGPUPassRegistry.def

[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)

2025-12-08 20:38:00 +05:30

AMDGPUPerfHintAnalysis.cpp

[llvm] Remove unused includes of SmallSet.h (NFC) (#154893)

2025-08-22 10:33:46 -07:00

AMDGPUPerfHintAnalysis.h

[llvm] Use "= default" (NFC) (#166088)

2025-11-02 17:16:47 -08:00

AMDGPUPostLegalizerCombiner.cpp

Fix typos and spelling errors across codebase (#156270)

2026-01-13 11:52:46 -05:00

AMDGPUPredicateControl.td

…

AMDGPUPreLegalizerCombiner.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPUPreloadKernArgProlog.cpp

[AMDGPU] Enable kernarg preload on gfx1250 (#153686)

2025-08-14 16:29:53 -07:00

AMDGPUPreloadKernArgProlog.h

…

AMDGPUPreloadKernelArguments.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPUPrepareAGPRAlloc.cpp

AMDGPU: Start using AV_MOV_B64_IMM_PSEUDO (#154500)

2025-08-22 13:59:36 +09:00

AMDGPUPrepareAGPRAlloc.h

AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)

2025-07-18 17:15:38 +09:00

AMDGPUPrintfRuntimeBinding.cpp

[AMDGPU] Skip printf runtime binding if function signature is unexpected (#177573)

2026-01-28 10:22:32 +00:00

AMDGPUPromoteAlloca.cpp

[AMDGPU][SROA] Unify cast chain implementations (#177945)

2026-02-03 11:12:02 +00:00

AMDGPUPromoteKernelArguments.cpp

…

AMDGPUPTNote.h

…

AMDGPURegBankCombiner.cpp

[AMDGPU] Fix legacy index in fmed3 optimization (#177426)

2026-01-28 10:22:22 +00:00

AMDGPURegBankLegalize.cpp

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)

2026-02-02 17:55:42 +01:00

AMDGPURegBankLegalizeHelper.cpp

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize (#179441)

2026-02-04 10:20:30 +00:00

AMDGPURegBankLegalizeHelper.h

Reland "[AMDGPU][GlobalISel] Add RegBankLegalize support for G_MUL (#… (#177481)

2026-01-22 14:59:52 -08:00

AMDGPURegBankLegalizeRules.cpp

[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)

2026-02-05 16:35:31 +00:00

AMDGPURegBankLegalizeRules.h

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)

2026-02-02 17:55:42 +01:00

AMDGPURegBankSelect.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

AMDGPURegisterBankInfo.cpp

[NFC][LLVM] Make constrainSelectedInstRegOperands return void (#179501)

2026-02-04 08:59:16 +01:00

AMDGPURegisterBankInfo.h

…

AMDGPURegisterBanks.td

AMDGPU: Start using RegClassByHwMode for wavesize operands

2025-11-11 15:07:59 -08:00

AMDGPURemoveIncompatibleFunctions.cpp

[AMDGPU] Remove wave64 functions (#153690)

2025-08-14 15:54:33 -07:00

AMDGPURemoveIncompatibleFunctions.h

…

AMDGPUReserveWWMRegs.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUReserveWWMRegs.h

[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM (#123722)

2025-03-10 17:36:35 +05:30

AMDGPUResourceUsageAnalysis.cpp

AMDGPU: Avoid crashing on statepoint-like pseudoinstructions (#170657)

2025-12-29 19:08:08 +01:00

AMDGPUResourceUsageAnalysis.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPURewriteAGPRCopyMFMA.cpp

[AMDGPU] Fix AGPR_32 reg assign for mfma scale ops (#168964)

2025-12-02 13:41:16 -05:00

AMDGPURewriteOutArguments.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPURewriteUndefForPHI.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUSearchableTables.td

AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)

2025-12-09 23:13:33 +00:00

AMDGPUSelectionDAGInfo.cpp

[AMDGPU] TableGen-erate SDNode descriptions (#168248)

2025-11-17 00:10:07 +00:00

AMDGPUSelectionDAGInfo.h

[AMDGPU] TableGen-erate SDNode descriptions (#168248)

2025-11-17 00:10:07 +00:00

AMDGPUSetWavePriority.cpp

[llvm] Replace SmallSet with SmallPtrSet (NFC) (#154068)

2025-08-18 07:01:29 -07:00

AMDGPUSplitModule.cpp

[NFC] Implicit container copy cleanup (#174702)

2026-01-14 11:16:32 +01:00

AMDGPUSplitModule.h

…

AMDGPUSubtarget.cpp

[NFCI][AMDGPU] Use GET_SUBTARGETINFO_MACRO in GCNSubtarget.h and R600Subtarget.h (#177402)

2026-01-25 09:38:42 -05:00

AMDGPUSubtarget.h

[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)

2026-01-26 14:16:36 +01:00

AMDGPUSwLowerLDS.cpp

Fix typos and spelling errors across codebase (#156270)

2026-01-13 11:52:46 -05:00

AMDGPUTargetMachine.cpp

[AMDGPU][NPM] Add target-specific register allocation options (#178889)

2026-02-04 11:27:47 +05:30

AMDGPUTargetMachine.h

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

AMDGPUTargetObjectFile.cpp

…

AMDGPUTargetObjectFile.h

…

AMDGPUTargetTransformInfo.cpp

[LowerMemIntrinsics] Optimize memset lowering (#169040)

2026-02-04 13:35:13 +01:00

AMDGPUTargetTransformInfo.h

[TTI] Add VectorInstrContext for context-aware insert/extract costs. (#175982)

2026-01-27 16:30:29 +00:00

AMDGPUUniformIntrinsicCombine.cpp

[AMDGPU] Add optimization for llvm.amdgcn.wave.shuffle in uniform cases (#174795)

2026-01-14 17:49:42 +00:00

AMDGPUUnifyDivergentExitNodes.cpp

Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)

2025-11-03 20:59:48 +01:00

AMDGPUUnifyDivergentExitNodes.h

…

AMDGPUWaitSGPRHazards.cpp

[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)

2026-01-31 10:46:59 -08:00

AMDGPUWaitSGPRHazards.h

…

AMDKernelCodeT.h

…

BUFInstructions.td

[AMDGPU] Global and Buffer loads to LDS should not increase lgkmcnt (#179305)

2026-02-05 09:36:00 -08:00

CaymanInstructions.td

…

CMakeLists.txt

[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)

2026-02-03 11:10:28 +09:00

DSDIRInstructions.td

AMDGPU: Remove LDS-direct(param)-loads and VINTERP ops from gfx1250 support (#145631)

2025-06-24 22:44:35 -07:00

DSInstructions.td

AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)

2025-12-09 23:13:33 +00:00

EvergreenInstructions.td

[AMDGPU] Make rotr illegal (#166558)

2025-12-05 12:39:50 +00:00

EXPInstructions.td

AMDGPU: Remove export and related instructions from gfx1250 support (#145624)

2025-06-24 19:59:26 -07:00

FLATInstructions.td

[AMDGPU] Global and Buffer loads to LDS should not increase lgkmcnt (#179305)

2026-02-05 09:36:00 -08:00

GCNCreateVOPD.cpp

[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)

2026-01-30 15:13:33 +00:00

GCNDPPCombine.cpp

[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)

2026-01-23 00:19:03 -08:00

GCNDPPCombine.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

GCNHazardRecognizer.cpp

[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)

2026-01-26 14:16:36 +01:00

GCNHazardRecognizer.h

[AMDGPU] Refactor hazard recognizer for VALU-pipeline hazards. NFCI. (#168801)

2025-12-01 10:59:52 -08:00

GCNILPSched.cpp

…

GCNIterativeScheduler.cpp

[AMDGPU] Iterative scheduling must behave the same with/without debug (#178460)

2026-02-02 09:15:48 -06:00

GCNIterativeScheduler.h

[AMDGPU] Teach iterative schedulers about IGLP (#134953)

2025-04-11 15:34:49 -07:00

GCNMinRegStrategy.cpp

…

GCNNSAReassign.cpp

[llvm] Use conventional enum declarations (NFC) (#166318)

2025-11-04 07:12:53 -08:00

GCNNSAReassign.h

[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager (#125034)

2025-02-18 11:13:31 +05:30

GCNPreRALongBranchReg.cpp

…

GCNPreRALongBranchReg.h

…

GCNPreRAOptimizations.cpp

[AMDGPU] Use subclass query for VGPR_16 RA hinting. NFCI (#177017)

2026-01-20 21:09:36 -08:00

GCNPreRAOptimizations.h

[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)

2025-02-11 11:09:38 +05:30

GCNProcessors.td

[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)

2026-01-26 14:16:36 +01:00

GCNRegPressure.cpp

[AMDGPU] Rematerialize VGPR candidates when SGPR spills results in VGPR Excess (#168079)

2026-01-16 09:08:55 +01:00

GCNRegPressure.h

[AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR (#170335)

2026-01-22 12:22:39 +01:00

GCNRewritePartialRegUses.cpp

[AMDGPU] Simplify GCNRewritePartialRegUses pass. (#135199)

2025-04-11 15:45:24 +02:00

GCNRewritePartialRegUses.h

[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)

2025-02-12 11:21:40 +05:30

GCNSchedStrategy.cpp

[AMDGPU][Scheduler] Fix incorrect region index in EXPENSIVE_CHECKS (#179461)

2026-02-03 17:51:36 +01:00

GCNSchedStrategy.h

Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#177206)

2026-02-02 12:34:16 +01:00

GCNSubtarget.cpp

[NFCI][AMDGPU] Final touch before moving to GET_SUBTARGETINFO_MACRO (#177401)

2026-01-22 17:33:17 +00:00

GCNSubtarget.h

[AMDGPU] Pre-GFX10 does not need added latency for workgroup fences (#177157)

2026-01-27 10:24:05 +09:00

GCNVOPDUtils.cpp

[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)

2026-01-30 15:13:33 +00:00

GCNVOPDUtils.h

[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)

2025-07-10 14:15:01 -07:00

MIMGInstructions.td

[AMDGPU] Set VADDR4 field to NULL for tensor ops for gfx1250 (#165917)

2025-10-31 16:48:20 -07:00

R600.h

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

R600.td

CodeGen: Make all targets override pseudos with pointers (#159881)

2025-11-26 14:57:14 +00:00

R600AsmPrinter.cpp

…

R600AsmPrinter.h

[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel

2025-03-29 11:08:13 -07:00

R600ClauseMergePass.cpp

…

R600ControlFlowFinalizer.cpp

[NFCI][AMDGPU] Use GET_SUBTARGETINFO_MACRO in GCNSubtarget.h and R600Subtarget.h (#177402)

2026-01-25 09:38:42 -05:00

R600Defines.h

…

R600EmitClauseMarkers.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

R600ExpandSpecialInstrs.cpp

[CodeGen] Remove FinalizeMachineBundles pass (#149806)

2025-07-23 11:36:49 +01:00

R600FrameLowering.cpp

…

R600FrameLowering.h

…

R600InstrFormats.td

…

R600InstrInfo.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

R600InstrInfo.h

[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)

2025-02-24 09:55:34 -08:00

R600InstrInfo.td

…

R600Instructions.td

[AMDGPU] Use FPImmLeaf for float constants, fix build_vector patterns (#178018)

2026-01-28 10:51:42 +01:00

R600ISelDAGToDAG.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

R600ISelLowering.cpp

Reapply "R600: Remove softPromoteHalfType (#177420)" (#178013)

2026-01-26 18:49:26 +00:00

R600ISelLowering.h

R600: Really remove softPromoteHalfType (#178040)

2026-01-26 20:46:37 +00:00

R600MachineCFGStructurizer.cpp

Reland "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176277)

2026-01-16 13:05:06 -08:00

R600MachineFunctionInfo.cpp

…

R600MachineFunctionInfo.h

…

R600MachineScheduler.cpp

…

R600MachineScheduler.h

…

R600MCInstLower.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

R600OpenCLImageTypeLoweringPass.cpp

…

R600OptimizeVectorRegisters.cpp

[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)

2026-02-03 14:24:31 +00:00

R600Packetizer.cpp

[TableGen] Add mapping from processor ID to resource index for packetizer (#158182)

2025-09-17 09:12:37 +08:00

R600Processors.td

[NFCI][AMDGPU] Use GET_SUBTARGETINFO_MACRO in GCNSubtarget.h and R600Subtarget.h (#177402)

2026-01-25 09:38:42 -05:00

R600RegisterInfo.cpp

…

R600RegisterInfo.h

…

R600RegisterInfo.td

…

R600Schedule.td

…

R600Subtarget.cpp

…

R600Subtarget.h

[NFCI][AMDGPU] Use GET_SUBTARGETINFO_MACRO in GCNSubtarget.h and R600Subtarget.h (#177402)

2026-01-25 09:38:42 -05:00

R600TargetMachine.cpp

[Codegen][NewPM] Explicitly Nest Passes in CodegenPassBuilder (#169867)

2025-12-16 15:42:28 -08:00

R600TargetMachine.h

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

R600TargetTransformInfo.cpp

[TTI] Add VectorInstrContext for context-aware insert/extract costs. (#175982)

2026-01-27 16:30:29 +00:00

R600TargetTransformInfo.h

[TTI] Add VectorInstrContext for context-aware insert/extract costs. (#175982)

2026-01-27 16:30:29 +00:00

R700Instructions.td

…

SIAnnotateControlFlow.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

SIDefines.h

[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)

2026-01-26 14:16:36 +01:00

SIFixSGPRCopies.cpp

[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)

2026-02-03 14:24:31 +00:00

SIFixSGPRCopies.h

…

SIFixVGPRCopies.cpp

…

SIFixVGPRCopies.h

…

SIFoldOperands.cpp

[AMDGPU] Clear no convergence flag on operand folding. NFCI (#179438)

2026-02-03 10:46:26 -08:00

SIFoldOperands.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIFormMemoryClauses.cpp

[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)

2026-01-23 00:19:03 -08:00

SIFormMemoryClauses.h

[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)

2025-02-17 11:07:17 +05:30

SIFrameLowering.cpp

[AMDGPU] Implement llvm.sponentry (#176357)

2026-02-03 15:02:07 +01:00

SIFrameLowering.h

[CodeGen] Replace (Min,Max)CSFrameIndex with flag on frame object [NFCI] (#170905)

2025-12-06 14:00:55 -08:00

SIInsertHardClauses.cpp

[AMDGPU] Adjust hard clause rules for gfx1250 (#152592)

2025-08-07 14:59:31 -07:00

SIInsertWaitcnts.cpp

[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)

2026-02-05 10:13:51 -06:00

SIInstrFormats.td

CodeGen: Add RegisterClass by HwMode (#158269)

2025-09-19 20:08:51 +09:00

SIInstrInfo.cpp

[AMDGPU] Implement llvm.sponentry (#176357)

2026-02-03 15:02:07 +01:00

SIInstrInfo.h

[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)

2026-01-31 10:46:59 -08:00

SIInstrInfo.td

[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)

2026-02-05 11:51:25 +01:00

SIInstructions.td

[AMDGPU] Implement llvm.sponentry (#176357)

2026-02-03 15:02:07 +01:00

SIISelLowering.cpp

[AMDGPU] Return two MMOs for load-to-lds and store-from-lds intrinsics (#175845)

2026-02-04 12:29:49 -08:00

SIISelLowering.h

[AMDGPU] Implement llvm.sponentry (#176357)

2026-02-03 15:02:07 +01:00

SILateBranchLowering.cpp

[AMDGPU] Teach SILateBranchLowering pass to preserve MachineLoopInfo (#178276)

2026-01-29 22:23:00 +05:30

SILoadStoreOptimizer.cpp

[AMDGPU][SILoadStoreOptimizer] Fix unused variable warning (#177969)

2026-01-26 15:59:34 +00:00

SILoadStoreOptimizer.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerControlFlow.cpp

[AMDGPU] Fix DomTree preservation in SILowerControlFlow when nodes are removed (#176691)

2026-01-25 09:45:44 +05:30

SILowerControlFlow.h

…

SILowerI1Copies.cpp

[NFC][AMDGPU] Declare variables initialized with getDebugLoc as const ref (#174434)

2026-01-05 12:37:47 -06:00

SILowerI1Copies.h

AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)

2025-03-12 12:09:37 +01:00

SILowerSGPRSpills.cpp

CodeGen: Remove TRI arguments from stack load/store hooks (#158240)

2025-11-10 16:24:39 -08:00

SILowerSGPRSpills.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerWWMCopies.cpp

…

SILowerWWMCopies.h

…

SIMachineFunctionInfo.cpp

[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)

2026-02-03 14:24:31 +00:00

SIMachineFunctionInfo.h

[AMDGPU] Remove NoSignedZerosFPMath uses (#178343)

2026-01-30 09:18:40 +08:00

SIMachineScheduler.cpp

[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)

2026-02-03 14:24:31 +00:00

SIMachineScheduler.h

[CodeGen] Use VirtRegOrUnit where appropriate (NFCI) (#167730)

2025-11-13 10:26:58 +00:00

SIMemoryLegalizer.cpp

[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)

2026-01-26 14:16:36 +01:00

SIModeRegister.cpp

[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)

2025-03-04 10:51:03 +05:30

SIModeRegisterDefaults.cpp

IR: Promote "denormal-fp-math" to a first class attribute (#174293)

2026-02-05 13:31:26 +00:00

SIModeRegisterDefaults.h

…

SIOptimizeExecMasking.cpp

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

SIOptimizeExecMasking.h

…

SIOptimizeExecMaskingPreRA.cpp

[AMDGPU] SIOptimizeExecMaskingPreRA: Fix crash on exec copy fold into INLINEASM (#172481)

2025-12-16 17:55:05 +01:00

SIOptimizeExecMaskingPreRA.h

[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)

2025-02-20 17:35:56 +05:30

SIOptimizeVGPRLiveRange.cpp

[LLVM][CodeGen] Remove pass initialization calls from pass constructors (#173061)

2026-01-21 08:44:51 -08:00

SIOptimizeVGPRLiveRange.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIPeepholeSDWA.cpp

Reland "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176277)

2026-01-16 13:05:06 -08:00

SIPeepholeSDWA.h

…

SIPostRABundler.cpp

[AMDGPU] Use MCRegUnit, insert explicit casts to/from unsigned (NFC) (#167889)

2025-11-13 21:39:02 +03:00

SIPostRABundler.h

[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)

2025-02-21 16:05:58 +05:30

SIPreAllocateWWMRegs.cpp

[regalloc][LiveRegMatrix][AMDGPU] Fix LiveInterval dangling pointers in LiveRegMatrix. (#168556)

2026-01-27 16:08:58 +01:00

SIPreAllocateWWMRegs.h

…

SIPreEmitPeephole.cpp

AMDGPU: Fix assert when looking for s_and_b64 + vcc branch pattern (#177031)

2026-01-20 22:23:52 +00:00

SIProgramInfo.cpp

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

SIProgramInfo.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

SIRegisterInfo.cpp

[AMDGPU][SIRegisterInfo] Fix maxoffset calculation in buildSpillLoadStore (#179182)

2026-02-04 16:27:48 +05:30

SIRegisterInfo.h

[RegAlloc] Change the computation of CSRCost (#177226)

2026-02-04 10:08:57 -08:00

SIRegisterInfo.td

[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)

2026-01-20 19:14:59 -05:00

SISchedule.td

AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)

2025-07-21 10:09:42 -07:00

SIShrinkInstructions.cpp

[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)

2026-01-23 00:19:03 -08:00

SIShrinkInstructions.h

…

SIWholeQuadMode.cpp

[AMDGPU] Fix crash in SIWholeQuadMode with debug instructions. (#178282)

2026-01-30 02:11:07 +01:00

SIWholeQuadMode.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SMInstructions.td

[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)

2026-01-26 14:16:36 +01:00

SOPInstructions.td

[AMDGPU] Add SOPK, SOPC and SOPP encoding support for gfx13 (#179179)

2026-02-03 08:27:15 +01:00

VIInstrFormats.td

…

VINTERPInstructions.td

[AMDGPU] Simplify class VINTERPe. NFC. (#175006)

2026-01-08 16:18:42 +00:00

VOP1Instructions.td

[AMDGPU] Implement llvm.fptosi.sat and llvm.fptoui.sat (#174726)

2026-01-30 17:07:40 +09:00

VOP2Instructions.td

[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)

2026-01-20 19:14:59 -05:00

VOP3Instructions.td

[AMDGPU] Further improve AMDGPUSubtargetFeature multiclass (#177077)

2026-01-21 21:05:13 +00:00

VOP3PInstructions.td

[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)

2026-02-05 11:51:25 +01:00

VOPCInstructions.td

[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)

2026-01-14 18:23:27 +00:00

VOPDInstructions.td

[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516)

2025-09-09 10:54:18 -04:00

VOPInstructions.td

[AMDGPU] Add VOP1 support for gfx13 (#177603)

2026-01-27 13:40:10 +01:00