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llvm-project/llvm/lib/Target/AMDGPU
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Kazu Hirata 4eed68357e
[llvm] Use "= default" (NFC) (#166088) 
Identified with modernize-use-equals-default.
2025-11-02 17:16:47 -08:00
..
AsmParser
[AMDGPU][AsmParser]: Use dummy operand for parsing buffer_ SWZ operand. (#165305)
2025-10-27 18:39:59 -07:00
Disassembler
[AMDGPU][MC] Fix disassembler warning for v_cmpx instructions in GFX9 (#163825)
2025-10-17 11:11:58 -07:00
MCA
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
MCTargetDesc
[AMDGPU] Record old VGPR MSBs in the high bits of s_set_vgpr_msb (#165035)
2025-10-31 12:21:59 -07:00
TargetInfo
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
Utils
[AMDGPU][NFC] Remove a duplicate isInlinableLiteralBF16() declaration.
2025-10-16 15:06:38 +01:00
AMDGPU.h
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
AMDGPU.td
[AMDGPU] Add target feature for waits before system scope stores. NFC. (#164993)
2025-10-27 10:31:37 +00:00
AMDGPUAliasAnalysis.cpp
…
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp
…
AMDGPUAnnotateUniformValues.cpp
…
AMDGPUArgumentUsageInfo.cpp
[AMDGPU] Support lowering of cluster related instrinsics (#157978)
2025-09-12 21:11:17 -04:00
AMDGPUArgumentUsageInfo.h
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
AMDGPUAsanInstrumentation.cpp
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
AMDGPUAsanInstrumentation.h
…
AMDGPUAsmPrinter.cpp
Revert "[AMDGPU][gfx1250] Add cu-store subtarget feature (#150588)" (#157639)
2025-09-10 10:20:59 +02:00
AMDGPUAsmPrinter.h
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
AMDGPUAtomicOptimizer.cpp
…
AMDGPUAttributes.def
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
AMDGPUAttributor.cpp
[llvm] Remove "const" in the presence of "constexpr" (NFC) (#166109)
2025-11-02 15:52:44 -08:00
AMDGPUBarrierLatency.cpp
[AMDGPU] Add DAG mutation to improve scheduling before barriers (#142716)
2025-10-21 13:28:52 +09:00
AMDGPUBarrierLatency.h
[AMDGPU] Add DAG mutation to improve scheduling before barriers (#142716)
2025-10-21 13:28:52 +09:00
AMDGPUCallingConv.td
…
AMDGPUCallLowering.cpp
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
AMDGPUCallLowering.h
[AMDGPU] ISel & PEI for whole wave functions (#145858)
2025-07-21 10:39:09 +02:00
AMDGPUCodeGenPrepare.cpp
[AMDGPU] Use reverse iteration in CodeGenPrepare (#145484)
2025-10-10 13:00:40 +02:00
AMDGPUCombine.td
[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)
2025-10-24 17:25:00 +02:00
AMDGPUCombinerHelper.cpp
[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)
2025-08-20 17:32:29 +02:00
AMDGPUCombinerHelper.h
[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)
2025-08-20 17:32:29 +02:00
AMDGPUCtorDtorLowering.cpp
…
AMDGPUCtorDtorLowering.h
…
AMDGPUExportClustering.cpp
…
AMDGPUExportClustering.h
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AMDGPUExportKernelRuntimeHandles.cpp
…
AMDGPUExportKernelRuntimeHandles.h
…
AMDGPUFeatures.td
[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)
2025-08-14 12:52:00 -07:00
AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
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AMDGPUGISel.td
AMDGPU: Use srcvalue and delete Ignore complex pattern (#161359)
2025-09-30 16:18:51 +02:00
AMDGPUGlobalISelDivergenceLowering.cpp
…
AMDGPUGlobalISelUtils.cpp
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
AMDGPUGlobalISelUtils.h
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
AMDGPUHSAMetadataStreamer.cpp
[AMDGPU] Add the support for .cluster_dims code object metadata (#158721)
2025-09-15 16:13:07 -04:00
AMDGPUHSAMetadataStreamer.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
AMDGPUIGroupLP.cpp
[AMDGPU] Do not put memory instructions in *ALU SchedGroups (#162560)
2025-10-13 11:49:32 -07:00
AMDGPUIGroupLP.h
…
AMDGPUImageIntrinsicOptimizer.cpp
…
AMDGPUInsertDelayAlu.cpp
AMDGPU: Treat WMMA XDL ops as TRANS in S_DELAY_ALU insertion for gfx1250 (#149208)
2025-07-16 17:07:48 -07:00
AMDGPUInstCombineIntrinsic.cpp
[AMDGPU] gfx1250 v_wmma_scale[16]_f32_16x16x128_f8f6f4 codegen (#152036)
2025-08-04 19:16:34 -07:00
AMDGPUInstrInfo.cpp
AMDGPU: Remove AMDGPUInstrInfo class (#144984)
2025-06-20 18:26:56 +09:00
AMDGPUInstrInfo.h
[AMDGPU] Support image atomic no return instructions (#150742)
2025-10-29 10:42:15 +08:00
AMDGPUInstrInfo.td
[AMDGPU] Tail call support for whole wave functions (#145860)
2025-09-04 10:34:43 +02:00
AMDGPUInstructions.td
[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)
2025-09-04 09:19:25 +00:00
AMDGPUInstructionSelector.cpp
[AMDGPU][GlobalISel] Clean up selectCOPY_SCC_VCC function (#165797)
2025-10-31 13:17:44 -07:00
AMDGPUInstructionSelector.h
AMDGPU: Use srcvalue and delete Ignore complex pattern (#161359)
2025-09-30 16:18:51 +02:00
AMDGPUISelDAGToDAG.cpp
[AMDGPU] Remove setcc by using add/sub carryout (#155255)
2025-10-08 22:19:05 -05:00
AMDGPUISelDAGToDAG.h
AMDGPU: Use srcvalue and delete Ignore complex pattern (#161359)
2025-09-30 16:18:51 +02:00
AMDGPUISelLowering.cpp
[AMDGPU][NFC] Cleanly make 32-bit abs legal (#164837)
2025-10-23 15:21:30 -05:00
AMDGPUISelLowering.h
Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)
2025-09-23 17:36:02 +01:00
AMDGPULaneMaskUtils.h
[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)
2025-09-16 03:22:14 +00:00
AMDGPULateCodeGenPrepare.cpp
[AMDGPU] LRO: allow same-BB non-lookthrough users for PHI (#160909)
2025-09-30 00:57:07 +09:00
AMDGPULegalizerInfo.cpp
[AMDGPU][GlobalISel] Lower G_FMINIMUM and G_FMAXIMUM (#151122)
2025-10-24 14:48:27 +02:00
AMDGPULegalizerInfo.h
[AMDGPU] Support lowering of cluster related instrinsics (#157978)
2025-09-12 21:11:17 -04:00
AMDGPULibCalls.cpp
[AMDGPU] Remove UnsafeFPMath uses (#151079)
2025-07-31 17:36:57 +08:00
AMDGPULibFunc.cpp
…
AMDGPULibFunc.h
…
AMDGPULowerBufferFatPointers.cpp
[AMDGPU][LowerBufferFatPointers] Erase dead ptr(7) intrinsics (#160798)
2025-09-29 10:46:45 -05:00
AMDGPULowerIntrinsics.cpp
[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)
2025-09-16 14:49:48 -07:00
AMDGPULowerKernelArguments.cpp
…
AMDGPULowerKernelAttributes.cpp
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AMDGPULowerModuleLDSPass.cpp
[NFC][AMDGPU] Replace size & set_is_subset by operator== (#161813)
2025-10-03 12:44:51 +02:00
AMDGPULowerVGPREncoding.cpp
[AMDGPU] Record old VGPR MSBs in the high bits of s_set_vgpr_msb (#165035)
2025-10-31 12:21:59 -07:00
AMDGPULowerVGPREncoding.h
[AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (#156971)
2025-09-05 00:07:47 -07:00
AMDGPUMachineFunction.cpp
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUMachineFunction.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUMachineModuleInfo.cpp
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
AMDGPUMachineModuleInfo.h
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
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AMDGPUMarkLastScratchLoad.cpp
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AMDGPUMCInstLower.cpp
[AMDGPU] Record old VGPR MSBs in the high bits of s_set_vgpr_msb (#165035)
2025-10-31 12:21:59 -07:00
AMDGPUMCInstLower.h
[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)
2025-09-24 11:27:26 -04:00
AMDGPUMCResourceInfo.cpp
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUMCResourceInfo.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUMemoryUtils.cpp
[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)
2025-09-16 14:49:48 -07:00
AMDGPUMemoryUtils.h
…
AMDGPUMIRFormatter.cpp
…
AMDGPUMIRFormatter.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
AMDGPUPassRegistry.def
[AMDGPU] make AMDGPUUniformIntrinsicCombine a function pass (#165265)
2025-10-29 11:56:43 +05:30
AMDGPUPerfHintAnalysis.cpp
[llvm] Remove unused includes of SmallSet.h (NFC) (#154893)
2025-08-22 10:33:46 -07:00
AMDGPUPerfHintAnalysis.h
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
AMDGPUPostLegalizerCombiner.cpp
…
AMDGPUPredicateControl.td
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AMDGPUPreLegalizerCombiner.cpp
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AMDGPUPreloadKernArgProlog.cpp
[AMDGPU] Enable kernarg preload on gfx1250 (#153686)
2025-08-14 16:29:53 -07:00
AMDGPUPreloadKernArgProlog.h
…
AMDGPUPreloadKernelArguments.cpp
[AMDGPU] Fix uncaught changes made by AMDGPUPreloadKernelArgumentsPass (#154645)
2025-08-20 16:23:23 -07:00
AMDGPUPrepareAGPRAlloc.cpp
AMDGPU: Start using AV_MOV_B64_IMM_PSEUDO (#154500)
2025-08-22 13:59:36 +09:00
AMDGPUPrepareAGPRAlloc.h
AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)
2025-07-18 17:15:38 +09:00
AMDGPUPrintfRuntimeBinding.cpp
[AMDGPU] Support 'F' and 'A' conversion specifiers with ocl printf (#148784)
2025-07-15 13:24:08 +05:30
AMDGPUPromoteAlloca.cpp
[AMDGPUPromoteAlloca][NFC] Avoid unnecessary APInt/int64_t conversions (#157864)
2025-09-12 09:51:55 +02:00
AMDGPUPromoteKernelArguments.cpp
…
AMDGPUPTNote.h
…
AMDGPURegBankCombiner.cpp
AMDGPU/GlobalISel: Import D16 load patterns and add combines for them (#153178)
2025-09-11 12:02:50 +02:00
AMDGPURegBankLegalize.cpp
[AMDGPU][GlobalISel] Add register bank legalization for G_FADD (#163407)
2025-10-31 16:45:40 +05:30
AMDGPURegBankLegalizeHelper.cpp
[AMDGPU][GlobalISel] Add register bank legalization for G_FADD (#163407)
2025-10-31 16:45:40 +05:30
AMDGPURegBankLegalizeHelper.h
[AMDGPU][GlobalISel] Add register bank legalization for G_FADD (#163407)
2025-10-31 16:45:40 +05:30
AMDGPURegBankLegalizeRules.cpp
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
AMDGPURegBankLegalizeRules.h
[AMDGPU][GlobalISel] Add register bank legalization for G_FADD (#163407)
2025-10-31 16:45:40 +05:30
AMDGPURegBankSelect.cpp
…
AMDGPURegisterBankInfo.cpp
[AMDGPU] Add intrinsics for v_[pk]_add_{min|max}_* instructions (#164731)
2025-10-22 17:46:33 -07:00
AMDGPURegisterBankInfo.h
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AMDGPURegisterBanks.td
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AMDGPURemoveIncompatibleFunctions.cpp
[AMDGPU] Remove wave64 functions (#153690)
2025-08-14 15:54:33 -07:00
AMDGPURemoveIncompatibleFunctions.h
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AMDGPUReserveWWMRegs.cpp
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AMDGPUReserveWWMRegs.h
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AMDGPUResourceUsageAnalysis.cpp
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUResourceUsageAnalysis.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPURewriteAGPRCopyMFMA.cpp
[AMDGPU] Make sort ordering in AMDGPURewriteAGPRCopyMFMAImpl::eliminateSpillsOfReassignedVGPRs() strict weak. (#162493)
2025-10-08 13:05:08 -04:00
AMDGPURewriteOutArguments.cpp
…
AMDGPURewriteUndefForPHI.cpp
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AMDGPUSearchableTables.td
[AMDGPU] Mark cluster_workgroup_id_* intrinsics always uniform (#159439)
2025-09-17 14:07:52 -07:00
AMDGPUSelectionDAGInfo.cpp
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AMDGPUSelectionDAGInfo.h
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AMDGPUSetWavePriority.cpp
[llvm] Replace SmallSet with SmallPtrSet (NFC) (#154068)
2025-08-18 07:01:29 -07:00
AMDGPUSplitModule.cpp
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AMDGPUSplitModule.h
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AMDGPUSubtarget.cpp
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
AMDGPUSubtarget.h
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
AMDGPUSwLowerLDS.cpp
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AMDGPUTargetMachine.cpp
[ADT] Prepare to deprecate variadic StringSwitch::Cases. NFC. (#166020)
2025-11-02 00:12:33 +00:00
AMDGPUTargetMachine.h
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
AMDGPUTargetObjectFile.cpp
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AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[AMDGPU] Fix vector legalization for bf16 valu ops (#158439)
2025-09-25 10:07:11 +01:00
AMDGPUTargetTransformInfo.h
[AMDGPU] Enable vectorization of i8 values. (#134934)
2025-06-26 19:15:31 -04:00
AMDGPUUniformIntrinsicCombine.cpp
[AMDGPU] insert eof white space (#165673)
2025-10-30 15:05:25 +05:30
AMDGPUUnifyDivergentExitNodes.cpp
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AMDGPUUnifyDivergentExitNodes.h
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AMDGPUWaitSGPRHazards.cpp
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
AMDGPUWaitSGPRHazards.h
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AMDKernelCodeT.h
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BUFInstructions.td
AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)
2025-10-08 11:19:54 +09:00
CaymanInstructions.td
…
CMakeLists.txt
[AMDGPU] Add DAG mutation to improve scheduling before barriers (#142716)
2025-10-21 13:28:52 +09:00
DSDIRInstructions.td
AMDGPU: Remove LDS-direct(param)-loads and VINTERP ops from gfx1250 support (#145631)
2025-06-24 22:44:35 -07:00
DSInstructions.td
[AMDGPU] Add additional aliases for load transpose instructions (#163900)
2025-10-17 10:01:02 -07:00
EvergreenInstructions.td
Remove an unused field (follow up to cc5e8967)
2025-08-30 07:55:56 +03:00
EXPInstructions.td
AMDGPU: Remove export and related instructions from gfx1250 support (#145624)
2025-06-24 19:59:26 -07:00
FLATInstructions.td
[AMDGPU] Add additional aliases for load transpose instructions (#163900)
2025-10-17 10:01:02 -07:00
GCNCreateVOPD.cpp
[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)
2025-07-10 14:15:01 -07:00
GCNDPPCombine.cpp
AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)
2025-10-08 11:19:54 +09:00
GCNDPPCombine.h
…
GCNHazardRecognizer.cpp
[AMDGPU] Rework GFX11 VALU Mask Write Hazard (#138663)
2025-10-28 16:09:28 +09:00
GCNHazardRecognizer.h
[AMDGPU] w/a for s_setreg_b32 gfx1250 hazard with MODE register (#153879)
2025-08-15 16:08:13 -07:00
GCNILPSched.cpp
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GCNIterativeScheduler.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
GCNIterativeScheduler.h
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GCNMinRegStrategy.cpp
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GCNNSAReassign.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
GCNNSAReassign.h
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GCNPreRALongBranchReg.cpp
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GCNPreRALongBranchReg.h
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GCNPreRAOptimizations.cpp
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GCNPreRAOptimizations.h
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GCNProcessors.td
[AMDGPU] Add gfx1251 subtarget (#159430)
2025-09-17 13:02:02 -07:00
GCNRegPressure.cpp
[AMDGPU] Add register usage debug printing the point of maximum register pressure. (#161850)
2025-10-13 16:17:11 +02:00
GCNRegPressure.h
[AMDGPU] Use std::array in GCNRegPressure (NFC) (#164117)
2025-10-18 15:41:40 -07:00
GCNRewritePartialRegUses.cpp
…
GCNRewritePartialRegUses.h
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GCNSchedStrategy.cpp
[AMDGPU] Examine instructions in pending queues during scheduling (#147653)
2025-10-16 08:46:29 -07:00
GCNSchedStrategy.h
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
GCNSubtarget.cpp
AMDGPU: Remove triple field from subtarget (#164208)
2025-10-20 06:58:16 +00:00
GCNSubtarget.h
[AMDGPU] Add target feature for waits before system scope stores. NFC. (#164993)
2025-10-27 10:31:37 +00:00
GCNVOPDUtils.cpp
[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)
2025-07-10 14:15:01 -07:00
GCNVOPDUtils.h
[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)
2025-07-10 14:15:01 -07:00
InstCombineTables.td
…
MIMGInstructions.td
[AMDGPU] Set VADDR4 field to NULL for tensor ops for gfx1250 (#165917)
2025-10-31 16:48:20 -07:00
R600.h
…
R600.td
…
R600AsmPrinter.cpp
…
R600AsmPrinter.h
…
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
…
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
[CodeGen] Remove FinalizeMachineBundles pass (#149806)
2025-07-23 11:36:49 +01:00
R600FrameLowering.cpp
…
R600FrameLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (#157337)
2025-09-08 12:12:19 +09:00
R600InstrInfo.h
…
R600InstrInfo.td
…
R600Instructions.td
[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)
2025-08-30 04:44:20 +00:00
R600ISelDAGToDAG.cpp
…
R600ISelLowering.cpp
[AMDGPU][NFC] Cleanly make 32-bit abs legal (#164837)
2025-10-23 15:21:30 -05:00
R600ISelLowering.h
…
R600MachineCFGStructurizer.cpp
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R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600MCInstLower.cpp
[AMDGPU] Fix compilation errors.
2025-08-22 10:30:43 +01:00
R600OpenCLImageTypeLoweringPass.cpp
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
[TableGen] Add mapping from processor ID to resource index for packetizer (#158182)
2025-09-17 09:12:37 +08:00
R600Processors.td
…
R600RegisterInfo.cpp
…
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
…
R600Subtarget.h
…
R600TargetMachine.cpp
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
R600TargetMachine.h
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
R600TargetTransformInfo.cpp
…
R600TargetTransformInfo.h
…
R700Instructions.td
…
SIAnnotateControlFlow.cpp
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
SIDefines.h
[AMDGPU] Enable volatile and non-temporal for loads to LDS (#153244)
2025-10-20 12:42:22 -05:00
SIFixSGPRCopies.cpp
[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)
2025-09-16 03:22:14 +00:00
SIFixSGPRCopies.h
…
SIFixVGPRCopies.cpp
…
SIFixVGPRCopies.h
…
SIFoldOperands.cpp
AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)
2025-10-08 11:19:54 +09:00
SIFoldOperands.h
…
SIFormMemoryClauses.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
SIFormMemoryClauses.h
…
SIFrameLowering.cpp
[AMDGPU] Fix iterator invalidation during frame lowering (#163952)
2025-10-20 13:17:56 +02:00
SIFrameLowering.h
…
SIInsertHardClauses.cpp
[AMDGPU] Adjust hard clause rules for gfx1250 (#152592)
2025-08-07 14:59:31 -07:00
SIInsertWaitcnts.cpp
[AMDGPU] Fix Xcnt handling between blocks (#165201)
2025-11-01 16:48:48 +05:30
SIInstrFormats.td
CodeGen: Add RegisterClass by HwMode (#158269)
2025-09-19 20:08:51 +09:00
SIInstrInfo.cpp
[llvm] Remove "const" in the presence of "constexpr" (NFC) (#166109)
2025-11-02 15:52:44 -08:00
SIInstrInfo.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
SIInstrInfo.td
AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)
2025-10-08 11:19:54 +09:00
SIInstructions.td
[AMDGPU] Remove magic constants from V_PK_ADD_F32 pattern. NFC (#164335)
2025-10-20 23:48:50 -07:00
SIISelLowering.cpp
[AMDGPU] Support bfloat comparison for ballot intrinsic (#165495)
2025-10-30 09:44:25 -07:00
SIISelLowering.h
DAG: Remove TargetLowering::checkForPhysRegDependency (#161787)
2025-10-03 15:58:51 +00:00
SILateBranchLowering.cpp
[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)
2025-09-16 03:22:14 +00:00
SILoadStoreOptimizer.cpp
CodeGen: Remove MachineFunction argument from getRegClass (#158188)
2025-09-12 19:22:02 +09:00
SILoadStoreOptimizer.h
…
SILowerControlFlow.cpp
[AMDGPU] SILowerControlFlow: ensure EXEC/SCC interval recompute (#160459)
2025-09-24 18:30:40 +09:00
SILowerControlFlow.h
…
SILowerI1Copies.cpp
…
SILowerI1Copies.h
…
SILowerSGPRSpills.cpp
[MIR] Support save/restore points with independent sets of registers (#119358)
2025-09-23 11:54:52 +03:00
SILowerSGPRSpills.h
…
SILowerWWMCopies.cpp
…
SILowerWWMCopies.h
…
SIMachineFunctionInfo.cpp
AMDGPU: Track minNumAGPRs in MFI instead of mayUseAGPRs (#161996)
2025-10-07 08:48:45 +09:00
SIMachineFunctionInfo.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
SIMachineScheduler.cpp
…
SIMachineScheduler.h
…
SIMemoryLegalizer.cpp
[AMDGPU] Add target feature for waits before system scope stores. NFC. (#164993)
2025-10-27 10:31:37 +00:00
SIModeRegister.cpp
…
SIModeRegisterDefaults.cpp
…
SIModeRegisterDefaults.h
…
SIOptimizeExecMasking.cpp
[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)
2025-09-16 03:22:14 +00:00
SIOptimizeExecMasking.h
…
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)
2025-09-16 03:22:14 +00:00
SIOptimizeExecMaskingPreRA.h
…
SIOptimizeVGPRLiveRange.cpp
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
SIOptimizeVGPRLiveRange.h
…
SIPeepholeSDWA.cpp
AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)
2025-10-08 11:19:54 +09:00
SIPeepholeSDWA.h
…
SIPostRABundler.cpp
[AMDGPU] Avoid bundling a SCHED_BARRIER with memops (#153533)
2025-08-27 17:09:27 -05:00
SIPostRABundler.h
…
SIPreAllocateWWMRegs.cpp
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
SIPreAllocateWWMRegs.h
…
SIPreEmitPeephole.cpp
[AMDGPU][NFC]: Minor Unpacking Fixes. (#163992)
2025-10-17 15:06:10 -07:00
SIProgramInfo.cpp
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
SIProgramInfo.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
SIRegisterInfo.cpp
[AMDGPU] Support true16 spill restore with sram-ecc (#165320)
2025-10-29 12:35:01 -07:00
SIRegisterInfo.h
CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)
2025-09-12 09:18:50 +00:00
SIRegisterInfo.td
AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)
2025-10-08 11:19:54 +09:00
SISchedule.td
AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)
2025-07-21 10:09:42 -07:00
SIShrinkInstructions.cpp
[AMDGPU] Skip debug instructions in SIShrinkInstructions::matchSwap (#160123)
2025-09-23 09:36:09 +01:00
SIShrinkInstructions.h
…
SIWholeQuadMode.cpp
[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)
2025-09-16 03:22:14 +00:00
SIWholeQuadMode.h
…
SMInstructions.td
[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)
2025-08-30 04:44:20 +00:00
SOPInstructions.td
[AMDGPU] Generate s_absdiff_i32 (#164835)
2025-10-27 14:40:56 -05:00
VIInstrFormats.td
…
VINTERPInstructions.td
…
VOP1Instructions.td
[AMDGPU] Fix real and fake true16 v_cvt_f32_bf16 disasm (#161578)
2025-10-01 14:22:56 -07:00
VOP2Instructions.td
AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)
2025-10-08 11:19:54 +09:00
VOP3Instructions.td
[AMDGPU] Change patterns for v_[pk_]add_{min|max} (#164881)
2025-10-23 15:45:15 -07:00
VOP3PInstructions.td
[AMDGPU] Change patterns for v_[pk_]add_{min|max} (#164881)
2025-10-23 15:45:15 -07:00
VOPCInstructions.td
[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516)
2025-09-09 10:54:18 -04:00
VOPDInstructions.td
[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516)
2025-09-09 10:54:18 -04:00
VOPInstructions.td
[AMDGPU][MC] GFX9 - allow op_sel in v_interp_p2_f16 (#150712)
2025-10-06 10:58:13 -07:00