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llvm-project/llvm/lib/Target/RISCV
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Kane Wang 81740e0c97
[RISCV][GlobalISel] Legalize and select G_ATOMICRMW_ADD instruction (#153791) 
This patch adds legalization and instruction selection support for the
`G_ATOMICRMW_ADD` opcode in the RISCV GlobalISel backend. Support for
other opcodes will be added in subsequent PRs.

Co-authored-by: Kane Wang <kanewang95@foxmail.com>
2025-08-25 20:38:41 -07:00
..
AsmParser
[RISCV] Add initial assembler/MC layer support for big-endian (#146534)
2025-08-22 09:21:10 +02:00
Disassembler
[NFC][MC][RISCV] Rearrange decoder functions for RISCV disassembler (#154998)
2025-08-22 11:55:40 -07:00
GISel
[RISCV][GlobalISel] Legalize and select G_ATOMICRMW_ADD instruction (#153791)
2025-08-25 20:38:41 -07:00
MCA
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
MCTargetDesc
MCAssembler: Simplify fragment relaxation
2025-08-23 20:12:57 -07:00
TargetInfo
[RISCV] Add initial assembler/MC layer support for big-endian (#146534)
2025-08-22 09:21:10 +02:00
CMakeLists.txt
[RISCV][NFC] Split InterleavedAccess related TLI hooks into a separate file (#148040)
2025-07-11 11:04:41 -07:00
RISCV.h
Register assembly printer passes (#138348)
2025-05-06 18:01:17 -07:00
RISCV.td
[RISCV] Implement base scheduling model for andes 45 series processor. (#141008)
2025-06-04 16:11:43 +08:00
RISCVAsmPrinter.cpp
[RISCV] Add initial assembler/MC layer support for big-endian (#146534)
2025-08-22 09:21:10 +02:00
RISCVCallingConv.cpp
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.h
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.td
[RISCV] Support PreserveMost calling convention (#148214)
2025-07-30 16:30:48 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
RISCVCombine.td
…
RISCVConstantPoolValue.cpp
…
RISCVConstantPoolValue.h
…
RISCVDeadRegisterDefinitions.cpp
[RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0,x0 vsetvli. NFC (#141875)
2025-05-29 10:21:38 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[NFC][LLVM][RISCV] Cleanup pass initialization for RISCV (#134279)
2025-04-03 11:28:45 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add nds.bfos and nds.bfoz for the short forward branch optimization. (#145836)
2025-06-27 10:54:41 +08:00
RISCVFeatures.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVFoldMemOffset.cpp
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
2025-04-22 19:24:29 -07:00
RISCVFrameLowering.cpp
[llvm] Use a range-based for loop instead of {std,llvm}::for_each (NFC) (#150841)
2025-07-27 10:43:52 -07:00
RISCVFrameLowering.h
[RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531)
2025-07-15 08:09:18 -07:00
RISCVGatherScatterLowering.cpp
[RISCV] Create disjoint or in RISCVGatherScatterLowering (#151981)
2025-08-05 12:19:10 +08:00
RISCVGISel.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVIndirectBranchTracking.cpp
[RISCV] Make RISCVIndirectBranchTracking visible in debug output (#141623)
2025-05-28 14:56:44 +08:00
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Don't increase vslide or splat vl if +vl-dependent-latency is present (#147089)
2025-07-09 16:25:22 +08:00
RISCVInsertWriteVXRM.cpp
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVInstrFormats.td
[Target] Remove SoftFail field on targets that don't use it (NFC) (#154659)
2025-08-21 05:21:42 +03:00
RISCVInstrFormatsC.td
[Target] Remove SoftFail field on targets that don't use it (NFC) (#154659)
2025-08-21 05:21:42 +03:00
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfo.cpp
[RISCV] Optimize the spill/reload of segment registers (#153184)
2025-08-21 16:38:53 +08:00
RISCVInstrInfo.h
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVInstrInfo.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoA.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoC.td
[RISCV] Accept c.slli/c.srli/c.srli with a 0 immediate as hints. (#150689)
2025-07-26 00:05:33 -07:00
RISCVInstrInfoD.td
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
RISCVInstrInfoF.td
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
RISCVInstrInfoM.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoP.td
[RISCV] Correct the OperandType for simm8_unsigned and simm10_unsigned. (#154667)
2025-08-21 12:01:07 -07:00
RISCVInstrInfoQ.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVInstrInfoSFB.td
[RISCV] Fix the operand types for shift instructions in RISCVInstrInfoSFB.td. NFC
2025-03-30 22:38:26 -07:00
RISCVInstrInfoV.td
[RISCV] Rename VALUrVV/VALUrVX/VALUrVF tablegen clases. NFC (#154989)
2025-08-22 16:36:11 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove unused vector pseudo class. NFC (#151327)
2025-07-31 10:14:36 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Use (i64 GPR:$rs1) instead of i64:$rs1 in isel patterns.
2025-08-01 09:44:09 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Use (i64 GPR:$rs1) instead of i64:$rs1 in isel patterns.
2025-08-01 09:44:09 -07:00
RISCVInstrInfoXAndes.td
[RISCV] Remove non-existent operand of nds.vfwcvt/nds.vfncvt instructions (#153865)
2025-08-16 00:46:19 +03:00
RISCVInstrInfoXCV.td
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVInstrInfoXMips.td
[RISCV] Rename MIPS_PREFETCH->MIPS_PREF. NFC (#154062)
2025-08-18 07:38:10 -07:00
RISCVInstrInfoXqccmp.td
[RISCV] Prefer RegList over Rlist in assembler. NFC
2025-04-04 09:37:52 -07:00
RISCVInstrInfoXqci.td
[RISCV] Add Tied operands to insert instructions in Qualcomm uC extension Xqcibm (#151339)
2025-08-05 15:02:19 +05:30
RISCVInstrInfoXRivos.td
[RISCV] Add TSFlag for reading past VL behaviour. NFCI (#149704)
2025-08-15 01:19:03 +00:00
RISCVInstrInfoXSf.td
[RISCV] Add TSFlag for reading past VL behaviour. NFCI (#149704)
2025-08-15 01:19:03 +00:00
RISCVInstrInfoXSfmm.td
[RISCV] Add TSFlag for reading past VL behaviour. NFCI (#149704)
2025-08-15 01:19:03 +00:00
RISCVInstrInfoXSpacemiT.td
[RISCV] Fold argstr into class for XSMTVDot instructions. NFC.
2025-08-21 13:12:46 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Use (i64 GPR:$rs1) instead of i64:$rs1 in isel patterns.
2025-08-01 09:44:09 -07:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
…
RISCVInstrInfoZa.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoZalasr.td
[TableGen][SelectionDAG][GISel][RISCV] Support IsNonExtLoad for IsAtomic PatFrags. (#137401)
2025-04-25 15:45:43 -07:00
RISCVInstrInfoZb.td
[RISCV] Add missing 'OrP' to comment in RISCVInstrInfoZb.td. NFC
2025-08-20 15:27:03 -07:00
RISCVInstrInfoZc.td
[RISCV] Remove extra operands from Zcb compression patterns. NFC (#150541)
2025-07-24 18:03:30 -07:00
RISCVInstrInfoZclsd.td
[RISCV] Reuse existing tablegen classes for Zilsd/Zclsd. NFC (#134946)
2025-04-08 17:53:39 -07:00
RISCVInstrInfoZcmop.td
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVInstrInfoZfa.td
[RISCV] Fix schedule info for FMVP_D_X. (#140766)
2025-05-22 08:39:57 -07:00
RISCVInstrInfoZfbfmin.td
…
RISCVInstrInfoZfh.td
[NFC][RISCV] Remove extra space in RISCVInstrInfoZfh.td
2025-05-13 13:53:38 +08:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZilsd.td
[RISCV] Lower i64 load/stores to ld/sd with Zilsd. (#139808)
2025-05-14 09:54:07 -07:00
RISCVInstrInfoZimop.td
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVInstrInfoZk.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZvfbf.td
…
RISCVInstrInfoZvk.td
[RISCV] Remove duplicate vsha2ch/vsha2cl/vsha2ms i32 patterns. NFC (#151835)
2025-08-02 21:53:58 -07:00
RISCVInstrInfoZvqdotq.td
[RISCV] Fix schedule info for Zqvdotq (#142717)
2025-06-05 12:22:43 +08:00
RISCVInstrPredicates.td
[RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions (#145147)
2025-07-03 12:47:53 +08:00
RISCVInterleavedAccess.cpp
[IA][RISCV] Recognize deinterleaved loads that could lower to strided segmented loads (#151612)
2025-08-12 14:08:18 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Generate QC_INSB/QC_INSBI instructions from OR of AND Imm (#154023)
2025-08-19 11:14:14 +05:30
RISCVISelDAGToDAG.h
[RISCV] Generate QC_INSB/QC_INSBI instructions from OR of AND Imm (#154023)
2025-08-19 11:14:14 +05:30
RISCVISelLowering.cpp
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVISelLowering.h
[IA][RISCV] Recognize deinterleaved loads that could lower to strided segmented loads (#151612)
2025-08-12 14:08:18 -07:00
RISCVLandingPadSetup.cpp
…
RISCVLateBranchOpt.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVLoadStoreOptimizer.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVMachineFunctionInfo.cpp
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMachineFunctionInfo.h
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMacroFusion.td
[RISCV] add more generic macrofusions (#151140)
2025-08-06 14:46:34 -04:00
RISCVMakeCompressible.cpp
[RISCV][NFC] Remove hasStdExtCOrZca (#145139)
2025-06-23 10:49:47 -07:00
RISCVMergeBaseOffset.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVMoveMerger.cpp
[RISCV] Minor refactor of RISCVMoveMerge::mergePairedInsns. (#154467)
2025-08-20 09:07:58 -07:00
RISCVOptWInstrs.cpp
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
RISCVPfmCounters.td
…
RISCVPostRAExpandPseudoInsts.cpp
…
RISCVProcessors.td
[RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (#151706)
2025-08-18 18:03:17 +08:00
RISCVProfiles.td
[RISCV][NFC] Add Zicsr to profiles explicitly (#136134)
2025-04-18 10:59:32 +08:00
RISCVPushPopOptimizer.cpp
[RISCV] Simplify how we find combinable cm.pop+ret. (#130204)
2025-03-06 21:55:47 -08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVRegisterInfo.cpp
[RISCV] Mark More Fatal Errors as Usage/Internal (#154876)
2025-08-22 11:57:17 -07:00
RISCVRegisterInfo.h
[RISCV] Optimize the spill/reload of segment registers (#153184)
2025-08-21 16:38:53 +08:00
RISCVRegisterInfo.td
[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructions. (#150710)
2025-07-25 20:55:15 -07:00
RISCVSchedAndes45.td
[RISCV] Fix typo in comment Interger->Integer. NFC
2025-08-13 11:19:49 -07:00
RISCVSchedGenericOOO.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedMIPSP8700.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedRocket.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFive7.td
[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)
2025-07-09 09:38:44 -07:00
RISCVSchedSiFiveP400.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP500.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP600.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP800.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSpacemitX60.td
[RISCV] Update SpacemiT-X60 vector fixed-point arithmetic latencies (#150517)
2025-08-08 11:57:35 -03:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedTTAscalonD8.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedule.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVScheduleV.td
[RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicates.td (#137938)
2025-05-12 12:05:50 +08:00
RISCVScheduleXSf.td
[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)
2025-07-09 09:38:44 -07:00
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
…
RISCVSchedXiangShanNanHu.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSelectionDAGInfo.cpp
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555)
2025-08-04 12:51:14 +05:30
RISCVSelectionDAGInfo.h
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555)
2025-08-04 12:51:14 +05:30
RISCVSubtarget.cpp
[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy (#149297)
2025-07-22 15:55:12 +08:00
RISCVSubtarget.h
[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy (#149297)
2025-07-22 15:55:12 +08:00
RISCVSystemOperands.td
[RISCV] Sort RISCVSystemOperands to match the RISC-V Privilege Specification. (#140967)
2025-05-22 08:46:48 -07:00
RISCVTargetMachine.cpp
[RISCV] Add initial assembler/MC layer support for big-endian (#146534)
2025-08-22 09:21:10 +02:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetObjectFile.h
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetTransformInfo.cpp
[LV][TTI] Calculate cost of extracting last index in a scalable vector (#144086)
2025-08-19 09:31:37 +01:00
RISCVTargetTransformInfo.h
[RISCV] Mark Sub/AddChainWithSubs as legal reduction types (#154753)
2025-08-21 21:43:48 +08:00
RISCVVectorMaskDAGMutation.cpp
Reland "[RISCV] AddEdge between mask producer and user of V0 (#146855)" (#148566)
2025-07-18 10:56:07 +08:00
RISCVVectorPeephole.cpp
[RISCV] Fold vmv.v.v into vmerge (#151341)
2025-07-31 10:15:12 +08:00
RISCVVLOptimizer.cpp
[RISCV] Move volatile check to isCandidate in VL optimizer. NFC (#154685)
2025-08-21 16:37:10 +08:00
RISCVVMV0Elimination.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVZacasABIFix.cpp
…