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mandelbrot? fractal

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shylie 2024-10-06 00:18:41 -04:00
parent f62fd1428c
commit d9b7fd7aa4
18 changed files with 426 additions and 53 deletions
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2
ice/constraints.sdc
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@ -1 +1 @@
create_clock -period 20.8333333 [get_ports {clk}] create_clock -period 125 [get_ports {clk}]

41
ice/coords.sv Normal file
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@ -0,0 +1,41 @@
module coords
#(
parameter WIDTH = 128,
parameter HEIGHT = 128,
parameter POS_COUNT = 4,
localparam WIDTH_BITS = $clog2(WIDTH),
localparam HEIGHT_BITS = $clog2(HEIGHT)
)(
input wire clk,
input wire rst,
output reg [WIDTH_BITS-1:0] x[POS_COUNT],
output reg [WIDTH_BITS-1:0] y[POS_COUNT],
output wire finished
);
reg [POS_COUNT-1:0] finished_r;
always_ff @(posedge clk) begin
integer i;
if (rst) begin
for (i = 0; i < POS_COUNT; i = i + 1) begin
x[i] <= WIDTH_BITS'(i);
y[i] <= 0;
end
finished_r <= '1;
end else begin
for (i = 0; i < POS_COUNT; i = i + 1) begin
x[i] <= WIDTH_BITS'((32'(x[i]) + POS_COUNT) % WIDTH);
if (x[i] > WIDTH_BITS'((32'(x[i]) + POS_COUNT) % WIDTH)) begin
y[i] <= y[i] + 1;
if (y[i] > HEIGHT_BITS'((32'(y[i]) + 1) % HEIGHT)) begin
finished_r[i] <= 0;
end
end
end
end
end
assign finished = finished_r == 0;
endmodule

2
ice/mandelbrot/.ng_run_manager.ini
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@ -1,6 +1,6 @@
[Runmanager] [Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x3\0\0\0\0\0\0\0\0\0\x14\0\0\x1\xca\0\0\0\xb9\0\0\0\0\0\0\0\x14\0\0\x1\xca\0\0\0\xb9\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x14\0\0\x1\xca\0\0\0\xb9) Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x3\0\0\0\0\0\0\0\0\0\x14\0\0\x1\xca\0\0\0\xb9\0\0\0\0\0\0\0\x14\0\0\x1\xca\0\0\0\xb9\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x14\0\0\x1\xca\0\0\0\xb9)
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x15\0\xf0\x1f\0\0\0\t\0\0\0\f\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x10\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\x5\xf\0\0\0\x15\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x84\0\0\0\0\0\0\0\x15\0\0\0\xc3\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\x3\xe8\0\0\0\0\x64) headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x15\0\xf0\x1f\0\0\0\t\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\f\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\0\x10\0\0\0\x64\0\0\x5\xf\0\0\0\x15\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x84\0\0\0\0\0\0\0\x15\0\0\0\xc3\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\x3\xe8\0\0\0\0\x64)
[impl_1%3CStrategy1%3E] [impl_1%3CStrategy1%3E]
isChecked=false isChecked=false

15
ice/mandelbrot/.recovery
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@ -2,12 +2,21 @@
<RadiantProject version="4.2" radiant="2024.1.0.34.2" title="mandelbrot" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" family_int="ice40tp" device_int="itpa08" package_int="SG48" operation_int="IND" speed_int="6" default_implementation="impl_1"> <RadiantProject version="4.2" radiant="2024.1.0.34.2" title="mandelbrot" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" family_int="ice40tp" device_int="itpa08" package_int="SG48" operation_int="IND" speed_int="6" default_implementation="impl_1">
<Options/> <Options/>
<Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1"> <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="top"/> <Options def_top="top" top="top"/>
<Source name="source/impl_1/top.sv" type="Verilog" type_short="Verilog"> <Source name="source/impl_1/top.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/> <Options VerilogStandard="System Verilog" top_module="top"/>
</Source> </Source>
<Source name="../ram.sv" type="Verilog" type_short="Verilog"> <Source name="../ram.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog" top_module="RAM"/> <Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../coords.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="source/impl_1/renderer.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="source/impl_1/multiplier.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source> </Source>
<Source name="../constraints.pdc" type="Physical Constraints File" type_short="PDC"> <Source name="../constraints.pdc" type="Physical Constraints File" type_short="PDC">
<Options/> <Options/>

11
ice/mandelbrot/mandelbrot.rdf
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@ -2,13 +2,22 @@
<RadiantProject version="4.2" radiant="2024.1.0.34.2" title="mandelbrot" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" family_int="ice40tp" device_int="itpa08" package_int="SG48" operation_int="IND" speed_int="6" default_implementation="impl_1"> <RadiantProject version="4.2" radiant="2024.1.0.34.2" title="mandelbrot" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" family_int="ice40tp" device_int="itpa08" package_int="SG48" operation_int="IND" speed_int="6" default_implementation="impl_1">
<Options/> <Options/>
<Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1"> <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1">
<Options/> <Options def_top="renderer" top="top"/>
<Source name="source/impl_1/top.sv" type="Verilog" type_short="Verilog"> <Source name="source/impl_1/top.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog" top_module="top"/> <Options VerilogStandard="System Verilog" top_module="top"/>
</Source> </Source>
<Source name="../ram.sv" type="Verilog" type_short="Verilog"> <Source name="../ram.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/> <Options VerilogStandard="System Verilog"/>
</Source> </Source>
<Source name="../coords.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="source/impl_1/renderer.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="source/impl_1/multiplier.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../constraints.pdc" type="Physical Constraints File" type_short="PDC"> <Source name="../constraints.pdc" type="Physical Constraints File" type_short="PDC">
<Options/> <Options/>
</Source> </Source>

100
ice/mandelbrot/mandelbrot_tcl.html
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@ -178,12 +178,112 @@ prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/ra
<A name="pn241003133906"></A><B><U><big>pn241003133906</big></U></B>
#Start recording tcl command: 10/2/2024 11:19:00
#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run PAR -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/color_converter.sv"
prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/color_converter.sv"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/framebuffer.sv"
prj_run PAR -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Export -impl impl_1
prj_run Synthesis -impl impl_1
#Stop recording: 10/3/2024 13:39:06
<A name="pn241004114221"></A><B><U><big>pn241004114221</big></U></B>
#Start recording tcl command: 10/3/2024 13:54:22
#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/xd.sv"
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Export -impl impl_1
prj_set_impl_opt -impl "impl_1" "top" "top"
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/xd.sv"
prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/framebuffer.sv"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
#Stop recording: 10/4/2024 11:42:21
<A name="pn241004151504"></A><B><U><big>pn241004151504</big></U></B>
#Start recording tcl command: 10/4/2024 13:54:24
#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
prj_run Synthesis -impl impl_1
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/coords.sv"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/source/impl_1/renderer.sv"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/source/impl_1/multiplier.sv"
#Stop recording: 10/4/2024 15:15:04
</PRE></DIV> </PRE></DIV>
<DIV id="toc" class="radiant"><span onmousemove="showTocList()">Contents</span> <DIV id="toc" class="radiant"><span onmousemove="showTocList()">Contents</span>
<UL id="toc_list"> <UL id="toc_list">
<LI><A href=#pn240928081403>pn240928081403</A></LI> <LI><A href=#pn240928081403>pn240928081403</A></LI>
<LI><A href=#pn241002102238>pn241002102238</A></LI> <LI><A href=#pn241002102238>pn241002102238</A></LI>
<LI><A href=#pn241003133906>pn241003133906</A></LI>
<LI><A href=#pn241004114221>pn241004114221</A></LI>
<LI><A href=#pn241004151504>pn241004151504</A></LI>
</UL> </UL>
</DIV> </DIV>

56
ice/mandelbrot/mandelbrot_tcr.dir/pn241003133906.tcr Normal file
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@ -0,0 +1,56 @@
#Start recording tcl command: 10/2/2024 11:19:00
#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run PAR -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/color_converter.sv"
prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/color_converter.sv"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/framebuffer.sv"
prj_run PAR -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Export -impl impl_1
prj_run Synthesis -impl impl_1
#Stop recording: 10/3/2024 13:39:06

20
ice/mandelbrot/mandelbrot_tcr.dir/pn241004114221.tcr Normal file
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@ -0,0 +1,20 @@
#Start recording tcl command: 10/3/2024 13:54:22
#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/xd.sv"
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Export -impl impl_1
prj_set_impl_opt -impl "impl_1" "top" "top"
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/xd.sv"
prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/framebuffer.sv"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
#Stop recording: 10/4/2024 11:42:21

9
ice/mandelbrot/mandelbrot_tcr.dir/pn241004151504.tcr Normal file
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@ -0,0 +1,9 @@
#Start recording tcl command: 10/4/2024 13:54:24
#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
prj_run Synthesis -impl impl_1
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/coords.sv"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/source/impl_1/renderer.sv"
prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/source/impl_1/multiplier.sv"
#Stop recording: 10/4/2024 15:15:04

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ice/mandelbrot/promote.xml
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<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<userSetting name="C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/promote.xml" version="Diamond (64-bit) 2024.1.0.34.2" date="Wed Oct 02 12:34:15 2024" vendor="Lattice Semiconductor Corporation" > <userSetting name="C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/promote.xml" version="Diamond (64-bit) 2024.1.0.34.2" date="Sun Oct 06 00:16:13 2024" vendor="Lattice Semiconductor Corporation" >
</userSetting> </userSetting>

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ice/mandelbrot/source/impl_1/.gitignore vendored Normal file
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obj_dir/

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ice/mandelbrot/source/impl_1/makefile Normal file
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run: build
cd obj_dir && ./Vtop && gtkwave waveform.vcd
build:
verilator --trace --cc top.sv --exe tb_top.cpp -I../../..
make -C obj_dir -f Vtop.mk Vtop

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ice/mandelbrot/source/impl_1/multiplier.sv Normal file
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module multiplier
(
input wire clk,
input wire signed [7:0] a,
input wire signed [7:0] b,
output reg signed [15:0] product
);
reg signed [7:0] a_reg;
reg signed [7:0] b_reg;
wire [15:0] product_out;
always_ff @(posedge clk) begin
a_reg <= a;
b_reg <= b;
product <= product_out;
end
assign product_out = a_reg * b_reg;
endmodule

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ice/mandelbrot/source/impl_1/renderer.sv Normal file
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module renderer
#(
parameter ITERATIONS = 7,
parameter OUTPUT_WIDTH = 3,
localparam ITERATION_WIDTH = $clog2(ITERATIONS + 1),
localparam SHIFT_AMOUNT = ITERATION_WIDTH - OUTPUT_WIDTH
)(
input wire clk,
input wire rst,
input wire start,
input wire signed [7:0] x,
input wire signed [7:0] y,
output reg done,
output reg [OUTPUT_WIDTH-1:0] iters
);
reg signed [7:0] x_reg;
reg signed [7:0] y_reg;
reg signed [7:0] z_real;
reg signed [7:0] z_imag;
reg [ITERATION_WIDTH-1:0] current_iteration;
wire signed [15:0] a_squared_p;
wire signed [15:0] b_squared_p;
wire signed [15:0] ab_p;
wire signed [7:0] a_squared;
wire signed [7:0] b_squared;
wire signed [7:0] ab;
always_ff @(posedge clk) begin
current_iteration <= current_iteration + 1'b1;
done <= 1'b0;
// 128 = 4 << FRACTION_BITS (4)
if (current_iteration == ITERATIONS || a_squared + b_squared >= 32) begin
x_reg <= '0;
y_reg <= '0;
z_real <= '0;
z_imag <= '0;
iters <= current_iteration >> SHIFT_AMOUNT;
current_iteration <= '0;
done <= 1'b1;
end else if (current_iteration == 0) begin
// store c for later
x_reg <= x;
y_reg <= y;
// add c for first iteration.
// no need to include z as it is initially (0, 0)
z_real <= x;
z_imag <= y;
if (!start) begin
current_iteration <= '0;
end
end else begin
z_real <= a_squared + b_squared + x_reg;
z_imag <= (ab << 1'b1) + y_reg;
end
if (rst) begin
x_reg <= 8'h00;
y_reg <= 8'h00;
z_real <= 8'h00;
z_imag <= 8'h00;
current_iteration <= '0;
end
end
multiplier m1(.clk(clk), .a(z_real), .b(z_real), .product(a_squared_p));
multiplier m2(.clk(clk), .a(z_imag), .b(z_imag), .product(b_squared_p));
multiplier m3(.clk(clk), .a(z_real), .b(z_imag), .product(ab_p));
assign a_squared = a_squared_p[11:4];
assign b_squared = b_squared_p[11:4];
assign ab = ab_p[11:4];
endmodule

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ice/mandelbrot/source/impl_1/tb_top.cpp Normal file
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#include <cstdlib>
#include <iostream>
#include <verilated.h>
#include <verilated_vcd_c.h>
#include "Vtop.h"
constexpr vluint64_t MAX_SIM_TIME = 100000;
vluint64_t sim_time = 0;
int main(int argc, char** argv, char** env)
{
Vtop* dut = new Vtop;
Verilated::traceEverOn(true);
VerilatedVcdC* m_trace = new VerilatedVcdC;
dut->trace(m_trace, 5);
m_trace->open("waveform.vcd");
while (sim_time < MAX_SIM_TIME)
{
dut->clk ^= 1;
dut->eval();
m_trace->dump(sim_time);
sim_time++;
}
m_trace->close();
delete m_trace;
delete dut;
return EXIT_SUCCESS;
}

64
ice/mandelbrot/source/impl_1/top.sv
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@ -7,35 +7,44 @@ module top
inout wire [7:0] data inout wire [7:0] data
); );
reg [3:0] clk_div_8_counter;
wire clk_div_8;
reg dir_last; reg dir_last;
reg req_last; reg req_last;
reg req_r; reg req_r;
reg fin_r;
reg [7:0] data_r;
reg [6:0] x;
reg [6:0] y;
reg cntr;
reg [7:0] waddr; reg [7:0] waddr;
reg [7:0] raddr; reg [7:0] raddr;
wire [7:0] command; wire [7:0] command;
RAM command_buffer(.wclk(clk), .rclk(clk), .waddr(waddr), .raddr(raddr), .data_in(data), .write_en(dir && req), .data_out(command)); ram command_buffer(.wclk(clk), .rclk(clk), .waddr(waddr), .raddr(raddr), .data_in(data), .write_en(dir && req), .data_out(command));
wire [6:0] x[4];
wire [6:0] y[4];
coords #(.POS_COUNT(4)) coords_inst(.clk(clk_div_8), .rst(!req_r), .x(x), .y(y), .finished(fin));
wire [2:0] iters[4];
wire [7:0] data_out;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin
renderer r(.clk(clk), .rst(dir), .start(clk_div_8_counter[2:0] >> 1 == i), .x({x[i], 1'b0}), .y({y[i], 1'b0}), .done(), .iters(iters[i]));
end
endgenerate
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
dir_last <= dir; dir_last <= dir;
req_last <= req; req_last <= req;
req_r <= !fin_r && !dir_last; req_r <= !fin && !dir_last;
if (dir) begin if (dir) begin
x <= 0; clk_div_8_counter <= 0;
y <= 0;
fin_r <= 0;
cntr <= 0;
raddr <= 0; raddr <= 0;
if (req && req_last) begin if (req && req_last) begin
@ -43,33 +52,18 @@ always_ff @(posedge clk) begin
end else begin end else begin
waddr <= 0; waddr <= 0;
end end
end else begin
cntr <= !cntr;
if (cntr) begin
data_r <= command;
raddr <= 1 - raddr;
if (x + y == 0) begin
fin_r <= 1;
end end
end else begin
data_r <= ((x + y) >> 1) + 16;
if (x < 127) begin if (!dir && !dir_last) begin
x <= x + 1; clk_div_8_counter <= clk_div_8_counter + 1;
end else begin
x <= 0;
if (y < 127) begin
y <= y + 1;
end else begin
y <= 0;
end
end
end
end end
end end
assign clk_div_8 = clk_div_8_counter[3];
assign data_out = clk_div_8_counter[0] ? 128 : ((8'(iters[clk_div_8_counter[2:1]]) << 4) + 8'd62);
assign req = dir ? 'Z : req_r; assign req = dir ? 'Z : req_r;
assign fin = fin_r; assign data = dir ? 'Z : data_out;
assign data = dir ? 'Z : data_r;
endmodule endmodule

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ice/ram.sv
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module RAM module ram
#( #(
parameter ADDR_WIDTH = 8, parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8

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ice/top.sv
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module top
(
input wire clk,
input wire start,
output wire [7:0] data
);
endmodule