Prasoon Mishra 1cea4a0841

[AMDGPU][NPM] Fix CFG invalidation detection in insertSimulatedTrap (#169290) ...

When SIMULATED_TRAP is at the end of a block with no successors,
insertSimulatedTrap incorrectly returns the original MBB despite adding
HaltLoopBB to the CFG.

EmitInstrWithCustomInserter detects CFG changes by comparing the
returned MBB with the original. When they match, it assumes no
modification occurred and skips MachineLoopInfo invalidation. This
causes stale loop information in subsequent passes, particularly when
using the NPM which relies on accurate invalidation signals.

Fix: Return HaltLoopBB to properly signal the CFG modification.

2025-11-28 13:45:46 +05:30

..

AsmParser

AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)

2025-11-25 18:55:34 +00:00

Disassembler

[AMDGPU] Remove implicit conversions of MCRegister to unsigned. NFC (#167284)

2025-11-11 08:54:27 -08:00

MCA

[Target] Add "override" where appropriate (NFC) (#165083)

2025-10-25 06:23:43 -07:00

MCTargetDesc

AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)

2025-11-25 18:55:34 +00:00

TargetInfo

[llvm] annotate interfaces in llvm/Target for DLL export (#143615)

2025-06-17 13:28:45 -07:00

Utils

[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)

2025-11-25 15:43:18 +00:00

AMDGPU.h

[AMDGPU] Add amdgpu-lower-exec-sync pass to lower named-barrier globals (#165692)

2025-11-17 10:08:40 +05:30

AMDGPU.td

[AMDGPU] Adding instruction specific features (#167809)

2025-11-19 11:06:00 +08:00

AMDGPUAliasAnalysis.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUAliasAnalysis.h

…

AMDGPUAlwaysInlinePass.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPUAnnotateUniformValues.cpp

[AMDGPU] Preserve all analyses if nothing changed (#117994)

2024-11-28 14:33:05 +00:00

AMDGPUArgumentUsageInfo.cpp

[AMDGPU] Support lowering of cluster related instrinsics (#157978)

2025-09-12 21:11:17 -04:00

AMDGPUArgumentUsageInfo.h

[AMDGPU] Use std::variant in ArgDescriptor. (#167992)

2025-11-14 09:54:56 -08:00

AMDGPUAsanInstrumentation.cpp

[IR] Replace alignment argument with attribute on masked intrinsics (#163802)

2025-10-20 08:50:09 +00:00

AMDGPUAsanInstrumentation.h

…

AMDGPUAsmPrinter.cpp

[AMDGPU] update LDS block size for gfx1250 (#167614)

2025-11-17 16:03:47 -08:00

AMDGPUAsmPrinter.h

AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)

2025-08-15 16:33:06 +01:00

AMDGPUAtomicOptimizer.cpp

[IRBuilder] Add new overload for CreateIntrinsic (#131942)

2025-03-31 08:10:34 -07:00

AMDGPUAttributes.def

[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)

2025-09-15 15:04:33 -04:00

AMDGPUAttributor.cpp

AMDGPU: Do not infer implicit inputs for !nocallback intrinsics

2025-11-05 04:53:42 +00:00

AMDGPUBarrierLatency.cpp

[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutation (#168500)

2025-11-19 17:49:14 +09:00

AMDGPUBarrierLatency.h

[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutation (#168500)

2025-11-19 17:49:14 +09:00

AMDGPUCallingConv.td

[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)

2025-03-08 09:28:20 -05:00

AMDGPUCallLowering.cpp

[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)

2025-09-16 15:37:01 -04:00

AMDGPUCallLowering.h

[AMDGPU] ISel & PEI for whole wave functions (#145858)

2025-07-21 10:39:09 +02:00

AMDGPUCodeGenPrepare.cpp

[AMDGPU] Remove unused functions isSigned. NFC (#169750)

2025-11-27 01:32:26 +00:00

AMDGPUCombine.td

[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)

2025-10-24 17:25:00 +02:00

AMDGPUCombinerHelper.cpp

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

AMDGPUCombinerHelper.h

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

AMDGPUCtorDtorLowering.cpp

…

AMDGPUCtorDtorLowering.h

…

AMDGPUExportClustering.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUExportClustering.h

…

AMDGPUExportKernelRuntimeHandles.cpp

AMDGPU: Move enqueued block handling into clang (#128519)

2025-03-10 19:54:04 +07:00

AMDGPUExportKernelRuntimeHandles.h

AMDGPU: Move enqueued block handling into clang (#128519)

2025-03-10 19:54:04 +07:00

AMDGPUFeatures.td

[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)

2025-08-14 12:52:00 -07:00

AMDGPUFrameLowering.cpp

…

AMDGPUFrameLowering.h

…

AMDGPUGenRegisterBankInfo.def

…

AMDGPUGISel.td

AMDGPU: Use srcvalue and delete Ignore complex pattern (#161359)

2025-09-30 16:18:51 +02:00

AMDGPUGlobalISelDivergenceLowering.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUGlobalISelUtils.cpp

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

AMDGPUGlobalISelUtils.h

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

AMDGPUHSAMetadataStreamer.cpp

[AMDGPU] Add the support for .cluster_dims code object metadata (#158721)

2025-09-15 16:13:07 -04:00

AMDGPUHSAMetadataStreamer.h

[Target] Add "override" where appropriate (NFC) (#165083)

2025-10-25 06:23:43 -07:00

AMDGPUIGroupLP.cpp

[NFC][AMDGPU] IGLP: Fixes for unsigned int handling (#135090)

2025-11-18 20:47:41 +01:00

AMDGPUIGroupLP.h

Remove unused <vector> inclusion (#166997)

2025-11-08 20:42:00 +00:00

AMDGPUImageIntrinsicOptimizer.cpp

[AMDGPU] Change placeholder from undef to poison (#130853)

2025-03-12 12:52:38 +00:00

AMDGPUInsertDelayAlu.cpp

[AMDGPU] Use MCRegUnit, insert explicit casts to/from unsigned (NFC) (#167889)

2025-11-13 21:39:02 +03:00

AMDGPUInstCombineIntrinsic.cpp

[AMDGPU] gfx1250 v_wmma_scale[16]_f32_16x16x128_f8f6f4 codegen (#152036)

2025-08-04 19:16:34 -07:00

AMDGPUInstrInfo.cpp

AMDGPU: Fix treating divergent loads as uniform (#168785)

2025-11-20 11:10:24 -05:00

AMDGPUInstrInfo.h

[AMDGPU] Support image atomic no return instructions (#150742)

2025-10-29 10:42:15 +08:00

AMDGPUInstrInfo.td

[AMDGPU] TableGen-erate SDNode descriptions (#168248)

2025-11-17 00:10:07 +00:00

AMDGPUInstructions.td

[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)

2025-09-04 09:19:25 +00:00

AMDGPUInstructionSelector.cpp

AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)

2025-11-25 18:55:34 +00:00

AMDGPUInstructionSelector.h

AMDGPU: Use srcvalue and delete Ignore complex pattern (#161359)

2025-09-30 16:18:51 +02:00

AMDGPUISelDAGToDAG.cpp

AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)

2025-11-25 18:55:34 +00:00

AMDGPUISelDAGToDAG.h

[AMDGPU] TableGen-erate SDNode descriptions (#168248)

2025-11-17 00:10:07 +00:00

AMDGPUISelLowering.cpp

[AMDGPU] Propagate AA info in vector load/store splitting. (#168871)

2025-11-24 03:30:35 +00:00

AMDGPUISelLowering.h

CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)

2025-11-19 19:18:13 +00:00

AMDGPULaneMaskUtils.h

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

AMDGPULateCodeGenPrepare.cpp

[AMDGPU] LRO: allow same-BB non-lookthrough users for PHI (#160909)

2025-09-30 00:57:07 +09:00

AMDGPULegalizerInfo.cpp

[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)

2025-11-25 15:43:18 +00:00

AMDGPULegalizerInfo.h

[AMDGPU] Support lowering of cluster related instrinsics (#157978)

2025-09-12 21:11:17 -04:00

AMDGPULibCalls.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPULibFunc.cpp

[AMDGPU] Provide default value in get intrinsic param type (#122448)

2025-01-10 15:29:42 +01:00

AMDGPULibFunc.h

AMDGPU: Verify function type matches when matching libcalls (#119043)

2024-12-16 15:01:48 +09:00

AMDGPULowerBufferFatPointers.cpp

[AMDGPU][LowerBufferFatPointers] Fix crash with select false (#166471)

2025-11-05 19:21:52 +00:00

AMDGPULowerExecSync.cpp

[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)

2025-11-25 15:43:18 +00:00

AMDGPULowerIntrinsics.cpp

[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)

2025-09-16 14:49:48 -07:00

AMDGPULowerKernelArguments.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPULowerKernelAttributes.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPULowerModuleLDSPass.cpp

[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)

2025-11-25 15:43:18 +00:00

AMDGPULowerVGPREncoding.cpp

[AMDGPU] Record old VGPR MSBs in the high bits of s_set_vgpr_msb (#165035)

2025-10-31 12:21:59 -07:00

AMDGPULowerVGPREncoding.h

[AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (#156971)

2025-09-05 00:07:47 -07:00

AMDGPUMachineFunction.cpp

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUMachineFunction.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUMachineModuleInfo.cpp

[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)

2025-09-10 11:41:43 +02:00

AMDGPUMachineModuleInfo.h

[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)

2025-09-10 11:41:43 +02:00

AMDGPUMacroFusion.cpp

…

AMDGPUMacroFusion.h

[CodeGen] Move MISched target hooks into TargetMachine (#125700)

2025-02-05 11:41:37 +05:30

AMDGPUMarkLastScratchLoad.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUMCInstLower.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPUMCInstLower.h

[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)

2025-09-24 11:27:26 -04:00

AMDGPUMCResourceInfo.cpp

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUMCResourceInfo.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPUMemoryUtils.cpp

[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)

2025-11-25 15:43:18 +00:00

AMDGPUMemoryUtils.h

[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)

2025-11-25 15:43:18 +00:00

AMDGPUMIRFormatter.cpp

[AMDGPU] Remove unused includes (NFC) (#116154)

2024-11-13 21:10:03 -08:00

AMDGPUMIRFormatter.h

[Target] Add "override" where appropriate (NFC) (#165083)

2025-10-25 06:23:43 -07:00

AMDGPUPassRegistry.def

[AMDGPU] Add amdgpu-lower-exec-sync pass to lower named-barrier globals (#165692)

2025-11-17 10:08:40 +05:30

AMDGPUPerfHintAnalysis.cpp

[llvm] Remove unused includes of SmallSet.h (NFC) (#154893)

2025-08-22 10:33:46 -07:00

AMDGPUPerfHintAnalysis.h

[llvm] Use "= default" (NFC) (#166088)

2025-11-02 17:16:47 -08:00

AMDGPUPostLegalizerCombiner.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

AMDGPUPredicateControl.td

…

AMDGPUPreLegalizerCombiner.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPUPreloadKernArgProlog.cpp

[AMDGPU] Enable kernarg preload on gfx1250 (#153686)

2025-08-14 16:29:53 -07:00

AMDGPUPreloadKernArgProlog.h

[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)

2025-01-10 11:39:02 -08:00

AMDGPUPreloadKernelArguments.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPUPrepareAGPRAlloc.cpp

AMDGPU: Start using AV_MOV_B64_IMM_PSEUDO (#154500)

2025-08-22 13:59:36 +09:00

AMDGPUPrepareAGPRAlloc.h

AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)

2025-07-18 17:15:38 +09:00

AMDGPUPrintfRuntimeBinding.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPUPromoteAlloca.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPUPromoteKernelArguments.cpp

…

AMDGPUPTNote.h

…

AMDGPURegBankCombiner.cpp

AMDGPU/GlobalISel: Import D16 load patterns and add combines for them (#153178)

2025-09-11 12:02:50 +02:00

AMDGPURegBankLegalize.cpp

AMDGPU/GlobalISel: Combine S16 copy-trunc-readanylane-anyext (#168410)

2025-11-24 15:57:07 +01:00

AMDGPURegBankLegalizeHelper.cpp

AMDGPU/GlobalISel: RegBankLegalize rules for G_FABS and G_FNEG (#168411)

2025-11-24 16:35:28 +01:00

AMDGPURegBankLegalizeHelper.h

AMDGPU/GlobalISel: RegBankLegalize rules for G_FABS and G_FNEG (#168411)

2025-11-24 16:35:28 +01:00

AMDGPURegBankLegalizeRules.cpp

AMDGPU/GlobalISel: RegBankLegalize rules for G_FABS and G_FNEG (#168411)

2025-11-24 16:35:28 +01:00

AMDGPURegBankLegalizeRules.h

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BLOCK_ADDR and G_GLOBAL_VALUE (#165340)

2025-11-11 09:31:59 -08:00

AMDGPURegBankSelect.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

AMDGPURegisterBankInfo.cpp

[AMDGPU] Add wave reduce intrinsics for float types - 2 (#168859)

2025-11-24 14:25:53 +05:30

AMDGPURegisterBankInfo.h

…

AMDGPURegisterBanks.td

AMDGPU: Start using RegClassByHwMode for wavesize operands

2025-11-11 15:07:59 -08:00

AMDGPURemoveIncompatibleFunctions.cpp

[AMDGPU] Remove wave64 functions (#153690)

2025-08-14 15:54:33 -07:00

AMDGPURemoveIncompatibleFunctions.h

[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)

2025-01-13 10:11:40 +05:30

AMDGPUReserveWWMRegs.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUReserveWWMRegs.h

[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM (#123722)

2025-03-10 17:36:35 +05:30

AMDGPUResourceUsageAnalysis.cpp

[AMDGPU] Remove calling conv check on entry function (#162080)

2025-11-10 16:27:55 -05:00

AMDGPUResourceUsageAnalysis.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

AMDGPURewriteAGPRCopyMFMA.cpp

[AMDGPU] Make sort ordering in AMDGPURewriteAGPRCopyMFMAImpl::eliminateSpillsOfReassignedVGPRs() strict weak. (#162493)

2025-10-08 13:05:08 -04:00

AMDGPURewriteOutArguments.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

AMDGPURewriteUndefForPHI.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUSearchableTables.td

[AMDGPU] Mark cluster_workgroup_id_* intrinsics always uniform (#159439)

2025-09-17 14:07:52 -07:00

AMDGPUSelectionDAGInfo.cpp

[AMDGPU] TableGen-erate SDNode descriptions (#168248)

2025-11-17 00:10:07 +00:00

AMDGPUSelectionDAGInfo.h

[AMDGPU] TableGen-erate SDNode descriptions (#168248)

2025-11-17 00:10:07 +00:00

AMDGPUSetWavePriority.cpp

[llvm] Replace SmallSet with SmallPtrSet (NFC) (#154068)

2025-08-18 07:01:29 -07:00

AMDGPUSplitModule.cpp

[AMDGPU] Remove const on a return type. (#168490)

2025-11-18 07:16:58 -08:00

AMDGPUSplitModule.h

…

AMDGPUSubtarget.cpp

[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)

2025-11-25 15:43:18 +00:00

AMDGPUSubtarget.h

[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)

2025-09-17 10:09:06 -04:00

AMDGPUSwLowerLDS.cpp

[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)

2025-11-25 15:43:18 +00:00

AMDGPUTargetMachine.cpp

AMDGPU: Stop forcing RequiresCodeGenSCCOrder (#169522)

2025-11-25 13:23:55 -05:00

AMDGPUTargetMachine.h

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

AMDGPUTargetObjectFile.cpp

…

AMDGPUTargetObjectFile.h

…

AMDGPUTargetTransformInfo.cpp

AMDGPU: Improve getShuffleCost accuracy for 8- and 16-bit shuffles (#168818)

2025-11-21 19:33:13 +00:00

AMDGPUTargetTransformInfo.h

[AMDGPU] Enable vectorization of i8 values. (#134934)

2025-06-26 19:15:31 -04:00

AMDGPUUniformIntrinsicCombine.cpp

[AMDGPU] Stop optimising readfirstlane in pass AMDGPUUniformIntrinsicCombine (#166955)

2025-11-08 01:17:39 +05:30

AMDGPUUnifyDivergentExitNodes.cpp

Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)

2025-11-03 20:59:48 +01:00

AMDGPUUnifyDivergentExitNodes.h

…

AMDGPUWaitSGPRHazards.cpp

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

AMDGPUWaitSGPRHazards.h

[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)

2025-01-30 11:21:11 +09:00

AMDKernelCodeT.h

…

BUFInstructions.td

AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)

2025-10-08 11:19:54 +09:00

CaymanInstructions.td

…

CMakeLists.txt

[AMDGPU] Add amdgpu-lower-exec-sync pass to lower named-barrier globals (#165692)

2025-11-17 10:08:40 +05:30

DSDIRInstructions.td

AMDGPU: Remove LDS-direct(param)-loads and VINTERP ops from gfx1250 support (#145631)

2025-06-24 22:44:35 -07:00

DSInstructions.td

AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)

2025-11-25 18:55:34 +00:00

EvergreenInstructions.td

Remove an unused field (follow up to cc5e8967)

2025-08-30 07:55:56 +03:00

EXPInstructions.td

AMDGPU: Remove export and related instructions from gfx1250 support (#145624)

2025-06-24 19:59:26 -07:00

FLATInstructions.td

[AMDGPU][True16][CodeGen] lower flat_d16_saddr_t16 to saddr inst (#166603)

2025-11-14 09:47:05 -05:00

GCNCreateVOPD.cpp

[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)

2025-07-10 14:15:01 -07:00

GCNDPPCombine.cpp

AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)

2025-10-08 11:19:54 +09:00

GCNDPPCombine.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

GCNHazardRecognizer.cpp

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

GCNHazardRecognizer.h

[AMDGPU] w/a for s_setreg_b32 gfx1250 hazard with MODE register (#153879)

2025-08-15 16:08:13 -07:00

GCNILPSched.cpp

…

GCNIterativeScheduler.cpp

[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)

2025-06-24 11:09:36 +02:00

GCNIterativeScheduler.h

[AMDGPU] Teach iterative schedulers about IGLP (#134953)

2025-04-11 15:34:49 -07:00

GCNMinRegStrategy.cpp

…

GCNNSAReassign.cpp

[llvm] Use conventional enum declarations (NFC) (#166318)

2025-11-04 07:12:53 -08:00

GCNNSAReassign.h

[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager (#125034)

2025-02-18 11:13:31 +05:30

GCNPreRALongBranchReg.cpp

[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)

2025-02-05 18:46:27 +05:30

GCNPreRALongBranchReg.h

[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)

2025-02-05 18:46:27 +05:30

GCNPreRAOptimizations.cpp

[AMDGPU][NFC] Avoid copying MachineOperands (#166293)

2025-11-04 23:18:40 -06:00

GCNPreRAOptimizations.h

[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)

2025-02-11 11:09:38 +05:30

GCNProcessors.td

[AMDGPU] Add gfx1251 subtarget (#159430)

2025-09-17 13:02:02 -07:00

GCNRegPressure.cpp

[AMDGPU] Delete some dead code (NFC) (#167891)

2025-11-15 06:30:07 +03:00

GCNRegPressure.h

[llvm] Use llvm::size (NFC) (#168675)

2025-11-19 07:29:57 -08:00

GCNRewritePartialRegUses.cpp

[AMDGPU] Simplify GCNRewritePartialRegUses pass. (#135199)

2025-04-11 15:45:24 +02:00

GCNRewritePartialRegUses.h

[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)

2025-02-12 11:21:40 +05:30

GCNSchedStrategy.cpp

[AMDGPU] Fixed crash in getLastMIForRegion when the region is empty. (#168653)

2025-11-19 16:19:20 -08:00

GCNSchedStrategy.h

[AMDGPU] Avoid changing minOccupancy if unclustered schedule was not run for any region. (#162025)

2025-11-12 10:11:22 -08:00

GCNSubtarget.cpp

AMDGPU: Remove triple field from subtarget (#164208)

2025-10-20 06:58:16 +00:00

GCNSubtarget.h

[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#168852)

2025-11-25 10:11:04 +01:00

GCNVOPDUtils.cpp

[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)

2025-07-10 14:15:01 -07:00

GCNVOPDUtils.h

[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)

2025-07-10 14:15:01 -07:00

InstCombineTables.td

…

MIMGInstructions.td

[AMDGPU] Set VADDR4 field to NULL for tensor ops for gfx1250 (#165917)

2025-10-31 16:48:20 -07:00

R600.h

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

R600.td

CodeGen: Make all targets override pseudos with pointers (#159881)

2025-11-26 14:57:14 +00:00

R600AsmPrinter.cpp

…

R600AsmPrinter.h

[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel

2025-03-29 11:08:13 -07:00

R600ClauseMergePass.cpp

…

R600ControlFlowFinalizer.cpp

…

R600Defines.h

…

R600EmitClauseMarkers.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

R600ExpandSpecialInstrs.cpp

[CodeGen] Remove FinalizeMachineBundles pass (#149806)

2025-07-23 11:36:49 +01:00

R600FrameLowering.cpp

…

R600FrameLowering.h

…

R600InstrFormats.td

…

R600InstrInfo.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

R600InstrInfo.h

[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)

2025-02-24 09:55:34 -08:00

R600InstrInfo.td

…

R600Instructions.td

[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)

2025-08-30 04:44:20 +00:00

R600ISelDAGToDAG.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

R600ISelLowering.cpp

CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)

2025-11-19 19:18:13 +00:00

R600ISelLowering.h

…

R600MachineCFGStructurizer.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

R600MachineFunctionInfo.cpp

…

R600MachineFunctionInfo.h

…

R600MachineScheduler.cpp

…

R600MachineScheduler.h

…

R600MCInstLower.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

R600OpenCLImageTypeLoweringPass.cpp

…

R600OptimizeVectorRegisters.cpp

[AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)

2025-06-04 12:30:56 -07:00

R600Packetizer.cpp

[TableGen] Add mapping from processor ID to resource index for packetizer (#158182)

2025-09-17 09:12:37 +08:00

R600Processors.td

…

R600RegisterInfo.cpp

…

R600RegisterInfo.h

…

R600RegisterInfo.td

…

R600Schedule.td

…

R600Subtarget.cpp

[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)

2024-12-16 15:13:46 +03:00

R600Subtarget.h

CodeGen: Remove target hook for terminal rule (#165962)

2025-11-12 21:12:19 +00:00

R600TargetMachine.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

R600TargetMachine.h

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

R600TargetTransformInfo.cpp

[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)

2025-05-01 15:55:08 +01:00

R600TargetTransformInfo.h

[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)

2025-05-01 15:55:08 +01:00

R700Instructions.td

…

SIAnnotateControlFlow.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

SIDefines.h

[AMDGPU] Enable volatile and non-temporal for loads to LDS (#153244)

2025-10-20 12:42:22 -05:00

SIFixSGPRCopies.cpp

[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)

2025-11-21 15:17:55 +00:00

SIFixSGPRCopies.h

…

SIFixVGPRCopies.cpp

[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)

2025-01-21 15:27:46 +05:30

SIFixVGPRCopies.h

[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)

2025-01-21 15:27:46 +05:30

SIFoldOperands.cpp

[NFC] Check operand type instead of opcode (#168641)

2025-11-18 21:37:56 -05:00

SIFoldOperands.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIFormMemoryClauses.cpp

[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)

2025-06-24 11:09:36 +02:00

SIFormMemoryClauses.h

[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)

2025-02-17 11:07:17 +05:30

SIFrameLowering.cpp

[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)

2025-11-21 19:42:17 +05:30

SIFrameLowering.h

Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)

2025-04-25 11:29:27 +02:00

SIInsertHardClauses.cpp

[AMDGPU] Adjust hard clause rules for gfx1250 (#152592)

2025-08-07 14:59:31 -07:00

SIInsertWaitcnts.cpp

[AMDGPU][SIInsertWaitCnts] Gfx12.5 - Refactor xcnt optimization (#164357)

2025-11-13 18:43:12 +00:00

SIInstrFormats.td

CodeGen: Add RegisterClass by HwMode (#158269)

2025-09-19 20:08:51 +09:00

SIInstrInfo.cpp

[AMDGPU][NPM] Fix CFG invalidation detection in insertSimulatedTrap (#169290)

2025-11-28 13:45:46 +05:30

SIInstrInfo.h

AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)

2025-11-25 18:55:34 +00:00

SIInstrInfo.td

[AMDGPU] Simplify VT comparisons. NFC. (#169526)

2025-11-25 20:22:56 +00:00

SIInstructions.td

CodeGen: Make all targets override pseudos with pointers (#159881)

2025-11-26 14:57:14 +00:00

SIISelLowering.cpp

AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)

2025-11-25 18:55:34 +00:00

SIISelLowering.h

DAG: Remove TargetLowering::checkForPhysRegDependency (#161787)

2025-10-03 15:58:51 +00:00

SILateBranchLowering.cpp

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

SILoadStoreOptimizer.cpp

CodeGen: Remove TRI argument from getRegClass (#158225)

2025-11-10 15:43:55 -08:00

SILoadStoreOptimizer.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerControlFlow.cpp

[AMDGPU] SILowerControlFlow: ensure EXEC/SCC interval recompute (#160459)

2025-09-24 18:30:40 +09:00

SILowerControlFlow.h

[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)

2025-01-16 11:06:38 +05:30

SILowerI1Copies.cpp

AMDGPU: Start using RegClassByHwMode for wavesize operands

2025-11-11 15:07:59 -08:00

SILowerI1Copies.h

AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)

2025-03-12 12:09:37 +01:00

SILowerSGPRSpills.cpp

CodeGen: Remove TRI arguments from stack load/store hooks (#158240)

2025-11-10 16:24:39 -08:00

SILowerSGPRSpills.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerWWMCopies.cpp

[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)

2025-01-22 14:54:01 +05:30

SILowerWWMCopies.h

[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)

2025-01-22 14:54:01 +05:30

SIMachineFunctionInfo.cpp

[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)

2025-11-22 14:03:14 -08:00

SIMachineFunctionInfo.h

[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)

2025-11-22 14:03:14 -08:00

SIMachineScheduler.cpp

[CodeGen] Use VirtRegOrUnit where appropriate (NFCI) (#167730)

2025-11-13 10:26:58 +00:00

SIMachineScheduler.h

[CodeGen] Use VirtRegOrUnit where appropriate (NFCI) (#167730)

2025-11-13 10:26:58 +00:00

SIMemoryLegalizer.cpp

[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#168852)

2025-11-25 10:11:04 +01:00

SIModeRegister.cpp

[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)

2025-03-04 10:51:03 +05:30

SIModeRegisterDefaults.cpp

…

SIModeRegisterDefaults.h

…

SIOptimizeExecMasking.cpp

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

SIOptimizeExecMasking.h

[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)

2025-01-20 16:34:01 +05:30

SIOptimizeExecMaskingPreRA.cpp

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16 03:22:14 +00:00

SIOptimizeExecMaskingPreRA.h

[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)

2025-02-20 17:35:56 +05:30

SIOptimizeVGPRLiveRange.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

SIOptimizeVGPRLiveRange.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIPeepholeSDWA.cpp

[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)

2025-11-14 11:00:57 +00:00

SIPeepholeSDWA.h

…

SIPostRABundler.cpp

[AMDGPU] Use MCRegUnit, insert explicit casts to/from unsigned (NFC) (#167889)

2025-11-13 21:39:02 +03:00

SIPostRABundler.h

[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)

2025-02-21 16:05:58 +05:30

SIPreAllocateWWMRegs.cpp

[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)

2025-08-22 10:05:06 +01:00

SIPreAllocateWWMRegs.h

…

SIPreEmitPeephole.cpp

[AMDGPU][NFC] Avoid copying MachineOperands (#166293)

2025-11-04 23:18:40 -06:00

SIProgramInfo.cpp

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

SIProgramInfo.h

[AMDGPU] upstream barrier count reporting part1 (#154409)

2025-08-19 16:42:31 -07:00

SIRegisterInfo.cpp

AMDGPU: Stop implementing shouldCoalesce (#168988)

2025-11-21 10:10:35 -05:00

SIRegisterInfo.h

AMDGPU: Stop implementing shouldCoalesce (#168988)

2025-11-21 10:10:35 -05:00

SIRegisterInfo.td

AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)

2025-11-25 18:55:34 +00:00

SISchedule.td

AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)

2025-07-21 10:09:42 -07:00

SIShrinkInstructions.cpp

[AMDGPU] When shrinking and/or to bitset*, remove implicit scc def (#168128)

2025-11-15 09:21:43 -06:00

SIShrinkInstructions.h

…

SIWholeQuadMode.cpp

[CodeGen] Use VirtRegOrUnit where appropriate (NFCI) (#167730)

2025-11-13 10:26:58 +00:00

SIWholeQuadMode.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SMInstructions.td

[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)

2025-08-30 04:44:20 +00:00

SOPInstructions.td

[AMDGPU] Generate s_absdiff_i32 (#164835)

2025-10-27 14:40:56 -05:00

VIInstrFormats.td

…

VINTERPInstructions.td

[AMDGPU][True16][CodeGen] support for true16 for vinterp 16bit instructions (#116702)

2024-12-09 11:52:05 -05:00

VOP1Instructions.td

[AMDGPU] Adding instruction specific features (#167809)

2025-11-19 11:06:00 +08:00

VOP2Instructions.td

[AMDGPU] Adding instruction specific features (#167809)

2025-11-19 11:06:00 +08:00

VOP3Instructions.td

[AMDGPU] Simplify VT comparisons. NFC. (#169526)

2025-11-25 20:22:56 +00:00

VOP3PInstructions.td

[AMDGPU] Change encoding of gfx1250 ld_scale (#167777)

2025-11-12 16:03:09 -08:00

VOPCInstructions.td

AMDGPU: Start using RegClassByHwMode for wavesize operands

2025-11-11 15:07:59 -08:00

VOPDInstructions.td

[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516)

2025-09-09 10:54:18 -04:00

VOPInstructions.td

AMDGPU: Start using RegClassByHwMode for wavesize operands

2025-11-11 15:07:59 -08:00