Jeffrey Byrnes 122e79c35f

[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977) ...

There are three calls to bumpCycle in bumpNode. Prior to the first call,
we calculate NextCycle as the next cycle in which all of a given
instruction's required hardware resources (as defined by the SchedModel)
are available. Any gap between this calculated NextCycle and CurrCycle
measures stalls that must occur before we can schedule the given
instruction.

The second and third call handle adjustments that occur during or after
issuing of the instruction (e.g. if the number of microops exceeds the
issue width).

According to the documentation of HazardRec->EmitInstruction, we should
call this method when an instruction is emitted: "This callback is
invoked when an instruction is emitted, to advance the hazard state."

In the context of bumpNode, this implies that it should be called after
we bumpCycle for stalls that must occur before issue of the
instructions, but before those that occur during or after. This PR moves
the placement to do that.

In practice, this affects schedulers that use both the SchedModel and
HazardRec. Suppose we have instructions A, B and C, and partial schedule
AB. Also, suppose instruction A exclusively holds ProcResource X for 2
cycles, and B uses ProcResource X, and there is a HazardRec hazard
between B and C which requires 1 cycle stall.

Currently, we call HazardRec->EmitInstruction on B before we call
HazardRec->AdvanceCycle for the stall between A->B. Then, when deciding
whether to schedule C, HazardRec sees that a cycle has already occurred
after B, so we do not need to stall.

After this change, we HazardRec->EmitInstruction on B after we call
HazardRec->AdvanceCycle for the stall between A->B. So, HazardRec
accurately places the stall cycle between A and B. Then, when deciding
whether to schedule C, HazardRec accurately sees that no cycles have
occurred after B, so we do need to stall for 1 cycle.

2026-02-25 15:24:54 -08:00

..

add_shl.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

add.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

add.v2i16.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

add.vni16.ll

AMDGPU/GlobalISel: Regbanklegalize for G_CONCAT_VECTORS (#171471)

2025-12-15 10:37:40 +01:00

addo.ll

[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)

2026-02-11 09:06:28 -08:00

addsubu64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

amdgpu-irtranslator.ll

Revert "[LSV] Merge contiguous chains across scalar types" (#170381)

2025-12-02 18:27:58 -05:00

amdgpu-prelegalizer-combiner-crash.mir

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and.ll

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andn2.i1.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

andn2.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

artifact-combiner-anyext.mir

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artifact-combiner-asserts.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

artifact-combiner-build-vector.mir

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artifact-combiner-concat-vectors.mir

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artifact-combiner-cse-leaves-dead-cast.mir

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artifact-combiner-extract.mir

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artifact-combiner-sext.mir

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artifact-combiner-trunc.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

artifact-combiner-unmerge-values.mir

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artifact-combiner-zext.mir

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ashr.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

assert-align.ll

[AMDGPU][GISel] Add RegbankLegalize Rules for G_ASSERT_ALIGN (#182353)

2026-02-19 12:30:31 -08:00

atomic_load_flat.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

atomic_load_global.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

atomic_load_local_2.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

atomic_load_local.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

atomic_optimizations_mul_one.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

atomic_store_local.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

atomicrmw_fmax.ll

[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)

2026-02-05 10:13:51 -06:00

atomicrmw_fmin.ll

[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)

2026-02-05 10:13:51 -06:00

atomicrmw_minmax.ll

[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)

2026-02-10 16:04:05 +05:30

atomicrmw_udec_wrap.ll

[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)

2026-02-10 16:04:05 +05:30

atomicrmw_uinc_wrap.ll

[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)

2026-02-10 16:04:05 +05:30

atomicrmw-add-sub.ll

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

atomicrmw-and.ll

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

atomicrmw-or.ll

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

atomicrmw-xchg.ll

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

atomicrmw-xor.ll

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

bitcast_38_i16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

bool-legalization.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

br-constant-invalid-sgpr-copy.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

bswap.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

buffer-atomic-fadd.f32-no-rtn.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

buffer-atomic-fadd.f32-rtn.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

buffer-atomic-fadd.f64.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

buffer-atomic-fadd.v2f16-no-rtn.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

buffer-atomic-fadd.v2f16-rtn.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

buffer-load-byte-short.ll

[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#172065)

2025-12-12 14:47:08 -06:00

buffer-load-store-pointers.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

buffer-schedule.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

bug_shuffle_vector_to_scalar.ll

[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)

2026-02-17 18:46:18 -05:00

bug-legalization-artifact-combiner-dead-def.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

bug-legalization-artifact-combiner-dead-def.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

call-outgoing-stack-args.ll

[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)

2025-09-16 15:37:01 -04:00

clamp-fmed3-const-combine.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)

2026-02-20 09:44:58 -08:00

clamp-minmax-const-combine.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)

2026-02-20 09:44:58 -08:00

combine-add-nullptr.mir

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combine-add-to-ptradd.mir

…

combine-amdgpu-cvt-f32-ubyte.mir

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combine-ashr-narrow.mir

…

combine-binop-s64-with-s32-mask.mir

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

combine-ext-legalizer.mir

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combine-extract-vector-load.mir

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combine-fabs-fneg.mir

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combine-fcanonicalize.mir

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combine-fdiv-sqrt-to-rsq.mir

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combine-fma-add-ext-fma.ll

[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)

2026-02-05 11:51:25 +01:00

combine-fma-add-ext-mul.ll

[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)

2026-02-05 11:51:25 +01:00

combine-fma-add-fma-mul.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)

2025-12-22 09:05:31 -08:00

combine-fma-add-mul-post-legalize.mir

[GlobalISel] Remove UnsafeFPMath references (#146319)

2025-07-29 12:11:52 +08:00

combine-fma-add-mul-pre-legalize.mir

[GlobalISel] Remove UnsafeFPMath references (#146319)

2025-07-29 12:11:52 +08:00

combine-fma-add-mul.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)

2025-12-22 09:05:31 -08:00

combine-fma-sub-ext-mul.ll

[AMDGPU] Fix and simplify patterns selecting fsub to v_fma_mix_f32 (#180169)

2026-02-06 14:39:13 +00:00

combine-fma-sub-ext-neg-mul.ll

[AMDGPU] Fix and simplify patterns selecting fsub to v_fma_mix_f32 (#180169)

2026-02-06 14:39:13 +00:00

combine-fma-sub-mul.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)

2025-12-22 09:05:31 -08:00

combine-fma-sub-neg-mul.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)

2025-12-22 09:05:31 -08:00

combine-fma-unmerge-values.mir

[CodeGen] Remove -enable-unsafe-fp-math option (#164559)

2025-10-22 15:40:31 +08:00

combine-fold-binop-into-select.mir

[GlobaISel] Allow expanding of sdiv -> mul by constant (#146504)

2025-07-14 15:01:12 +01:00

combine-foldable-fneg.mir

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combine-fpneg-one-fneg.mir

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combine-fsh.mir

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combine-fsub-fneg.mir

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combine-itofp.mir

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combine-lshr-narrow.mir

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combine-or-redundant.mir

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combine-or-s64-s32.mir

[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)

2025-10-24 17:25:00 +02:00

combine-redundant-and.mir

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combine-redundant-neg.mir

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combine-redundant-sext-inreg.mir

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combine-rot.mir

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combine-rsq.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

combine-rsq.mir

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combine-sext-inreg.mir

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combine-sext-trunc-sextinreg.mir

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combine-shift-amount-zext.mir

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combine-shift-imm-chain-illegal-types.mir

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combine-shift-imm-chain-shlsat.mir

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combine-shift-imm-chain.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

combine-shift-of-shifted-logic-shlsat.mir

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combine-shift-of-shifted-logic.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

combine-shifts.mir

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combine-shl-from-extend-narrow.postlegal.mir

[GlobalISel] Rewrite binop_left_to_zero using MIR Patterns (#177924)

2026-01-29 18:28:34 +00:00

combine-shl-from-extend-narrow.prelegal.mir

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combine-shl-narrow.mir

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combine-short-clamp.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for SMED3 and CVT_PK_I16_I32 (#176596)

2026-01-21 08:57:53 -08:00

combine-trunc-sext.mir

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combine-trunc-shift.mir

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combine-urem-pow-2.mir

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combine-zext-trunc.mir

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combiner-crash.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

compute-num-sign-bits-med3.mir

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constant-bus-restriction.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

crash-stack-address-O0.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

cvt_f32_ubyte.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

dereferenceable-declaration.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)

2025-10-10 08:48:06 -07:00

divergence-divergent-i1-phis-no-lane-mask-merging.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

divergence-divergent-i1-phis-no-lane-mask-merging.mir

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divergence-divergent-i1-used-outside-loop.ll

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

divergence-divergent-i1-used-outside-loop.mir

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divergence-structurizer.ll

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

divergence-structurizer.mir

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divergence-temporal-divergent-i1.ll

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

divergence-temporal-divergent-i1.mir

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divergence-temporal-divergent-reg.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

divergence-temporal-divergent-reg.mir

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divergent-control-flow.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

dropped_debug_info_assert.ll

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dummy-target.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

dynamic-alloca-uniform.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

extractelement-stack-lower.ll

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

extractelement.i8.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

extractelement.i16.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

extractelement.i128.ll

AMDGPU: Fix treating unknown mem operands as uniform (#170309)

2025-12-02 16:19:46 +00:00

extractelement.ll

[AMDGPU] Set GRANULATED_WAVEFRONT_SGPR_COUNT of compute_pgm_rsrc1 to 0 for gfx10+ (#154666)

2025-08-27 09:48:42 +08:00

fabs.ll

[AMDGPU][GlobalISel] Add readanylane combines for merge-like instruct… (#172546)

2025-12-18 08:04:06 -08:00

fadd.ll

[AMDGPU][GlobalISel] Add register bank legalization for G_FADD (#163407)

2025-10-31 16:45:40 +05:30

fcmp.ll

[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)

2026-02-11 09:06:28 -08:00

fdiv.f16.ll

[AMDGPU] Fix pattern selecting fmul to v_fma_mix_f32 (#180210)

2026-02-07 09:31:07 +00:00

fdiv.f32.ll

IR: Promote "denormal-fp-math" to a first class attribute (#174293)

2026-02-05 13:31:26 +00:00

fdiv.f64.ll

[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180940)

2026-02-11 19:14:54 +00:00

flat-atomic-fadd.f32.ll

[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)

2026-02-09 15:37:27 +00:00

flat-atomic-fadd.f64.ll

[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)

2026-02-09 15:37:27 +00:00

flat-atomic-fadd.v2f16.ll

[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)

2026-02-09 15:37:27 +00:00

flat-scratch-init.gfx.ll

[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)

2025-09-16 02:26:32 -07:00

flat-scratch-init.ll

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flat-scratch.ll

[AMDGPU] Remove FeaturePromoteAlloca (#177636)

2026-02-23 15:24:57 -05:00

floor.f64.ll

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fma.ll

AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)

2026-01-22 18:34:06 +00:00

fmad.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)

2025-12-22 09:05:31 -08:00

fmamix-constant-bus-violation.ll

IR: Promote "denormal-fp-math" to a first class attribute (#174293)

2026-02-05 13:31:26 +00:00

fmamix-constant-bus-violation.mir

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fmax_legacy.ll

[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)

2026-02-11 09:06:28 -08:00

fmed3-min-max-const-combine.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)

2026-02-20 09:44:58 -08:00

fmed3.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_FMED3 (#173085)

2025-12-23 17:31:11 -08:00

fmin_legacy.ll

[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)

2026-02-11 09:06:28 -08:00

fmul.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMUL (#167847)

2025-11-17 08:45:49 -08:00

fmul.v2f16.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)

2025-12-22 09:05:31 -08:00

fneg.ll

[AMDGPU][GlobalISel] Add readanylane combines for merge-like instruct… (#172546)

2025-12-18 08:04:06 -08:00

fp64-atomics-gfx90a.ll

[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)

2026-02-05 10:13:51 -06:00

fp-atomics-gfx942.ll

[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)

2026-02-09 15:37:27 +00:00

fp-int-conversions.ll

[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp (#176300)

2026-02-03 11:45:49 -06:00

fpext.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)

2026-02-02 17:55:42 +01:00

fpow.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

fptrunc.ll

[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)

2026-01-30 15:13:33 +00:00

frem.ll

IR: Promote "denormal-fp-math" to a first class attribute (#174293)

2026-02-05 13:31:26 +00:00

fshl.ll

[AMDGPU] Optimize S_OR_B32 to S_ADDK_I32 where possible (#177949)

2026-02-07 09:10:12 +00:00

fshr-new-regbank-select.ll

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

fshr.ll

[AMDGPU] Optimize S_OR_B32 to S_ADDK_I32 where possible (#177949)

2026-02-07 09:10:12 +00:00

fsub.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FSUB (#171244)

2025-12-11 11:55:28 -08:00

function-returns.ll

[GISel] Set more MIFlags when translating GEPs (#151708)

2025-08-04 13:25:33 +02:00

function-returns.v2i65.ll

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global-atomic-fadd.f32-no-rtn.ll

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global-atomic-fadd.f32-rtn.ll

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global-atomic-fadd.f64.ll

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global-atomic-fadd.v2f16-no-rtn.ll

[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)

2026-02-09 15:37:27 +00:00

global-atomic-fadd.v2f16-rtn.ll

[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)

2026-02-09 15:37:27 +00:00

global-value-addrspaces.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

global-value.illegal.ll

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

global-value.ll

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hip.extern.shared.array.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

i1-copy.ll

[AMDGPU] Add missing comma between export target and first export data (#181641)

2026-02-17 09:24:34 +01:00

icmp.ll

[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)

2026-02-11 09:06:28 -08:00

image-waterfall-loop-O0.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

implicit-kernarg-backend-usage-global-isel.ll

[AMDGPU] Add regbankselect rules for G_ICMP/G_FCMP (#172048)

2026-01-14 12:37:16 -05:00

inline-asm-mismatched-size.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

inline-asm.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

insertelement-stack-lower.ll

Revert "CodeGen: Record MMOs in finalizeBundle" (#166520)

2025-11-05 11:11:08 +01:00

insertelement.i8.ll

[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)

2026-01-30 15:13:33 +00:00

insertelement.i16.ll

[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)

2026-01-30 15:13:33 +00:00

insertelement.large.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)

2025-10-10 08:48:06 -07:00

insertelement.ll

[AMDGPU] Remove redundant s_cmp_* after add X, 1 (#176962)

2026-01-23 07:51:36 -06:00

inst-select-abs.mir

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inst-select-add.mir

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inst-select-add.s16.mir

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inst-select-amdgcn.class.mir

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inst-select-amdgcn.class.s16.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-amdgcn.cos.mir

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inst-select-amdgcn.cos.s16.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-amdgcn.cvt.pk.i16.mir

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inst-select-amdgcn.cvt.pk.u16.mir

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inst-select-amdgcn.cvt.pknorm.i16.mir

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inst-select-amdgcn.cvt.pknorm.u16.mir

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inst-select-amdgcn.cvt.pkrtz.mir

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inst-select-amdgcn.ds.swizzle.mir

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inst-select-amdgcn.exp.compr.mir

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inst-select-amdgcn.exp.mir

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inst-select-amdgcn.fcmp.constants.w32.mir

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inst-select-amdgcn.fcmp.constants.w64.mir

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inst-select-amdgcn.fmad.ftz.mir

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inst-select-amdgcn.fmed3.mir

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inst-select-amdgcn.fmed3.s16.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-amdgcn.fract.mir

…

inst-select-amdgcn.fract.s16.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-amdgcn.groupstaticsize.mir

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inst-select-amdgcn.mbcnt.lo.mir

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inst-select-amdgcn.mul.u24.mir

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inst-select-amdgcn.mulhi.i24.mir

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inst-select-amdgcn.mulhi.u24.mir

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inst-select-amdgcn.rcp.legacy.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-amdgcn.rcp.mir

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inst-select-amdgcn.rcp.s16.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-amdgcn.readfirstlane.mir

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inst-select-amdgcn.reloc.constant.mir

…

inst-select-amdgcn.rsq.clamp.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-amdgcn.rsq.legacy.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-amdgcn.rsq.mir

…

inst-select-amdgcn.rsq.s16.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-amdgcn.s.barrier.mir

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inst-select-amdgcn.s.sendmsg.mir

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inst-select-amdgcn.sffbh.mir

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inst-select-amdgcn.sin.mir

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inst-select-amdgcn.sin.s16.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-amdgpu-atomic-cmpxchg-flat.mir

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

inst-select-amdgpu-atomic-cmpxchg-global.mir

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inst-select-amdgpu-ffbh-u32.mir

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inst-select-amdgpu-ffbl-b32.mir

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inst-select-amdgpu-wave-address.mir

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inst-select-and.mir

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inst-select-anyext.mir

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inst-select-ashr.mir

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inst-select-ashr.s16.mir

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inst-select-ashr.v2s16.mir

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inst-select-atomic-cmpxchg-local.mir

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inst-select-atomic-cmpxchg-region.mir

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inst-select-atomicrmw-add-flat.mir

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

inst-select-atomicrmw-add-global.mir

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inst-select-atomicrmw-fadd-local.mir

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inst-select-atomicrmw-fadd-region.mir

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inst-select-atomicrmw-xchg-local.mir

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inst-select-atomicrmw-xchg-region.mir

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inst-select-bitcast.mir

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inst-select-bitreverse.mir

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inst-select-br.mir

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inst-select-brcond.mir

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inst-select-bswap.mir

Reapply "[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and … (#149262)

2025-07-21 10:14:45 -07:00

inst-select-build-vector-trunc.v2s16.mir

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inst-select-build-vector.mir

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inst-select-concat-vectors.mir

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inst-select-constant.mir

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inst-select-copy-scc-vcc.ll

[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)

2026-02-11 09:06:28 -08:00

inst-select-copy-scc-vcc.mir

[AMDGPU][GlobalISel] Clean up selectCOPY_SCC_VCC function (#165797)

2025-10-31 13:17:44 -07:00

inst-select-copy.mir

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inst-select-ctlz-zero-undef.mir

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inst-select-ctpop.mir

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inst-select-cttz-zero-undef.mir

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inst-select-extract-vector-elt.mir

[AMDGPU] Add missing cases for V_INDIRECT_REG_{READ/WRITE}_GPR_IDX and V/S_INDIRECT_REG_WRITE_MOVREL (#171835)

2025-12-12 15:45:34 +00:00

inst-select-extract.mir

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inst-select-fabs.mir

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inst-select-fadd.s16.mir

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inst-select-fadd.s32.mir

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inst-select-fadd.s64.mir

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inst-select-fcanonicalize.mir

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inst-select-fceil.mir

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inst-select-fceil.s16.mir

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inst-select-fcmp.mir

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inst-select-fcmp.s16.gfx11plus-fake16.mir

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inst-select-fcmp.s16.gfx11plus.mir

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inst-select-fcmp.s16.mir

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inst-select-fconstant.mir

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inst-select-fexp2.mir

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inst-select-ffloor.s16.mir

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inst-select-ffloor.s32.mir

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inst-select-ffloor.s64.mir

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inst-select-fma.s32.mir

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inst-select-fmad.s32.mir

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inst-select-fmaxnum-ieee.mir

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inst-select-fmaxnum-ieee.s16.mir

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inst-select-fmaxnum-ieee.v2s16.mir

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inst-select-fmaxnum.mir

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inst-select-fmaxnum.s16.mir

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inst-select-fmaxnum.v2s16.mir

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inst-select-fminnum-ieee.mir

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inst-select-fminnum-ieee.s16.mir

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inst-select-fminnum-ieee.v2s16.mir

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inst-select-fminnum.mir

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inst-select-fminnum.s16.mir

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inst-select-fminnum.v2s16.mir

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inst-select-fmul.mir

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inst-select-fmul.v2s16.mir

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inst-select-fneg.mir

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inst-select-fptosi.mir

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inst-select-fptoui.mir

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inst-select-fract.f64.mir

[CodeGen] Remove -enable-unsafe-fp-math option (#164559)

2025-10-22 15:40:31 +08:00

inst-select-frame-index.mir

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inst-select-freeze.mir

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inst-select-fshr.mir

Reapply "[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and … (#149262)

2025-07-21 10:14:45 -07:00

inst-select-i1-copy.mir

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inst-select-icmp.mir

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inst-select-icmp.s16.mir

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inst-select-icmp.s64.mir

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inst-select-implicit-def.mir

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inst-select-insert-vector-elt.mir

[AMDGPU] Add missing cases for V_INDIRECT_REG_{READ/WRITE}_GPR_IDX and V/S_INDIRECT_REG_WRITE_MOVREL (#171835)

2025-12-12 15:45:34 +00:00

inst-select-insert.mir

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inst-select-intrinsic-trunc.mir

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inst-select-intrinsic-trunc.s16.mir

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inst-select-inttoptr.mir

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inst-select-load-atomic-flat.mir

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

inst-select-load-atomic-global.mir

[AMDGPU] More flatGVS gfx1250 patterns (#149410)

2025-07-17 16:10:59 -07:00

inst-select-load-atomic-local.mir

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inst-select-load-constant.mir

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inst-select-load-flat.mir

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

inst-select-load-global-old-legalization.mir

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inst-select-load-global-saddr.mir

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inst-select-load-global.mir

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inst-select-load-global.s96.mir

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inst-select-load-local-128.mir

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inst-select-load-local.mir

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inst-select-load-private.mir

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inst-select-load-smrd.mir

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inst-select-lshr.mir

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inst-select-lshr.s16.mir

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inst-select-lshr.v2s16.mir

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inst-select-mad_64_32.mir

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inst-select-merge-values.mir

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inst-select-mul.mir

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inst-select-or.mir

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inst-select-pattern-add3.mir

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inst-select-pattern-and-or.mir

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inst-select-pattern-or3.mir

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inst-select-pattern-smed3.mir

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inst-select-pattern-smed3.s16.mir

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inst-select-pattern-umed3.mir

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inst-select-pattern-umed3.s16.mir

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inst-select-pattern-xor3.mir

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inst-select-phi.mir

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inst-select-pseudo-scalar-transcendental.mir

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inst-select-ptr-add.mir

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inst-select-ptrmask.mir

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inst-select-ptrtoint.mir

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inst-select-returnaddress.mir

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inst-select-sbfx.mir

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inst-select-scalar-float-sop1.mir

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inst-select-scalar-float-sop2.mir

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inst-select-scalar-float-sopc.mir

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inst-select-scalar-packed.xfail.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-select.mir

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inst-select-sext-inreg.mir

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inst-select-sext.mir

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inst-select-sextload-local.mir

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inst-select-shl.mir

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inst-select-shl.s16.mir

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inst-select-shl.v2s16.mir

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inst-select-sitofp.mir

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inst-select-smax-64.mir

[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)

2025-08-25 14:32:08 -07:00

inst-select-smax.mir

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inst-select-smin-64.mir

[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)

2025-08-25 14:32:08 -07:00

inst-select-smin.mir

[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)

2025-08-25 14:32:08 -07:00

inst-select-smulh.mir

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inst-select-stacksave-stackrestore.invalid.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

inst-select-stacksave-stackrestore.mir

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inst-select-store-atomic-flat.mir

[AMDGPU] More flatGVS gfx1250 patterns (#149410)

2025-07-17 16:10:59 -07:00

inst-select-store-atomic-local.mir

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inst-select-store-flat.mir

[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)

2025-08-12 09:35:19 +02:00

inst-select-store-global.mir

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inst-select-store-global.s96.mir

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inst-select-store-local.mir

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inst-select-store-private.mir

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inst-select-sub.mir

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inst-select-trunc.mir

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inst-select-trunc.v2s16.mir

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inst-select-uadde.gfx10.mir

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inst-select-uadde.mir

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inst-select-uaddo.mir

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inst-select-ubfx.mir

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inst-select-uitofp.mir

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inst-select-umax-64.mir

[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)

2025-08-25 14:32:08 -07:00

inst-select-umax.mir

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inst-select-umin-64.mir

[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)

2025-08-25 14:32:08 -07:00

inst-select-umin.mir

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inst-select-umulh.mir

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inst-select-unmerge-values.mir

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inst-select-usube.gfx10.mir

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inst-select-usube.mir

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inst-select-usubo.mir

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inst-select-xor.mir

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inst-select-zext.mir

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inst-select-zextload-local.mir

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irtranslate-bf16.ll

AMDGPU: Directly use v2bf16 as register type for bf16 vectors. (#175761)

2026-01-13 17:48:38 +01:00

irtranslator-amdgcn-cs-chain.ll

[AMDGPU] Allow any SGPRs for chain callees (#168345)

2025-12-02 09:44:35 +01:00

irtranslator-amdgcn-sendmsg.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-amdgpu_kernel-system-sgprs.ll

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irtranslator-amdgpu_kernel.ll

[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)

2026-02-17 18:46:18 -05:00

irtranslator-amdgpu_ps.ll

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irtranslator-amdgpu_vs.ll

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irtranslator-assert-align.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-atomicrmw.ll

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irtranslator-call-abi-attribute-hints.ll

[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)

2025-09-16 15:37:01 -04:00

irtranslator-call-implicit-args.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-call-non-fixed.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-call-return-values.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-call-sret.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-call.ll

[AMDGPU] Fix caller/callee mismatch in SGPR assignment for inreg args (#182754)

2026-02-23 18:13:41 +00:00

irtranslator-constant-fold-vector-op.ll

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irtranslator-constantexpr.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-constrained-fp.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-fast-math-flags.ll

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irtranslator-fence.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-fixed-function-abi-vgpr-args.ll

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irtranslator-function-args.ll

AMDGPU: Directly use v2bf16 as register type for bf16 vectors. (#175761)

2026-01-13 17:48:38 +01:00

irtranslator-function-args.v2i65.ll

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irtranslator-getelementptr.ll

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irtranslator-indirect-call.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-inline-asm.ll

[GlobalISel] Add support for value/constants as inline asm memory operand (#161501)

2025-11-14 10:34:38 +01:00

irtranslator-invariant.ll

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

irtranslator-memory-intrinsics.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-metadata.ll

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irtranslator-non-integral-address-spaces-vectors.ll

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irtranslator-non-integral-address-spaces.ll

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irtranslator-prefetch.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-ptrmask.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-readnone-intrinsic-callsite.ll

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irtranslator-sat.ll

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irtranslator-sibling-call.ll

[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)

2025-09-16 15:37:01 -04:00

irtranslator-struct-return-intrinsics.ll

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irtranslator-tail-call.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

irtranslator-zext-vec-index.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

is-safe-to-sink-bug.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

known-bits-sbfe.mir

[AMDGPU] Compute GISel KnownBits for S_BFE instructions (#141588)

2025-07-16 09:56:45 +02:00

knownbits-ptrtoint.mir

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lds-global-value.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

lds-misaligned-bug.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)

2025-10-10 08:48:06 -07:00

lds-relocs.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BLOCK_ADDR and G_GLOBAL_VALUE (#165340)

2025-11-11 09:31:59 -08:00

lds-zero-initializer.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BLOCK_ADDR and G_GLOBAL_VALUE (#165340)

2025-11-11 09:31:59 -08:00

legalize-abs.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-add.mir

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legalize-addrspacecast.mir

AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)

2025-12-01 18:40:26 -05:00

legalize-amdgcn.if-invalid.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

legalize-amdgcn.if.xfail.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

legalize-amdgcn.rsq.clamp.mir

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legalize-amdgcn.wavefrontsize.mir

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legalize-amdgcn.workitem.id.mir

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legalize-and.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-anyext.mir

…

legalize-ashr.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-atomic-cmpxchg-with-success.mir

…

legalize-atomic-cmpxchg.mir

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legalize-atomicrmw-add.mir

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legalize-atomicrmw-and.mir

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legalize-atomicrmw-fadd-global.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

legalize-atomicrmw-fadd-local.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

legalize-atomicrmw-max.mir

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legalize-atomicrmw-min.mir

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legalize-atomicrmw-nand.mir

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legalize-atomicrmw-or.mir

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legalize-atomicrmw-sub.mir

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legalize-atomicrmw-umax.mir

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legalize-atomicrmw-umin.mir

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legalize-atomicrmw-xchg-flat.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

legalize-atomicrmw-xchg.mir

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legalize-atomicrmw-xor.mir

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legalize-bitcast.mir

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legalize-bitreverse.mir

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legalize-block-addr.mir

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legalize-brcond.mir

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legalize-bswap.mir

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legalize-build-vector-splat.mir

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legalize-build-vector-trunc.mir

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legalize-build-vector.mir

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legalize-build-vector.s16.mir

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legalize-concat-vectors.mir

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legalize-constant.mir

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legalize-ctlz-zero-undef.mir

[GlobalIsel] Use aext in ctlz_zero_undef widenScalar expansion (#181506)

2026-02-18 21:38:17 -08:00

legalize-ctlz.mir

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legalize-ctpop.mir

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legalize-cttz-zero-undef.mir

[GISel] handle CTTZ in computeKnownBits (#181474)

2026-02-15 15:43:05 -08:00

legalize-cttz.mir

[GISel] handle CTTZ in computeKnownBits (#181474)

2026-02-15 15:43:05 -08:00

legalize-divrem.mir

GlobalISel: Adjust insert point when expanding G_[SU]DIVREM

2025-09-25 11:00:53 +00:00

legalize-extract-vector-elt.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-extract.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-extractelement-crash.mir

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legalize-fabs.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fadd.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fcanonicalize.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fceil.mir

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legalize-fcmp-s32.mir

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legalize-fcmp.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fconstant.mir

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legalize-fcopysign.mir

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legalize-fcos.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fdiv.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fexp2.mir

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legalize-fexp.mir

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legalize-ffloor.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-flog2.mir

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legalize-flog10.mir

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legalize-flog.mir

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legalize-fma.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fmad.s16.mir

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legalize-fmad.s32.mir

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legalize-fmad.s64.mir

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legalize-fmaximum.mir

[AMDGPU][GlobalISel] Lower G_FMINIMUM and G_FMAXIMUM (#151122)

2025-10-24 14:48:27 +02:00

legalize-fmaxnum.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fminimum.mir

[AMDGPU][GlobalISel] Lower G_FMINIMUM and G_FMAXIMUM (#151122)

2025-10-24 14:48:27 +02:00

legalize-fminnum.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fmul.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fneg.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fpext.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fpow.mir

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legalize-fpowi.mir

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legalize-fptosi.mir

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legalize-fptoui.mir

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legalize-fptrunc.mir

[GlobalISel] Remove UnsafeFPMath references (#146319)

2025-07-29 12:11:52 +08:00

legalize-freeze.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fshl.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fshr.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fsin.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fsqrt.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-fsub.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-icmp.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-implicit-def-s1025.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-implicit-def.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-insert-vector-elt.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-insert.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-intrinsic-amdgcn-fdiv-fast.mir

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legalize-intrinsic-round.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-intrinsic-trunc.mir

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legalize-inttoptr.mir

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legalize-jump-table.mir

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

legalize-llvm.amdgcn.image.atomic.dim.a16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

legalize-llvm.amdgcn.image.dim.a16.ll

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-llvm.amdgcn.image.load.2d.d16.ll

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-llvm.amdgcn.image.load.2d.ll

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-llvm.amdgcn.image.load.2darraymsaa.ll

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legalize-llvm.amdgcn.image.load.3d.ll

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legalize-llvm.amdgcn.image.sample.a16.ll

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legalize-llvm.amdgcn.image.sample.d.ll

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legalize-llvm.amdgcn.image.sample.g16.a16.ll

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legalize-llvm.amdgcn.image.sample.g16.ll

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legalize-llvm.amdgcn.image.store.2d.d16.ll

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legalize-llvm.amdgcn.s.buffer.load.mir

[AMDGPU] gfx1250 s_buffer_load tests. NFC. (#155295)

2025-08-25 14:32:50 -07:00

legalize-load-constant-32bit.mir

AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)

2025-12-01 18:40:26 -05:00

legalize-load-constant.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-load-flat.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-load-global.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-load-local.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-load-memory-metadata.mir

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legalize-load-private.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-lshr.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-memcpy.mir

[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)

2025-07-22 00:42:23 -07:00

legalize-memcpyinline.mir

[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)

2025-07-22 00:42:23 -07:00

legalize-memmove.mir

[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)

2025-07-22 00:42:23 -07:00

legalize-memset.mir

[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)

2025-07-22 00:42:23 -07:00

legalize-merge-values-build-vector.mir

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legalize-merge-values.mir

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legalize-mul.mir

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legalize-or.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-phi.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-ptr-add.mir

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legalize-ptrmask.mir

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legalize-ptrtoint.mir

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legalize-rotl-rotr.mir

[AArch64][GlobalISel] Add disjoint to the G_OR when lowering G_ROTR/L (#172317)

2026-01-02 09:07:21 +00:00

legalize-sadde.mir

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legalize-saddo.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-saddsat.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-sbfx.mir

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legalize-sdiv.mir

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legalize-select.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-sext-inreg.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-sext.mir

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legalize-sextload-constant-32bit.mir

AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)

2025-12-01 18:40:26 -05:00

legalize-sextload-flat.mir

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legalize-sextload-global.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-sextload-local.mir

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legalize-sextload-private.mir

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legalize-shl.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-shuffle-vector.mir

[Legalizer] Cache extracted element when lowering G_SHUFFLE_VECTOR. (#163893)

2025-10-25 10:26:11 -05:00

legalize-shuffle-vector.s16.mir

[Legalizer] Cache extracted element when lowering G_SHUFFLE_VECTOR. (#163893)

2025-10-25 10:26:11 -05:00

legalize-sitofp.mir

Revert "[AMDGPU] Replace AMDGPUISD::FFBH_I32 with ISD::CTLS" (#178837)

2026-01-29 21:19:15 -08:00

legalize-smax.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-smin.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-smulh.mir

[GlobalISel] Add computeNumSignBits for ASHR (#139503)

2025-07-21 10:23:26 +01:00

legalize-smulo.mir

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legalize-srem.mir

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legalize-sshlsat.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-ssube.mir

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legalize-ssubo.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-ssubsat.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-store-global.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-store.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-strict_fsub.mir

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legalize-sub.mir

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legalize-trap-gfx11.mir

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legalize-trap.mir

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legalize-trunc.mir

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legalize-uadde.mir

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legalize-uaddo.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-uaddsat.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-ubfx.mir

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legalize-udiv.mir

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legalize-uitofp.mir

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legalize-umax.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-umin.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-umulh.mir

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legalize-umulo.mir

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legalize-unmerge-values.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-urem.mir

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legalize-ushlsat.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-usube.mir

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legalize-usubo.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-usubsat.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-vector-args-gfx7.mir

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legalize-vector-args-gfx8-plus.mir

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legalize-xor.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-zext.mir

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

legalize-zextload-constant-32bit.mir

AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)

2025-12-01 18:40:26 -05:00

legalize-zextload-flat.mir

…

legalize-zextload-global.mir

[GISel] Introduce MIFlags::InBounds (#150900)

2025-07-30 13:01:23 +02:00

legalize-zextload-local.mir

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legalize-zextload-private.mir

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llvm.abs.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

llvm.amdgcn.ballot.i32.ll

[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)

2025-10-30 12:32:32 +05:30

llvm.amdgcn.ballot.i64.ll

[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)

2025-10-30 12:32:32 +05:30

llvm.amdgcn.dispatch.ptr.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

llvm.amdgcn.div.fmas.ll

[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)

2026-02-03 11:10:28 +09:00

llvm.amdgcn.div.scale.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.end.cf.i32.ll

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

llvm.amdgcn.end.cf.i64.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for amd_gcn_end_cf (#175118)

2026-01-13 18:18:39 +05:30

llvm.amdgcn.fdot2.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.fmul.legacy.ll

IR: Promote "denormal-fp-math" to a first class attribute (#174293)

2026-02-05 13:31:26 +00:00

llvm.amdgcn.fract.ll

[AMDGPU][GlobalISel] Add frexp_mant/fract intrinsic RegBankLegalize r… (#177512)

2026-01-26 10:23:40 -08:00

llvm.amdgcn.frexp.mant.ll

[AMDGPU][GlobalISel] Add frexp_mant/fract intrinsic RegBankLegalize r… (#177512)

2026-01-26 10:23:40 -08:00

llvm.amdgcn.if.break.i32.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

llvm.amdgcn.if.break.i64.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for S64 amdgcn_if_break (#176496)

2026-01-19 11:25:01 -08:00

llvm.amdgcn.image.atomic.dim.a16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.atomic.dim.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.atomic.dim.mir

[AMDGPU] Support image atomic no return instructions (#150742)

2025-10-29 10:42:15 +08:00

llvm.amdgcn.image.gather4.a16.dim.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.gather4.dim.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.gather4.o.dim.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.getresinfo.a16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.getresinfo.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.load.1d.d16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.load.1d.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.load.2d.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.load.2darraymsaa.a16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.load.2darraymsaa.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.load.3d.a16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.load.3d.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.sample.cd.g16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.sample.g16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.store.2d.d16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.image.store.2d.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

llvm.amdgcn.implicit.ptr.buffer.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

llvm.amdgcn.interp.inreg.ll

[AMDGPU] Add missing comma between export target and first export data (#181641)

2026-02-17 09:24:34 +01:00

llvm.amdgcn.interp.p1.f16.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.intersect_ray.ll

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

llvm.amdgcn.kernarg.segment.ptr.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

llvm.amdgcn.make.buffer.rsrc.ll

[AMDGPU] Add the support for 45-bit buffer resource (#159702)

2025-09-24 11:12:02 -04:00

llvm.amdgcn.mfma.gfx90a.ll

AMDGPU: Select VGPR MFMAs by default (#159493)

2026-01-22 13:41:25 +00:00

llvm.amdgcn.mov.dpp.ll

[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)

2026-02-25 15:24:54 -08:00

llvm.amdgcn.mul24.ll

[AMDGPU][GlobalISel] Add RegBankLegalize mul24 and fmul.legacy (#173123)

2025-12-23 12:35:28 -08:00

llvm.amdgcn.queue.ptr.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

llvm.amdgcn.raw.buffer.atomic.add.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.raw.buffer.atomic.cmpswap.ll

AMDGPU/GlobalISel: RegBankLegalize rules for buffer atomic cmpswap (#180666)

2026-02-10 11:11:38 -08:00

llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

llvm.amdgcn.raw.buffer.atomic.fadd.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

llvm.amdgcn.raw.buffer.atomic.integer-minmax.ll

[AMDGPU][NFC] Fix test by removing debug flag in llvm.amdgcn.raw.buffer.atomic.integer-minmax.ll (#181044)

2026-02-11 18:04:31 -06:00

llvm.amdgcn.raw.buffer.atomic.swap.ll

AMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)

2026-02-09 09:04:17 -08:00

llvm.amdgcn.raw.buffer.load.format.f16.ll

[AMDGPU][GlobalISel] Fix D16 buffer load RegBankLegalize rules (#179982)

2026-02-06 08:01:30 -08:00

llvm.amdgcn.raw.buffer.load.format.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)

2025-09-30 07:56:23 -07:00

llvm.amdgcn.raw.buffer.load.ll

[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#172065)

2025-12-12 14:47:08 -06:00

llvm.amdgcn.raw.buffer.load.tfe.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for TFE buffer loads (#179529)

2026-02-05 13:42:11 -08:00

llvm.amdgcn.raw.buffer.store.format.f16.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

llvm.amdgcn.raw.buffer.store.format.f32.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

llvm.amdgcn.raw.buffer.store.ll

[AMDGPU][GlobalISel] Add buffer store byte/short RegBankLegalize rules (#179367)

2026-02-05 07:18:39 -08:00

llvm.amdgcn.raw.ptr.buffer.atomic.add.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll

AMDGPU/GlobalISel: RegBankLegalize rules for buffer atomic cmpswap (#180666)

2026-02-10 11:11:38 -08:00

llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll

AMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)

2026-02-09 09:04:17 -08:00

llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll

[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)

2026-02-04 09:20:41 -08:00

llvm.amdgcn.raw.ptr.buffer.load.format.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)

2025-09-30 07:56:23 -07:00

llvm.amdgcn.raw.ptr.buffer.load.ll

[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#172065)

2025-12-12 14:47:08 -06:00

llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

llvm.amdgcn.raw.ptr.buffer.store.ll

[AMDGPU][GlobalISel] Add buffer store byte/short RegBankLegalize rules (#179367)

2026-02-05 07:18:39 -08:00

llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll

[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)

2026-02-04 09:20:41 -08:00

llvm.amdgcn.raw.ptr.tbuffer.load.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)

2025-09-30 07:56:23 -07:00

llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll

AMDGPU/GlobalISel: Fix buffer store RegBankLegalize rules (#179994)

2026-02-05 16:20:09 -08:00

llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

llvm.amdgcn.raw.ptr.tbuffer.store.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

llvm.amdgcn.raw.tbuffer.load.f16.ll

[AMDGPU][GlobalISel] Fix D16 buffer load RegBankLegalize rules (#179982)

2026-02-06 08:01:30 -08:00

llvm.amdgcn.raw.tbuffer.load.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)

2025-09-30 07:56:23 -07:00

llvm.amdgcn.raw.tbuffer.store.f16.ll

AMDGPU/GlobalISel: Fix buffer store RegBankLegalize rules (#179994)

2026-02-05 16:20:09 -08:00

llvm.amdgcn.raw.tbuffer.store.i8.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

llvm.amdgcn.raw.tbuffer.store.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

llvm.amdgcn.rsq.clamp.ll

[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180940)

2026-02-11 19:14:54 +00:00

llvm.amdgcn.s.buffer.load.ll

[AMDGPU][GFX1250] Implement offset handling in s.buffer.load (#178389)

2026-01-29 18:00:48 +09:00

llvm.amdgcn.s.setreg.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.s.sleep.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_s_sleep (#178838)

2026-01-30 09:00:14 -08:00

llvm.amdgcn.sbfe.ll

[AMDGPU][GlobalISel] Add ubfe and sbfe intrinsic RegBankLegalize rules (#177276)

2026-01-22 09:01:52 -08:00

llvm.amdgcn.sdot2.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.sdot4.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.sdot8.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.set.inactive.ll

[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)

2026-02-17 18:46:18 -05:00

llvm.amdgcn.softwqm.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.buffer.atomic.add.ll

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07 14:23:41 -07:00

llvm.amdgcn.struct.buffer.atomic.cmpswap.ll

AMDGPU/GlobalISel: RegBankLegalize rules for buffer atomic cmpswap (#180666)

2026-02-10 11:11:38 -08:00

llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

llvm.amdgcn.struct.buffer.atomic.fadd.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

llvm.amdgcn.struct.buffer.atomic.swap.ll

AMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)

2026-02-09 09:04:17 -08:00

llvm.amdgcn.struct.buffer.load.format.f16.ll

[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)

2026-02-04 09:20:41 -08:00

llvm.amdgcn.struct.buffer.load.format.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for TFE buffer loads (#179529)

2026-02-05 13:42:11 -08:00

llvm.amdgcn.struct.buffer.load.ll

[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#172065)

2025-12-12 14:47:08 -06:00

llvm.amdgcn.struct.buffer.load.tfe.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for TFE buffer loads (#179529)

2026-02-05 13:42:11 -08:00

llvm.amdgcn.struct.buffer.store.format.f16.ll

AMDGPU/GlobalISel: Fix buffer store RegBankLegalize rules (#179994)

2026-02-05 16:20:09 -08:00

llvm.amdgcn.struct.buffer.store.format.f32.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

llvm.amdgcn.struct.buffer.store.ll

[AMDGPU][GlobalISel] Add buffer store byte/short RegBankLegalize rules (#179367)

2026-02-05 07:18:39 -08:00

llvm.amdgcn.struct.ptr.buffer.atomic.add.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll

AMDGPU/GlobalISel: RegBankLegalize rules for buffer atomic cmpswap (#180666)

2026-02-10 11:11:38 -08:00

llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll

[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)

2026-02-20 11:30:05 +00:00

llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll

AMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)

2026-02-09 09:04:17 -08:00

llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll

[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)

2026-02-04 09:20:41 -08:00

llvm.amdgcn.struct.ptr.buffer.load.format.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for TFE buffer loads (#179529)

2026-02-05 13:42:11 -08:00

llvm.amdgcn.struct.ptr.buffer.load.ll

[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#172065)

2025-12-12 14:47:08 -06:00

llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll

AMDGPU/GlobalISel: Fix buffer store RegBankLegalize rules (#179994)

2026-02-05 16:20:09 -08:00

llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

llvm.amdgcn.struct.ptr.buffer.store.ll

[AMDGPU][GlobalISel] Add buffer store byte/short RegBankLegalize rules (#179367)

2026-02-05 07:18:39 -08:00

llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll

[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)

2026-02-04 09:20:41 -08:00

llvm.amdgcn.struct.ptr.tbuffer.load.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)

2025-09-30 07:56:23 -07:00

llvm.amdgcn.struct.tbuffer.load.f16.ll

[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)

2026-02-04 09:20:41 -08:00

llvm.amdgcn.struct.tbuffer.load.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)

2025-09-30 07:56:23 -07:00

llvm.amdgcn.sudot4.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.sudot8.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.trig.preop.ll

…

llvm.amdgcn.ubfe.ll

[AMDGPU][GlobalISel] Add ubfe and sbfe intrinsic RegBankLegalize rules (#177276)

2026-01-22 09:01:52 -08:00

llvm.amdgcn.udot2.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.udot4.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.udot8.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.update.dpp.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.wmma_32.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.wmma_64.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.workgroup.id.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

llvm.amdgcn.workitem.id.ll

[AMDGPU] Fix duplicate RUN lines in tests (#182286)

2026-02-19 16:07:20 +00:00

llvm.amdgcn.wqm.demote.ll

[AMDGPU] Add missing comma between export target and first export data (#181641)

2026-02-17 09:24:34 +01:00

llvm.amdgcn.wqm.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.writelane.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.amdgcn.wwm.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_wwm/strict_wwm (#178615)

2026-01-30 08:26:59 -08:00

llvm.atomic.cmpxchg.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ATOMIC_CMPXCHG (#178066)

2026-01-27 09:02:33 -08:00

llvm.memcpy.inline.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

llvm.memcpy.ll

[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)

2025-12-03 11:13:52 +01:00

llvm.memmove.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

llvm.memset.ll

[LowerMemIntrinsics] Optimize memset lowering (#169040)

2026-02-04 13:35:13 +01:00

llvm.powi.ll

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

load-constant32bit.ll

AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)

2025-12-01 18:40:26 -05:00

load-constant.96.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

load-d16.ll

AMDGPU/GlobalISel: Import D16 load patterns and add combines for them (#153178)

2025-09-11 12:02:50 +02:00

load-divergent.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

load-legalize-range-metadata.ll

…

load-local.96.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

load-local.128.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

load-unaligned.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

load-uniform-in-vgpr.ll

AMDGPU/GlobalISel: Combine S16 copy-trunc-readanylane-anyext (#168410)

2025-11-24 15:57:07 +01:00

load-uniform.ll

AMDGPU/GlobalISel: Combine S16 copy-trunc-readanylane-anyext (#168410)

2025-11-24 15:57:07 +01:00

load-zero-and-sign-extending-divergent.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

load-zero-and-sign-extending-uniform-in-vgpr.ll

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)

2025-11-25 11:55:26 +00:00

load-zero-and-sign-extending-uniform.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

localizer-wrong-insert-point.mir

…

localizer.ll

…

lshr.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

mad.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_MAD_U64_U32 (#176060)

2026-01-19 11:21:45 -08:00

madmix-constant-bus-violation.ll

IR: Promote "denormal-fp-math" to a first class attribute (#174293)

2026-02-05 13:31:26 +00:00

madmix-constant-bus-violation.mir

…

memory-legalizer-atomic-fence.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FENCE (#165939)

2025-11-03 09:36:49 -08:00

merge-buffer-stores.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

minmaxabs-i64.ll

[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)

2025-11-21 19:42:17 +05:30

minmaxabs.ll

…

mmra.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FENCE (#165939)

2025-11-03 09:36:49 -08:00

mubuf-global.ll

[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)

2025-12-17 17:53:00 +05:30

mul-known-bits.i64.ll

Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" (#169219)

2025-11-24 09:27:25 +08:00

mul-known-bits.i64.mir

…

mul.ll

[AMDGPU] Update gfx1250 sched model to latest table (#182923)

2026-02-23 13:25:07 -08:00

mul.v2i16.ll

…

no-cse-nonlocal-convergent-instrs.mir

…

no-ctlz-from-umul-to-lshr-in-postlegalizer.ll

…

no-ctlz-from-umul-to-lshr-in-postlegalizer.mir

…

no-legalize-atomic.mir

…

non-entry-alloca.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

or.ll

[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)

2025-10-24 17:25:00 +02:00

orn2.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

postlegalizer-combiner-buildvector-identities.mir

…

postlegalizer-combiner-divrem.mir

…

postlegalizer-combiner-fcanonicalize.mir

…

postlegalizer-combiner-freeze.mir

…

postlegalizer-combiner-merge.mir

[GlobalISel] Insert bitcast instead of register replacement when types don't match. (#177397)

2026-01-30 09:18:31 +00:00

postlegalizer-combiner-reassoc.mir

…

postlegalizer-combiner-sextload-from-sextinreg.mir

…

postlegalizer-combiner-trunc-bitcast-buildvector.mir

…

postlegalizer-combiner-unmerge-undef.mir

…

postlegalizer-combiner-zextload-from-and.mir

[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)

2025-08-20 17:32:29 +02:00

postlegalizercombiner-and.mir

…

postlegalizercombiner-ashr.mir

…

postlegalizercombiner-load-and-mask.mir

…

postlegalizercombiner-lshr.mir

…

postlegalizercombiner-mul.mir

…

postlegalizercombiner-sbfx.mir

[GlobalISel] Add computeNumSignBits for ASHR (#139503)

2025-07-21 10:23:26 +01:00

postlegalizercombiner-select.mir

…

postlegalizercombiner-shl.mir

…

postlegalizercombiner-ubfx.mir

…

prelegalizer-combiner-divrem.mir

…

prelegalizer-combiner-fptrunc_fpext.mir

…

prelegalizer-combiner-redundant-bitcast.mir

…

prelegalizer-combiner-sext_inreg-to-and.mir

…

prelegalizer-combiner-shuffle.mir

[GlobalISel] Make scalar G_SHUFFLE_VECTOR illegal. (#140508)

2025-10-24 08:21:35 +01:00

promote-dependency-on-invariant-result.ll

…

readanylane-combines.ll

[AMDGPU][GlobalISel] Add readanylane combines for merge-like instruct… (#172546)

2025-12-18 08:04:06 -08:00

readanylane-combines.mir

[AMDGPU][GlobalISel] Add readanylane combines for merge-like instruct… (#172546)

2025-12-18 08:04:06 -08:00

regbankcombiner-clamp-fmed3-const.mir

…

regbankcombiner-clamp-minmax-const.mir

…

regbankcombiner-fmed3-minmax-const.mir

…

regbankcombiner-ignore-copies-crash.mir

AMDGPU: Start using RegClassByHwMode for wavesize operands

2025-11-11 15:07:59 -08:00

regbankcombiner-redundant-and.mir

…

regbankcombiner-smed3.mir

…

regbankcombiner-umed3.mir

…

regbankselect-abs.mir

…

regbankselect-add.mir

[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)

2025-10-30 11:45:02 -04:00

regbankselect-add.s16.mir

[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)

2025-10-30 11:45:02 -04:00

regbankselect-add.s32.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-add.v2s16.mir

[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)

2025-10-30 11:45:02 -04:00

regbankselect-amdgcn-exp-compr.mir

…

regbankselect-amdgcn-exp.mir

…

regbankselect-amdgcn-s-buffer-load.mir

…

regbankselect-amdgcn.ballot.i64.mir

…

regbankselect-amdgcn.class.mir

…

regbankselect-amdgcn.cvt.pkrtz.mir

…

regbankselect-amdgcn.div.fmas.mir

…

regbankselect-amdgcn.div.scale.mir

…

regbankselect-amdgcn.ds.append.mir

…

regbankselect-amdgcn.ds.bpermute.mir

…

regbankselect-amdgcn.ds.consume.mir

…

regbankselect-amdgcn.ds.gws.init.mir

…

regbankselect-amdgcn.ds.gws.sema.v.mir

…

regbankselect-amdgcn.ds.ordered.add.mir

…

regbankselect-amdgcn.ds.ordered.swap.mir

…

regbankselect-amdgcn.ds.permute.mir

…

regbankselect-amdgcn.ds.swizzle.mir

…

regbankselect-amdgcn.else.32.mir

…

regbankselect-amdgcn.else.64.mir

…

regbankselect-amdgcn.fcmp.mir

…

regbankselect-amdgcn.fmul.legacy.mir

[AMDGPU][GlobalISel] Add RegBankLegalize mul24 and fmul.legacy (#173123)

2025-12-23 12:35:28 -08:00

regbankselect-amdgcn.groupstaticsize.mir

[AMDGPU][GlobalISel] Add RegBankLegalize rules for groupstaticsize (#178618)

2026-01-29 11:00:44 -08:00

regbankselect-amdgcn.icmp.mir

…

regbankselect-amdgcn.image.load.1d.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

regbankselect-amdgcn.image.sample.1d.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)

2026-02-20 13:34:13 +01:00

regbankselect-amdgcn.interp.mov.mir

…

regbankselect-amdgcn.interp.p1.f16.mir

…

regbankselect-amdgcn.interp.p1.mir

…

regbankselect-amdgcn.interp.p2.f16.mir

…

regbankselect-amdgcn.interp.p2.mir

…

regbankselect-amdgcn.kernarg.segment.ptr.mir

…

regbankselect-amdgcn.kill.mir

…

regbankselect-amdgcn.lds.direct.load.mir

…

regbankselect-amdgcn.lds.param.load.mir

…

regbankselect-amdgcn.live.mask.mir

…

regbankselect-amdgcn.mfma.gfx90a.mir

AMDGPU: Select VGPR MFMAs by default (#159493)

2026-01-22 13:41:25 +00:00

regbankselect-amdgcn.mfma.gfx942.mir

AMDGPU: Select VGPR MFMAs by default (#159493)

2026-01-22 13:41:25 +00:00

regbankselect-amdgcn.mfma.mir

…

regbankselect-amdgcn.ps.live.mir

…

regbankselect-amdgcn.raw.buffer.load.ll

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

regbankselect-amdgcn.raw.ptr.buffer.load.ll

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

regbankselect-amdgcn.readfirstlane.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-amdgcn.readlane.mir

…

regbankselect-amdgcn.s.buffer.load.ll

[AMDGPU][GFX1250] Implement offset handling in s.buffer.load (#178389)

2026-01-29 18:00:48 +09:00

regbankselect-amdgcn.s.buffer.load.mir

…

regbankselect-amdgcn.s.get.waveid.in.workgroup.mir

…

regbankselect-amdgcn.s.getpc.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-amdgcn.s.getreg.mir

…

regbankselect-amdgcn.s.memrealtime.mir

…

regbankselect-amdgcn.s.memtime.mir

…

regbankselect-amdgcn.s.sendmsg.mir

…

regbankselect-amdgcn.s.sendmsghalt.mir

…

regbankselect-amdgcn.struct.buffer.load.ll

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

regbankselect-amdgcn.struct.buffer.store.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

regbankselect-amdgcn.struct.ptr.buffer.load.ll

AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)

2025-07-23 16:47:00 +02:00

regbankselect-amdgcn.struct.ptr.buffer.store.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

2026-01-29 10:39:35 -08:00

regbankselect-amdgcn.update.dpp.mir

…

regbankselect-amdgcn.wqm.demote.mir

…

regbankselect-amdgcn.wqm.mir

…

regbankselect-amdgcn.wqm.vote.mir

…

regbankselect-amdgcn.writelane.mir

…

regbankselect-amdgcn.wwm.mir

[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_wwm/strict_wwm (#178615)

2026-01-30 08:26:59 -08:00

regbankselect-amdgpu-ffbh-u32.mir

…

regbankselect-amdgpu-ffbl-b32.mir

…

regbankselect-amdgpu-wave-address.mir

[AMDGPU][GISel] Add RegBankLegalize support for G_AMDGPU_WAVE_ADDRESS (#167456)

2025-11-11 16:37:42 -08:00

regbankselect-and-s1.mir

AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)

2025-07-23 16:44:53 +02:00

regbankselect-and.mir

…

regbankselect-anyext.mir

AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)

2025-07-23 16:44:53 +02:00

regbankselect-ashr.mir

…

regbankselect-assert-align.mir

[AMDGPU][GISel] Add RegbankLegalize Rules for G_ASSERT_ALIGN (#182353)

2026-02-19 12:30:31 -08:00

regbankselect-assert-sext.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)

2025-10-10 08:48:06 -07:00

regbankselect-assert-zext.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)

2025-10-10 08:48:06 -07:00

regbankselect-atomic-cmpxchg.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ATOMIC_CMPXCHG (#178066)

2026-01-27 09:02:33 -08:00

regbankselect-atomicrmw-add-sub.mir

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

regbankselect-atomicrmw-add.mir

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

regbankselect-atomicrmw-and.mir

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

regbankselect-atomicrmw-fadd.mir

[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)

2026-02-09 15:37:27 +00:00

regbankselect-atomicrmw-fadd.v2f16.mir

[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)

2026-02-09 15:37:27 +00:00

regbankselect-atomicrmw-max.mir

…

regbankselect-atomicrmw-min.mir

…

regbankselect-atomicrmw-minmax-uminmax.mir

[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)

2026-02-10 16:04:05 +05:30

regbankselect-atomicrmw-or.mir

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

regbankselect-atomicrmw-sub.mir

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

regbankselect-atomicrmw-uinc-udec-wrap.mir

[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)

2026-02-10 16:04:05 +05:30

regbankselect-atomicrmw-umax.mir

…

regbankselect-atomicrmw-umin.mir

…

regbankselect-atomicrmw-xchg.mir

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

regbankselect-atomicrmw-xor.mir

[AMDGPU] Add legalization rules for atomic ops (#175253)

2026-01-16 23:01:24 -05:00

regbankselect-bitcast.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-bitreverse.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BITREVERSE (#172101)

2025-12-15 17:45:33 -08:00

regbankselect-block-addr.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BLOCK_ADDR and G_GLOBAL_VALUE (#165340)

2025-11-11 09:31:59 -08:00

regbankselect-brcond.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-bswap.mir

…

regbankselect-build-vector.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-call.ll

[AMDGPU][GISel] Add RegBankLegalize support for G_SI_CALL (#165747)

2026-02-19 09:48:21 -08:00

regbankselect-concat-vector.mir

…

regbankselect-constant.mir

…

regbankselect-copy.mir

AMDGPU: Fixes for regbankselecting copies of i1 physregs to sgprs (#159283)

2025-09-17 19:48:39 +09:00

regbankselect-ctlz-zero-undef.mir

…

regbankselect-ctpop.mir

…

regbankselect-cttz-zero-undef.mir

…

regbankselect-default.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-dyn-stackalloc.mir

…

regbankselect-extract-vector-elt.mir

…

regbankselect-extract.mir

…

regbankselect-fabs.mir

…

regbankselect-fadd.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-fcanonicalize.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FCANONICALIZE (#174662)

2026-01-09 08:51:16 -08:00

regbankselect-fceil.mir

[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)

2026-02-05 16:35:31 +00:00

regbankselect-fcmp.mir

…

regbankselect-fexp2.mir

[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)

2026-02-05 16:35:31 +00:00

regbankselect-ffloor.mir

[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)

2026-02-05 16:35:31 +00:00

regbankselect-flog2.mir

[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)

2026-02-05 16:35:31 +00:00

regbankselect-fma.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)

2025-12-22 09:05:31 -08:00

regbankselect-fmul.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMUL (#167847)

2025-11-17 08:45:49 -08:00

regbankselect-fneg.mir

…

regbankselect-fpext.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPEXT (#171483)

2025-12-10 08:58:27 -08:00

regbankselect-fptosi.mir

[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp (#176300)

2026-02-03 11:45:49 -06:00

regbankselect-fptoui.mir

[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp (#176300)

2026-02-03 11:45:49 -06:00

regbankselect-fptrunc.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPTRUNC (#171723)

2025-12-18 13:16:46 -08:00

regbankselect-frame-index.mir

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

regbankselect-freeze.mir

…

regbankselect-fshr.mir

…

regbankselect-fsqrt.mir

AMDGPU/GlobalISel: Regbanklegalize rules for G_FSQRT (#179817)

2026-02-09 18:24:28 -08:00

regbankselect-fsub.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FSUB (#171244)

2025-12-11 11:55:28 -08:00

regbankselect-icmp.mir

…

regbankselect-icmp.s16.mir

…

regbankselect-illegal-copy.mir

…

regbankselect-implicit-def.mir

…

regbankselect-insert-vector-elt.mir

…

regbankselect-insert.mir

…

regbankselect-intrinsic-roundeven.mir

[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)

2026-02-05 16:35:31 +00:00

regbankselect-intrinsic-trunc.mir

[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)

2026-02-05 16:35:31 +00:00

regbankselect-inttoptr.mir

…

regbankselect-load.mir

AMDGPU: Use ConstantPool as source value for DAG lowered kernarg loads (#168917)

2025-12-02 15:48:02 +00:00

regbankselect-lshr.mir

…

regbankselect-mad_64_32.mir

…

regbankselect-merge-values.mir

…

regbankselect-mui-regbanklegalize.mir

…

regbankselect-mui-regbankselect.mir

…

regbankselect-mui-salu-float.ll

…

regbankselect-mui-salu-float.mir

…

regbankselect-mui.ll

[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)

2026-02-11 09:06:28 -08:00

regbankselect-mui.mir

…

regbankselect-mul.mir

Reland "[AMDGPU][GlobalISel] Add RegBankLegalize support for G_MUL (#… (#177481)

2026-01-22 14:59:52 -08:00

regbankselect-or.mir

…

regbankselect-phi-s1.mir

…

regbankselect-phi.mir

…

regbankselect-pseudo-scalar-transcendental.mir

…

regbankselect-ptr-add.mir

AMDGPU/GlobalISel: Add regbanklegalize rules for ptr-add (#153175)

2025-08-13 15:49:48 +02:00

regbankselect-ptrmask.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_PTRMASK (#174889)

2026-01-09 08:51:51 -08:00

regbankselect-ptrtoint.mir

…

regbankselect-reg-sequence.mir

…

regbankselect-sadde.mir

[AMDGPU][GlobalISel] Add G_SADDE/SSUBE RegBankLegalize rule (#179603)

2026-02-04 09:41:27 -08:00

regbankselect-salu-float.mir

…

regbankselect-sbfx.mir

…

regbankselect-select.mir

…

regbankselect-sext-inreg.mir

…

regbankselect-sext.mir

[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)

2025-10-30 11:45:02 -04:00

regbankselect-sextload.mir

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

regbankselect-shl.mir

…

regbankselect-sitofp.mir

[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp (#176300)

2026-02-03 11:45:49 -06:00

regbankselect-smax.mir

[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)

2025-10-10 14:34:15 +02:00

regbankselect-smin.mir

[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)

2025-10-10 14:34:15 +02:00

regbankselect-smulh.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_UMULH, G_SMULH (#174555)

2026-01-08 13:57:57 -08:00

regbankselect-split-scalar-load-metadata.mir

AMDGPU: Use ConstantPool as source value for DAG lowered kernarg loads (#168917)

2025-12-02 15:48:02 +00:00

regbankselect-ssube.mir

[AMDGPU][GlobalISel] Add G_SADDE/SSUBE RegBankLegalize rule (#179603)

2026-02-04 09:41:27 -08:00

regbankselect-sub.mir

[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)

2025-10-30 11:45:02 -04:00

regbankselect-trunc.mir

[AMDGPU][GlobalISel] Fix G_TRUNC S16 to VCC for pre-GFX8 targets (#176254)

2026-01-16 08:00:42 -08:00

regbankselect-uadde.mir

…

regbankselect-uaddo.mir

…

regbankselect-ubfx.mir

…

regbankselect-uitofp.mir

[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp (#176300)

2026-02-03 11:45:49 -06:00

regbankselect-umax.mir

[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)

2025-10-10 14:34:15 +02:00

regbankselect-umin.mir

[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)

2025-10-10 14:34:15 +02:00

regbankselect-umulh.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_UMULH, G_SMULH (#174555)

2026-01-08 13:57:57 -08:00

regbankselect-uniform-load-noclobber.mir

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

regbankselect-unmerge-values.mir

…

regbankselect-usube.mir

…

regbankselect-usubo.mir

…

regbankselect-waterfall-agpr.mir

…

regbankselect-waterfall-call.mir

[AMDGPU][GISel] Add RegBankLegalize support for G_SI_CALL (#165747)

2026-02-19 09:48:21 -08:00

regbankselect-whole-wave-functions.mir

[AMDGPU] ISel & PEI for whole wave functions (#145858)

2025-07-21 10:39:09 +02:00

regbankselect-widen-scalar-loads.mir

AMDGPU: Use ConstantPool as source value for DAG lowered kernarg loads (#168917)

2025-12-02 15:48:02 +00:00

regbankselect-xor.mir

…

regbankselect-zext.mir

[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)

2025-10-30 11:45:02 -04:00

regbankselect-zextload.mir

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

regbankselect.mir

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

saddsat.ll

[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)

2026-02-11 09:06:28 -08:00

sbfx.ll

…

sdiv.i32.ll

[GlobaISel] Allow expanding of sdiv -> mul by constant (#146504)

2025-07-14 15:01:12 +01:00

sdiv.i64.ll

AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)

2025-11-11 13:50:57 -08:00

sdivrem.ll

AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)

2025-11-11 13:50:57 -08:00

select-to-fmin-fmax.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

selected-inst-flags.mir

…

sext_inreg.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

shader-epilogs.ll

[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)

2025-07-23 13:42:46 -04:00

shl-ext-reduce.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

shl.ll

[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)

2026-01-30 15:13:33 +00:00

shufflevector-pointer-crash.mir

[GlobalISel] Make scalar G_SHUFFLE_VECTOR illegal. (#140508)

2025-10-24 08:21:35 +01:00

shufflevector.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

smed3.ll

[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)

2025-10-10 14:34:15 +02:00

smrd.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

smul.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_S_MUL_* (#176842)

2026-01-21 08:58:35 -08:00

srem.i32.ll

[GlobalISel] Allow expansion of srem by constant in prelegalizer (#148845)

2025-07-17 14:43:58 +01:00

srem.i64.ll

AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)

2025-11-11 13:50:57 -08:00

ssubsat.ll

[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)

2026-02-11 09:06:28 -08:00

store-divergent-addr.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

store-local.96.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

store-local.128.ll

Reland: CodeGen: Record MMOs in finalizeBundle (#166689)

2025-11-06 07:34:36 -08:00

store-uniform-addr.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

store-weird-size.ll

[AMDGPU] Narrow only on store to pow of 2 mem location (#150093)

2025-08-19 00:04:27 +09:00

strict_fma.f16.ll

Adding support for G_STRICT_FMA in new reg bank select (#170330)

2026-02-06 15:43:37 +05:30

strict_fma.f32.ll

Adding support for G_STRICT_FMA in new reg bank select (#170330)

2026-02-06 15:43:37 +05:30

strict_fma.f64.ll

Adding support for G_STRICT_FMA in new reg bank select (#170330)

2026-02-06 15:43:37 +05:30

sub.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

sub.v2i16.ll

…

subo.ll

[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)

2026-02-11 09:06:28 -08:00

trunc.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

twoaddr-extract-dyn-v7f64.mir

…

uaddsat.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)

2026-02-02 17:55:42 +01:00

ubfx.ll

…

udiv.i32.ll

…

udiv.i64.ll

[GlobalISel] add KnownBits tracking for G_UMULH and G_SMULH (#158445)

2025-10-10 18:42:14 +09:00

udivrem.ll

AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)

2025-11-11 13:50:57 -08:00

umed3.ll

[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)

2025-10-10 14:34:15 +02:00

unmerge-sgpr-s16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)

2026-02-02 17:55:42 +01:00

unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize (#179441)

2026-02-04 10:20:30 +00:00

unsupported-load.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

unsupported-ptr-add.ll

…

urem.i32.ll

…

urem.i64.ll

[GlobalISel] add KnownBits tracking for G_UMULH and G_SMULH (#158445)

2025-10-10 18:42:14 +09:00

usubsat.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)

2026-02-02 17:55:42 +01:00

v_bfe_i32.ll

AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)

2025-08-12 15:03:31 +02:00

vni8-across-blocks.ll

Reland: CodeGen: Record MMOs in finalizeBundle (#166689)

2025-11-06 07:34:36 -08:00

widen-i8-i16-scalar-loads.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00

wmma-gfx12-w32-f16-f32-matrix-modifiers.ll

[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)

2026-02-18 19:17:48 +01:00

wmma-gfx12-w32-imm.ll

[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)

2026-02-18 19:17:48 +01:00

wmma-gfx12-w32-iu-modifiers.ll

[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)

2026-02-18 19:17:48 +01:00

wmma-gfx12-w32-swmmac-index_key.ll

[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)

2026-02-18 19:17:48 +01:00

wmma-gfx12-w32.ll

[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)

2026-02-18 19:17:48 +01:00

wmma-gfx12-w64-f16-f32-matrix-modifiers.ll

[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)

2026-02-18 19:17:48 +01:00

wmma-gfx12-w64-imm.ll

[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)

2026-02-18 19:17:48 +01:00

wmma-gfx12-w64-iu-modifiers.ll

[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)

2026-02-18 19:17:48 +01:00

wmma-gfx12-w64-swmmac-index_key.ll

[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)

2026-02-18 19:17:48 +01:00

wmma-gfx12-w64.ll

[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)

2026-02-18 19:17:48 +01:00

xnor.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)

2026-01-22 17:24:29 +01:00

xor.ll

…

zextload.ll

AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)

2025-09-11 11:26:20 +02:00