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llvm-project/llvm/lib/Target/AMDGPU
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Shilei Tian 02d34a76f7
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297) 
We are getting pretty close to use `GET_SUBTARGETINFO_MACRO` in the
header with this cleanup.
2026-01-22 09:07:15 -05:00
..
AsmParser
[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)
2026-01-20 19:14:59 -05:00
Disassembler
[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)
2026-01-20 19:14:59 -05:00
MCA
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
MCTargetDesc
[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)
2026-01-20 19:14:59 -05:00
TargetInfo
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
Utils
[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)
2026-01-20 19:14:59 -05:00
AMDGPU.h
[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)
2025-12-08 20:38:00 +05:30
AMDGPU.td
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
AMDGPUAliasAnalysis.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
AMDGPUAnnotateUniformValues.cpp
…
AMDGPUArgumentUsageInfo.cpp
[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)
2025-12-08 20:38:00 +05:30
AMDGPUArgumentUsageInfo.h
[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)
2025-12-08 20:38:00 +05:30
AMDGPUAsanInstrumentation.cpp
[llvm] Use ConstantInt::getAllOnesValue()
2025-12-09 12:02:39 +01:00
AMDGPUAsanInstrumentation.h
…
AMDGPUAsmPrinter.cpp
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
AMDGPUAsmPrinter.h
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
AMDGPUAtomicOptimizer.cpp
[llvm] Use ConstantInt::getAllOnesValue()
2025-12-09 12:02:39 +01:00
AMDGPUAttributes.def
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
AMDGPUAttributor.cpp
Reapply "AMDGPU: Do not infer implicit inputs for !nocallback intrinsics" (#176081)
2026-01-15 09:08:27 -06:00
AMDGPUBarrierLatency.cpp
[AMDGPU] Schedule independent instructions between s_barrier_signal and s_barrier_wait (#172057)
2025-12-16 11:48:50 +05:30
AMDGPUBarrierLatency.h
[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutation (#168500)
2025-11-19 17:49:14 +09:00
AMDGPUCallingConv.td
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
AMDGPUCallLowering.cpp
AMDGPU: Use ConstantPool as source value for DAG lowered kernarg loads (#168917)
2025-12-02 15:48:02 +00:00
AMDGPUCallLowering.h
[AMDGPU] ISel & PEI for whole wave functions (#145858)
2025-07-21 10:39:09 +02:00
AMDGPUCodeGenPrepare.cpp
[AMDGPU]: Rewrite mbcnt_lo/mbcnt_hi to work item ID where applicable (#160496)
2026-01-12 20:18:07 +01:00
AMDGPUCombine.td
[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)
2025-10-24 17:25:00 +02:00
AMDGPUCombinerHelper.cpp
[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)
2025-08-20 17:32:29 +02:00
AMDGPUCombinerHelper.h
[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)
2025-08-20 17:32:29 +02:00
AMDGPUCtorDtorLowering.cpp
…
AMDGPUCtorDtorLowering.h
…
AMDGPUExportClustering.cpp
[AMDGPU] Remove unused includes (NFC) (#141376)
2025-05-24 14:48:46 -07:00
AMDGPUExportClustering.h
…
AMDGPUExportKernelRuntimeHandles.cpp
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUExportKernelRuntimeHandles.h
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUFeatures.td
[NFCI][AMDGPU] Convert more SubtargetFeatures to use AMDGPUSubtargetFeature and X-macros (#177256)
2026-01-21 18:03:32 -05:00
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
…
AMDGPUGISel.td
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
2025-12-05 12:37:33 +00:00
AMDGPUGlobalISelDivergenceLowering.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUGlobalISelUtils.cpp
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
AMDGPUGlobalISelUtils.h
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
AMDGPUHSAMetadataStreamer.cpp
[AMDGPU] Add the support for .cluster_dims code object metadata (#158721)
2025-09-15 16:13:07 -04:00
AMDGPUHSAMetadataStreamer.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
AMDGPUIGroupLP.cpp
[llvm][AMDGPU] Fix signed/unsigned comparison warning in 32-bit builds (#172623)
2025-12-18 11:11:09 +00:00
AMDGPUIGroupLP.h
Remove unused <vector> inclusion (#166997)
2025-11-08 20:42:00 +00:00
AMDGPUImageIntrinsicOptimizer.cpp
[AMDGPU] Change placeholder from undef to poison (#130853)
2025-03-12 12:52:38 +00:00
AMDGPUInsertDelayAlu.cpp
[AMDGPU] Do not use s_delay_alu instskip to skip s_set_vgpr_msb (#175925)
2026-01-20 10:59:55 +00:00
AMDGPUInstCombineIntrinsic.cpp
[AMDGPU] tensor_{load_to/store_from}_lds => ..._d2 simplification (#171540)
2025-12-15 08:11:03 -08:00
AMDGPUInstrInfo.cpp
AMDGPU: Fix treating unknown mem operands as uniform (#170309)
2025-12-02 16:19:46 +00:00
AMDGPUInstrInfo.h
[AMDGPU] Support image atomic no return instructions (#150742)
2025-10-29 10:42:15 +08:00
AMDGPUInstrInfo.td
[AMDGPU] TableGen-erate SDNode descriptions (#168248)
2025-11-17 00:10:07 +00:00
AMDGPUInstructions.td
AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)
2025-12-09 23:13:33 +00:00
AMDGPUInstructionSelector.cpp
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
AMDGPUInstructionSelector.h
Reland "[AMDGPU] Add new llvm.amdgcn.wave.shuffle intrinsic (#167372)" (#174614)
2026-01-06 15:02:08 -05:00
AMDGPUISelDAGToDAG.cpp
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
AMDGPUISelDAGToDAG.h
[AMDGPU] TableGen-erate SDNode descriptions (#168248)
2025-11-17 00:10:07 +00:00
AMDGPUISelLowering.cpp
AMDGPU: Teach lowering that sqrt never returns subnormal (#174838)
2026-01-08 12:05:29 +01:00
AMDGPUISelLowering.h
[TargetLowering] Change the softPromoteHalfType default to true (#175149)
2026-01-11 12:48:26 +01:00
AMDGPULaneMaskUtils.h
[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)
2025-09-16 03:22:14 +00:00
AMDGPULateCodeGenPrepare.cpp
[AMDGPU] LiveRegOptimizer: consider i8/i16 binops on SDWA (#155800)
2025-12-15 12:04:33 -05:00
AMDGPULegalizerInfo.cpp
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
AMDGPULegalizerInfo.h
AMDGPU/GlobalISel: Fix broken exp10 lowering for f16 (#170708)
2025-12-08 10:35:40 +01:00
AMDGPULibCalls.cpp
Use AllocaInst::getAllocationSize instead of manual size calculations (#176486)
2026-01-19 09:55:52 -05:00
AMDGPULibFunc.cpp
[AMDGPU] Provide default value in get intrinsic param type (#122448)
2025-01-10 15:29:42 +01:00
AMDGPULibFunc.h
…
AMDGPULowerBufferFatPointers.cpp
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
2025-12-05 12:37:33 +00:00
AMDGPULowerExecSync.cpp
[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)
2025-11-25 15:43:18 +00:00
AMDGPULowerIntrinsics.cpp
[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)
2025-09-16 14:49:48 -07:00
AMDGPULowerKernelArguments.cpp
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
AMDGPULowerKernelAttributes.cpp
[AMDGPU] Fix AMDGPULowerKernelAttributes not invalidating analysis (#175256)
2026-01-09 23:03:15 +00:00
AMDGPULowerModuleLDSPass.cpp
[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)
2025-11-25 15:43:18 +00:00
AMDGPULowerVGPREncoding.cpp
[AMDGPU] Reduce number of emitted S_SET_VGPR_MSB instructions (#176502)
2026-01-20 10:47:24 +01:00
AMDGPULowerVGPREncoding.h
[AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (#156971)
2025-09-05 00:07:47 -07:00
AMDGPUMachineFunction.cpp
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUMachineFunction.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUMachineModuleInfo.cpp
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
AMDGPUMachineModuleInfo.h
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
AMDGPUMarkLastScratchLoad.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUMCInstLower.cpp
AMDGPU: Avoid crashing on statepoint-like pseudoinstructions (#170657)
2025-12-29 19:08:08 +01:00
AMDGPUMCInstLower.h
[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)
2025-09-24 11:27:26 -04:00
AMDGPUMCResourceInfo.cpp
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUMCResourceInfo.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPUMemoryUtils.cpp
[AMDGPU] Add s_wakeup_barrier instruction for gfx1250 (#170501)
2025-12-10 09:45:13 +01:00
AMDGPUMemoryUtils.h
[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)
2025-11-25 15:43:18 +00:00
AMDGPUMIRFormatter.cpp
…
AMDGPUMIRFormatter.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
AMDGPUPassRegistry.def
[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)
2025-12-08 20:38:00 +05:30
AMDGPUPerfHintAnalysis.cpp
[llvm] Remove unused includes of SmallSet.h (NFC) (#154893)
2025-08-22 10:33:46 -07:00
AMDGPUPerfHintAnalysis.h
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
AMDGPUPostLegalizerCombiner.cpp
Fix typos and spelling errors across codebase (#156270)
2026-01-13 11:52:46 -05:00
AMDGPUPredicateControl.td
…
AMDGPUPreLegalizerCombiner.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
AMDGPUPreloadKernArgProlog.cpp
[AMDGPU] Enable kernarg preload on gfx1250 (#153686)
2025-08-14 16:29:53 -07:00
AMDGPUPreloadKernArgProlog.h
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
2025-01-10 11:39:02 -08:00
AMDGPUPreloadKernelArguments.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
AMDGPUPrepareAGPRAlloc.cpp
AMDGPU: Start using AV_MOV_B64_IMM_PSEUDO (#154500)
2025-08-22 13:59:36 +09:00
AMDGPUPrepareAGPRAlloc.h
AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)
2025-07-18 17:15:38 +09:00
AMDGPUPrintfRuntimeBinding.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
AMDGPUPromoteAlloca.cpp
[AMDGPU] Fix a potential use-after-erase in AMDGPUPromoteAlloca pass (#174529)
2026-01-08 11:44:16 -05:00
AMDGPUPromoteKernelArguments.cpp
…
AMDGPUPTNote.h
…
AMDGPURegBankCombiner.cpp
AMDGPU/GlobalISel: Import D16 load patterns and add combines for them (#153178)
2025-09-11 12:02:50 +02:00
AMDGPURegBankLegalize.cpp
[AMDGPU][GlobalISel] Add readanylane combines for merge-like instruct… (#172546)
2025-12-18 08:04:06 -08:00
AMDGPURegBankLegalizeHelper.cpp
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_S_MUL_* (#176842)
2026-01-21 08:58:35 -08:00
AMDGPURegBankLegalizeHelper.h
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_MAD_U64_U32 (#176060)
2026-01-19 11:21:45 -08:00
AMDGPURegBankLegalizeRules.cpp
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_S_MUL_* (#176842)
2026-01-21 08:58:35 -08:00
AMDGPURegBankLegalizeRules.h
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_S_MUL_* (#176842)
2026-01-21 08:58:35 -08:00
AMDGPURegBankSelect.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
AMDGPURegisterBankInfo.cpp
Reland "[AMDGPU] Add new llvm.amdgcn.wave.shuffle intrinsic (#167372)" (#174614)
2026-01-06 15:02:08 -05:00
AMDGPURegisterBankInfo.h
…
AMDGPURegisterBanks.td
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
AMDGPURemoveIncompatibleFunctions.cpp
[AMDGPU] Remove wave64 functions (#153690)
2025-08-14 15:54:33 -07:00
AMDGPURemoveIncompatibleFunctions.h
[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)
2025-01-13 10:11:40 +05:30
AMDGPUReserveWWMRegs.cpp
[AMDGPU] Remove unused includes (NFC) (#141376)
2025-05-24 14:48:46 -07:00
AMDGPUReserveWWMRegs.h
[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM (#123722)
2025-03-10 17:36:35 +05:30
AMDGPUResourceUsageAnalysis.cpp
AMDGPU: Avoid crashing on statepoint-like pseudoinstructions (#170657)
2025-12-29 19:08:08 +01:00
AMDGPUResourceUsageAnalysis.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
AMDGPURewriteAGPRCopyMFMA.cpp
[AMDGPU] Fix AGPR_32 reg assign for mfma scale ops (#168964)
2025-12-02 13:41:16 -05:00
AMDGPURewriteOutArguments.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
AMDGPURewriteUndefForPHI.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUSearchableTables.td
AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)
2025-12-09 23:13:33 +00:00
AMDGPUSelectionDAGInfo.cpp
[AMDGPU] TableGen-erate SDNode descriptions (#168248)
2025-11-17 00:10:07 +00:00
AMDGPUSelectionDAGInfo.h
[AMDGPU] TableGen-erate SDNode descriptions (#168248)
2025-11-17 00:10:07 +00:00
AMDGPUSetWavePriority.cpp
[llvm] Replace SmallSet with SmallPtrSet (NFC) (#154068)
2025-08-18 07:01:29 -07:00
AMDGPUSplitModule.cpp
[NFC] Implicit container copy cleanup (#174702)
2026-01-14 11:16:32 +01:00
AMDGPUSplitModule.h
…
AMDGPUSubtarget.cpp
[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)
2025-11-25 15:43:18 +00:00
AMDGPUSubtarget.h
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
AMDGPUSwLowerLDS.cpp
Fix typos and spelling errors across codebase (#156270)
2026-01-13 11:52:46 -05:00
AMDGPUTargetMachine.cpp
[AMDGPU][NPM] Enable "AMDGPURewriteAGPRCopyMFMAPass" (#173487)
2026-01-21 17:57:34 +01:00
AMDGPUTargetMachine.h
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[NFCI][AMDGPU] Convert more SubtargetFeatures to use AMDGPUSubtargetFeature and X-macros (#177256)
2026-01-21 18:03:32 -05:00
AMDGPUTargetTransformInfo.h
[NFC][TTI] Introduce getInstructionUniformity API for uniformity analysis (#168903)
2025-12-10 23:14:34 +05:30
AMDGPUUniformIntrinsicCombine.cpp
[AMDGPU] Add optimization for llvm.amdgcn.wave.shuffle in uniform cases (#174795)
2026-01-14 17:49:42 +00:00
AMDGPUUnifyDivergentExitNodes.cpp
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
AMDGPUUnifyDivergentExitNodes.h
…
AMDGPUWaitSGPRHazards.cpp
[AMDGPU][NewPM] Consistently preserve IR analyses in MF passes
2025-12-28 13:12:10 -08:00
AMDGPUWaitSGPRHazards.h
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
AMDKernelCodeT.h
…
BUFInstructions.td
AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)
2025-12-09 23:13:33 +00:00
CaymanInstructions.td
…
CMakeLists.txt
[AMDGPU] Eliminate InstCombineTables.td. NFC. (#170857)
2025-12-06 07:27:45 +00:00
DSDIRInstructions.td
AMDGPU: Remove LDS-direct(param)-loads and VINTERP ops from gfx1250 support (#145631)
2025-06-24 22:44:35 -07:00
DSInstructions.td
AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)
2025-12-09 23:13:33 +00:00
EvergreenInstructions.td
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
EXPInstructions.td
AMDGPU: Remove export and related instructions from gfx1250 support (#145624)
2025-06-24 19:59:26 -07:00
FLATInstructions.td
[AMDGPU] Allow predicates for alias in VFLAT_Real_AllAddr_gfx1250 (#176987)
2026-01-20 12:42:40 -08:00
GCNCreateVOPD.cpp
[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)
2025-07-10 14:15:01 -07:00
GCNDPPCombine.cpp
Reland "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176277)
2026-01-16 13:05:06 -08:00
GCNDPPCombine.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
GCNHazardRecognizer.cpp
Reland "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176277)
2026-01-16 13:05:06 -08:00
GCNHazardRecognizer.h
[AMDGPU] Refactor hazard recognizer for VALU-pipeline hazards. NFCI. (#168801)
2025-12-01 10:59:52 -08:00
GCNILPSched.cpp
…
GCNIterativeScheduler.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
GCNIterativeScheduler.h
[AMDGPU] Teach iterative schedulers about IGLP (#134953)
2025-04-11 15:34:49 -07:00
GCNMinRegStrategy.cpp
…
GCNNSAReassign.cpp
[llvm] Use conventional enum declarations (NFC) (#166318)
2025-11-04 07:12:53 -08:00
GCNNSAReassign.h
[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager (#125034)
2025-02-18 11:13:31 +05:30
GCNPreRALongBranchReg.cpp
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
GCNPreRALongBranchReg.h
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
GCNPreRAOptimizations.cpp
[AMDGPU] Use subclass query for VGPR_16 RA hinting. NFCI (#177017)
2026-01-20 21:09:36 -08:00
GCNPreRAOptimizations.h
[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)
2025-02-11 11:09:38 +05:30
GCNProcessors.td
[AMDGPU] Add gfx1251 subtarget (#159430)
2025-09-17 13:02:02 -07:00
GCNRegPressure.cpp
[AMDGPU] Rematerialize VGPR candidates when SGPR spills results in VGPR Excess (#168079)
2026-01-16 09:08:55 +01:00
GCNRegPressure.h
[AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR (#170335)
2026-01-22 12:22:39 +01:00
GCNRewritePartialRegUses.cpp
[AMDGPU] Simplify GCNRewritePartialRegUses pass. (#135199)
2025-04-11 15:45:24 +02:00
GCNRewritePartialRegUses.h
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
2025-02-12 11:21:40 +05:30
GCNSchedStrategy.cpp
[AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR (#170335)
2026-01-22 12:22:39 +01:00
GCNSchedStrategy.h
[AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR (#170335)
2026-01-22 12:22:39 +01:00
GCNSubtarget.cpp
[AMDGPU] Latency calculation must be independent of meta insts (#177052)
2026-01-21 12:19:55 -06:00
GCNSubtarget.h
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
GCNVOPDUtils.cpp
[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)
2025-07-10 14:15:01 -07:00
GCNVOPDUtils.h
[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)
2025-07-10 14:15:01 -07:00
MIMGInstructions.td
[AMDGPU] Set VADDR4 field to NULL for tensor ops for gfx1250 (#165917)
2025-10-31 16:48:20 -07:00
R600.h
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
R600.td
CodeGen: Make all targets override pseudos with pointers (#159881)
2025-11-26 14:57:14 +00:00
R600AsmPrinter.cpp
…
R600AsmPrinter.h
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
…
R600Defines.h
…
R600EmitClauseMarkers.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
R600ExpandSpecialInstrs.cpp
[CodeGen] Remove FinalizeMachineBundles pass (#149806)
2025-07-23 11:36:49 +01:00
R600FrameLowering.cpp
…
R600FrameLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
R600InstrInfo.h
[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)
2025-02-24 09:55:34 -08:00
R600InstrInfo.td
…
R600Instructions.td
[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)
2025-08-30 04:44:20 +00:00
R600ISelDAGToDAG.cpp
[AMDGPU] Remove unused includes (NFC) (#141376)
2025-05-24 14:48:46 -07:00
R600ISelLowering.cpp
[NFC][TargetLowering] Make shouldExpandAtomicRMWInIR and shouldExpandAtomicCmpXchgInIR take a const Instruction pointer (#176073)
2026-01-15 14:22:57 -08:00
R600ISelLowering.h
[NFC][TargetLowering] Make shouldExpandAtomicRMWInIR and shouldExpandAtomicCmpXchgInIR take a const Instruction pointer (#176073)
2026-01-15 14:22:57 -08:00
R600MachineCFGStructurizer.cpp
Reland "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176277)
2026-01-16 13:05:06 -08:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600MCInstLower.cpp
[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)
2025-11-14 11:00:57 +00:00
R600OpenCLImageTypeLoweringPass.cpp
…
R600OptimizeVectorRegisters.cpp
[NFC][AMDGPU] Declare variables initialized with getDebugLoc as const ref (#174434)
2026-01-05 12:37:47 -06:00
R600Packetizer.cpp
[TableGen] Add mapping from processor ID to resource index for packetizer (#158182)
2025-09-17 09:12:37 +08:00
R600Processors.td
…
R600RegisterInfo.cpp
…
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
…
R600Subtarget.h
[NFCI][AMDGPU] Convert more SubtargetFeatures to use AMDGPUSubtargetFeature and X-macros (#177256)
2026-01-21 18:03:32 -05:00
R600TargetMachine.cpp
[Codegen][NewPM] Explicitly Nest Passes in CodegenPassBuilder (#169867)
2025-12-16 15:42:28 -08:00
R600TargetMachine.h
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
R600TargetTransformInfo.cpp
[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)
2025-05-01 15:55:08 +01:00
R600TargetTransformInfo.h
[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)
2025-05-01 15:55:08 +01:00
R700Instructions.td
…
SIAnnotateControlFlow.cpp
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
SIDefines.h
[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)
2026-01-20 19:14:59 -05:00
SIFixSGPRCopies.cpp
[NFC] Implicit container copy cleanup (#174702)
2026-01-14 11:16:32 +01:00
SIFixSGPRCopies.h
…
SIFixVGPRCopies.cpp
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)
2025-01-21 15:27:46 +05:30
SIFixVGPRCopies.h
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)
2025-01-21 15:27:46 +05:30
SIFoldOperands.cpp
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
SIFoldOperands.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SIFormMemoryClauses.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
SIFormMemoryClauses.h
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
SIFrameLowering.cpp
[NFCI][AMDGPU] Use X-macro to reduce boilerplate in GCNSubtarget.h (#176844)
2026-01-21 15:29:09 -05:00
SIFrameLowering.h
[CodeGen] Replace (Min,Max)CSFrameIndex with flag on frame object [NFCI] (#170905)
2025-12-06 14:00:55 -08:00
SIInsertHardClauses.cpp
[AMDGPU] Adjust hard clause rules for gfx1250 (#152592)
2025-08-07 14:59:31 -07:00
SIInsertWaitcnts.cpp
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
SIInstrFormats.td
CodeGen: Add RegisterClass by HwMode (#158269)
2025-09-19 20:08:51 +09:00
SIInstrInfo.cpp
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
SIInstrInfo.h
[AMDGPU] NFC: Add a comment (#176435)
2026-01-16 15:49:14 -08:00
SIInstrInfo.td
AMDGPU: Add pattern for copysign of 0 (#172699)
2025-12-18 11:34:24 +01:00
SIInstructions.td
AMDGPU: Enable selection of strict_fp16_to_fp (#175834)
2026-01-13 21:40:51 +00:00
SIISelLowering.cpp
[NFCI][AMDGPU] Remove more redundant code from GCNSubtarget.h (#177297)
2026-01-22 09:07:15 -05:00
SIISelLowering.h
[NFC][TargetLowering] Make shouldExpandAtomicRMWInIR and shouldExpandAtomicCmpXchgInIR take a const Instruction pointer (#176073)
2026-01-15 14:22:57 -08:00
SILateBranchLowering.cpp
[NFC][AMDGPU] Declare variables initialized with getDebugLoc as const ref (#174434)
2026-01-05 12:37:47 -06:00
SILoadStoreOptimizer.cpp
[NFC][AMDGPU] Declare variables initialized with getDebugLoc as const ref (#174434)
2026-01-05 12:37:47 -06:00
SILoadStoreOptimizer.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SILowerControlFlow.cpp
Make MachineBlockFrequencyInfo a required pass for the MachineScheduler pass. (#176172)
2026-01-15 20:26:51 +00:00
SILowerControlFlow.h
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
SILowerI1Copies.cpp
[NFC][AMDGPU] Declare variables initialized with getDebugLoc as const ref (#174434)
2026-01-05 12:37:47 -06:00
SILowerI1Copies.h
AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)
2025-03-12 12:09:37 +01:00
SILowerSGPRSpills.cpp
CodeGen: Remove TRI arguments from stack load/store hooks (#158240)
2025-11-10 16:24:39 -08:00
SILowerSGPRSpills.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SILowerWWMCopies.cpp
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)
2025-01-22 14:54:01 +05:30
SILowerWWMCopies.h
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)
2025-01-22 14:54:01 +05:30
SIMachineFunctionInfo.cpp
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
SIMachineFunctionInfo.h
[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)
2025-11-22 14:03:14 -08:00
SIMachineScheduler.cpp
[CodeGen] Use VirtRegOrUnit where appropriate (NFCI) (#167730)
2025-11-13 10:26:58 +00:00
SIMachineScheduler.h
[CodeGen] Use VirtRegOrUnit where appropriate (NFCI) (#167730)
2025-11-13 10:26:58 +00:00
SIMemoryLegalizer.cpp
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
SIModeRegister.cpp
[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)
2025-03-04 10:51:03 +05:30
SIModeRegisterDefaults.cpp
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SIModeRegisterDefaults.h
…
SIOptimizeExecMasking.cpp
[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)
2025-09-16 03:22:14 +00:00
SIOptimizeExecMasking.h
[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)
2025-01-20 16:34:01 +05:30
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] SIOptimizeExecMaskingPreRA: Fix crash on exec copy fold into INLINEASM (#172481)
2025-12-16 17:55:05 +01:00
SIOptimizeExecMaskingPreRA.h
[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)
2025-02-20 17:35:56 +05:30
SIOptimizeVGPRLiveRange.cpp
[LLVM][CodeGen] Remove pass initialization calls from pass constructors (#173061)
2026-01-21 08:44:51 -08:00
SIOptimizeVGPRLiveRange.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SIPeepholeSDWA.cpp
Reland "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176277)
2026-01-16 13:05:06 -08:00
SIPeepholeSDWA.h
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SIPostRABundler.cpp
[AMDGPU] Use MCRegUnit, insert explicit casts to/from unsigned (NFC) (#167889)
2025-11-13 21:39:02 +03:00
SIPostRABundler.h
[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)
2025-02-21 16:05:58 +05:30
SIPreAllocateWWMRegs.cpp
[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)
2025-08-22 10:05:06 +01:00
SIPreAllocateWWMRegs.h
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SIPreEmitPeephole.cpp
AMDGPU: Fix assert when looking for s_and_b64 + vcc branch pattern (#177031)
2026-01-20 22:23:52 +00:00
SIProgramInfo.cpp
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
SIProgramInfo.h
[AMDGPU] upstream barrier count reporting part1 (#154409)
2025-08-19 16:42:31 -07:00
SIRegisterInfo.cpp
Reland "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176277)
2026-01-16 13:05:06 -08:00
SIRegisterInfo.h
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
SIRegisterInfo.td
[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)
2026-01-20 19:14:59 -05:00
SISchedule.td
AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)
2025-07-21 10:09:42 -07:00
SIShrinkInstructions.cpp
[AMDGPU] Make SIShrinkInstructions pass return valid changed state (#168833)
2025-12-26 08:15:23 +05:30
SIShrinkInstructions.h
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SIWholeQuadMode.cpp
[NFC][AMDGPU] Declare variables initialized with getDebugLoc as const ref (#174434)
2026-01-05 12:37:47 -06:00
SIWholeQuadMode.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SMInstructions.td
[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)
2025-08-30 04:44:20 +00:00
SOPInstructions.td
[AMDGPU] Improve codegen for uniform f16<-->i32 conversions (#176833)
2026-01-21 13:07:14 -06:00
VIInstrFormats.td
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VINTERPInstructions.td
[AMDGPU] Simplify class VINTERPe. NFC. (#175006)
2026-01-08 16:18:42 +00:00
VOP1Instructions.td
[AMDGPU] Further improve AMDGPUSubtargetFeature multiclass (#177077)
2026-01-21 21:05:13 +00:00
VOP2Instructions.td
[AMDGPU] Fix inline constant encoding for v_pk_fmac_f16 (#176659)
2026-01-20 19:14:59 -05:00
VOP3Instructions.td
[AMDGPU] Further improve AMDGPUSubtargetFeature multiclass (#177077)
2026-01-21 21:05:13 +00:00
VOP3PInstructions.td
[AMDGPU] Reimplement scale_src2 encoding using PostEncoderMethod (#176140)
2026-01-16 12:21:58 +00:00
VOPCInstructions.td
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
VOPDInstructions.td
[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516)
2025-09-09 10:54:18 -04:00
VOPInstructions.td
[AMDGPU] Make VOP_SDWA_Pseudo inherit from VOP_Pseudo (#176209)
2026-01-16 11:56:56 -05:00