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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel
History
Mariusz Sikora 2b4a462e95
[AMDGPU] Add missing comma between export target and first export data (#181641) 
The new format matches the official ISA spec and ensures the
disassembler prints 'export mrt0, v0, off, off, off' instead of 'export
mrt0 v0, off, off, off'.

No functional encoding changes; printing/AsmString only.
2026-02-17 09:24:34 +01:00
..
add_shl.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
add.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
add.v2i16.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
add.vni16.ll
AMDGPU/GlobalISel: Regbanklegalize for G_CONCAT_VECTORS (#171471)
2025-12-15 10:37:40 +01:00
addo.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
addsubu64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgpu-irtranslator.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
amdgpu-prelegalizer-combiner-crash.mir
…
and.ll
[GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (#138574)
2025-05-08 19:31:28 +02:00
andn2.i1.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
andn2.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
artifact-combiner-anyext.mir
…
artifact-combiner-asserts.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
artifact-combiner-build-vector.mir
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artifact-combiner-concat-vectors.mir
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artifact-combiner-cse-leaves-dead-cast.mir
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artifact-combiner-extract.mir
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artifact-combiner-sext.mir
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artifact-combiner-trunc.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
artifact-combiner-unmerge-values.mir
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artifact-combiner-zext.mir
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ashr.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
assert-align.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomic_load_flat.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
atomic_load_global.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
atomic_load_local_2.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
atomic_load_local.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
atomic_optimizations_mul_one.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomic_store_local.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
atomicrmw_fmax.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
atomicrmw_fmin.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
atomicrmw_minmax.ll
[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)
2026-02-10 16:04:05 +05:30
atomicrmw_udec_wrap.ll
[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)
2026-02-10 16:04:05 +05:30
atomicrmw_uinc_wrap.ll
[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)
2026-02-10 16:04:05 +05:30
atomicrmw-add-sub.ll
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
atomicrmw-and.ll
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
atomicrmw-or.ll
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
atomicrmw-xchg.ll
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
atomicrmw-xor.ll
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
bitcast_38_i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bool-legalization.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
br-constant-invalid-sgpr-copy.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
bswap.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
buffer-atomic-fadd.f32-no-rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-atomic-fadd.f32-rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-atomic-fadd.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-atomic-fadd.v2f16-no-rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-atomic-fadd.v2f16-rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-load-byte-short.ll
[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#172065)
2025-12-12 14:47:08 -06:00
buffer-load-store-pointers.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
buffer-schedule.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
bug_shuffle_vector_to_scalar.ll
[GISel] Fix ShuffleVector assert (#139769)
2025-05-20 21:25:31 -04:00
bug-legalization-artifact-combiner-dead-def.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
bug-legalization-artifact-combiner-dead-def.mir
[GISel] Introduce MIFlags::InBounds (#150900)
2025-07-30 13:01:23 +02:00
call-outgoing-stack-args.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
clamp-fmed3-const-combine.ll
[AMDGPU] Fix legacy index in fmed3 optimization (#177426)
2026-01-28 10:22:22 +00:00
clamp-minmax-const-combine.ll
[GlobalIsel] Remove NoNaNsFPMath uses (#163484)
2025-10-16 09:58:44 +08:00
combine-add-nullptr.mir
…
combine-add-to-ptradd.mir
…
combine-amdgpu-cvt-f32-ubyte.mir
…
combine-ashr-narrow.mir
…
combine-binop-s64-with-s32-mask.mir
[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)
2025-08-20 17:32:29 +02:00
combine-ext-legalizer.mir
…
combine-extract-vector-load.mir
…
combine-fabs-fneg.mir
…
combine-fcanonicalize.mir
…
combine-fdiv-sqrt-to-rsq.mir
…
combine-fma-add-ext-fma.ll
[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)
2026-02-05 11:51:25 +01:00
combine-fma-add-ext-mul.ll
[LLVM] Select fma_mix for v_cvt_f32_f16 and v_add_f32/v_mul_f32 (#160151)
2026-02-05 11:51:25 +01:00
combine-fma-add-fma-mul.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)
2025-12-22 09:05:31 -08:00
combine-fma-add-mul-post-legalize.mir
[GlobalISel] Remove UnsafeFPMath references (#146319)
2025-07-29 12:11:52 +08:00
combine-fma-add-mul-pre-legalize.mir
[GlobalISel] Remove UnsafeFPMath references (#146319)
2025-07-29 12:11:52 +08:00
combine-fma-add-mul.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)
2025-12-22 09:05:31 -08:00
combine-fma-sub-ext-mul.ll
[AMDGPU] Fix and simplify patterns selecting fsub to v_fma_mix_f32 (#180169)
2026-02-06 14:39:13 +00:00
combine-fma-sub-ext-neg-mul.ll
[AMDGPU] Fix and simplify patterns selecting fsub to v_fma_mix_f32 (#180169)
2026-02-06 14:39:13 +00:00
combine-fma-sub-mul.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)
2025-12-22 09:05:31 -08:00
combine-fma-sub-neg-mul.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)
2025-12-22 09:05:31 -08:00
combine-fma-unmerge-values.mir
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
combine-fold-binop-into-select.mir
[GlobaISel] Allow expanding of sdiv -> mul by constant (#146504)
2025-07-14 15:01:12 +01:00
combine-foldable-fneg.mir
…
combine-fpneg-one-fneg.mir
…
combine-fsh.mir
…
combine-fsub-fneg.mir
…
combine-itofp.mir
…
combine-lshr-narrow.mir
…
combine-or-redundant.mir
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combine-or-s64-s32.mir
[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)
2025-10-24 17:25:00 +02:00
combine-redundant-and.mir
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combine-redundant-neg.mir
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combine-redundant-sext-inreg.mir
[GlobalISel] Combine redundant sext_inreg (#131624)
2025-04-14 11:48:08 +02:00
combine-rot.mir
…
combine-rsq.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
combine-rsq.mir
…
combine-sext-inreg.mir
…
combine-sext-trunc-sextinreg.mir
[GlobalISel] Combine redundant sext_inreg (#131624)
2025-04-14 11:48:08 +02:00
combine-shift-amount-zext.mir
[AMDGPU] Canonicalize G_ZEXT of the shift amount in RegBankCombiner (#131792)
2025-05-14 10:48:51 +02:00
combine-shift-imm-chain-illegal-types.mir
…
combine-shift-imm-chain-shlsat.mir
…
combine-shift-imm-chain.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
combine-shift-of-shifted-logic-shlsat.mir
…
combine-shift-of-shifted-logic.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
combine-shifts.mir
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
combine-shl-from-extend-narrow.postlegal.mir
[GlobalISel] Rewrite binop_left_to_zero using MIR Patterns (#177924)
2026-01-29 18:28:34 +00:00
combine-shl-from-extend-narrow.prelegal.mir
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
combine-shl-narrow.mir
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combine-short-clamp.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for SMED3 and CVT_PK_I16_I32 (#176596)
2026-01-21 08:57:53 -08:00
combine-trunc-sext.mir
[AMDGPU] Add sext_trunc in RegBankCombiner (#131623)
2025-04-14 10:15:29 +02:00
combine-trunc-shift.mir
…
combine-urem-pow-2.mir
…
combine-zext-trunc.mir
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combiner-crash.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
compute-num-sign-bits-med3.mir
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constant-bus-restriction.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
crash-stack-address-O0.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
cvt_f32_ubyte.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dereferenceable-declaration.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)
2025-10-10 08:48:06 -07:00
divergence-divergent-i1-phis-no-lane-mask-merging.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
divergence-divergent-i1-phis-no-lane-mask-merging.mir
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-divergent-i1-used-outside-loop.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
divergence-divergent-i1-used-outside-loop.mir
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-structurizer.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
divergence-structurizer.mir
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-temporal-divergent-i1.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
divergence-temporal-divergent-i1.mir
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
divergence-temporal-divergent-reg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
divergence-temporal-divergent-reg.mir
AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)
2025-03-12 12:09:37 +01:00
divergent-control-flow.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dropped_debug_info_assert.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
dummy-target.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
dynamic-alloca-uniform.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extractelement-stack-lower.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
extractelement.i8.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
extractelement.i16.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
extractelement.i128.ll
AMDGPU: Fix treating unknown mem operands as uniform (#170309)
2025-12-02 16:19:46 +00:00
extractelement.ll
[AMDGPU] Set GRANULATED_WAVEFRONT_SGPR_COUNT of compute_pgm_rsrc1 to 0 for gfx10+ (#154666)
2025-08-27 09:48:42 +08:00
fabs.ll
[AMDGPU][GlobalISel] Add readanylane combines for merge-like instruct… (#172546)
2025-12-18 08:04:06 -08:00
fadd.ll
[AMDGPU][GlobalISel] Add register bank legalization for G_FADD (#163407)
2025-10-31 16:45:40 +05:30
fcmp.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
fdiv.f16.ll
[AMDGPU] Fix pattern selecting fmul to v_fma_mix_f32 (#180210)
2026-02-07 09:31:07 +00:00
fdiv.f32.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fdiv.f64.ll
[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180940)
2026-02-11 19:14:54 +00:00
flat-atomic-fadd.f32.ll
[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)
2026-02-09 15:37:27 +00:00
flat-atomic-fadd.f64.ll
[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)
2026-02-09 15:37:27 +00:00
flat-atomic-fadd.v2f16.ll
[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)
2026-02-09 15:37:27 +00:00
flat-scratch-init.gfx.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
flat-scratch-init.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
flat-scratch.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
floor.f64.ll
…
fma.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fmad.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)
2025-12-22 09:05:31 -08:00
fmamix-constant-bus-violation.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fmamix-constant-bus-violation.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
fmax_legacy.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
fmed3-min-max-const-combine.ll
[GlobalIsel] Remove NoNaNsFPMath uses (#163484)
2025-10-16 09:58:44 +08:00
fmed3.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_FMED3 (#173085)
2025-12-23 17:31:11 -08:00
fmin_legacy.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
fmul.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMUL (#167847)
2025-11-17 08:45:49 -08:00
fmul.v2f16.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)
2025-12-22 09:05:31 -08:00
fneg.ll
[AMDGPU][GlobalISel] Add readanylane combines for merge-like instruct… (#172546)
2025-12-18 08:04:06 -08:00
fp64-atomics-gfx90a.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
fp-atomics-gfx942.ll
[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)
2026-02-09 15:37:27 +00:00
fp-int-conversions.ll
[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp (#176300)
2026-02-03 11:45:49 -06:00
fpext.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)
2026-02-02 17:55:42 +01:00
fpow.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
fptrunc.ll
[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)
2026-01-30 15:13:33 +00:00
frem.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fshl.ll
[AMDGPU] Optimize S_OR_B32 to S_ADDK_I32 where possible (#177949)
2026-02-07 09:10:12 +00:00
fshr-new-regbank-select.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
fshr.ll
[AMDGPU] Optimize S_OR_B32 to S_ADDK_I32 where possible (#177949)
2026-02-07 09:10:12 +00:00
fsub.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FSUB (#171244)
2025-12-11 11:55:28 -08:00
function-returns.ll
[GISel] Set more MIFlags when translating GEPs (#151708)
2025-08-04 13:25:33 +02:00
function-returns.v2i65.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
global-atomic-fadd.f32-no-rtn.ll
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
global-atomic-fadd.f32-rtn.ll
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
global-atomic-fadd.f64.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
global-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)
2026-02-09 15:37:27 +00:00
global-atomic-fadd.v2f16-rtn.ll
[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)
2026-02-09 15:37:27 +00:00
global-value-addrspaces.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
global-value.illegal.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
global-value.ll
…
hip.extern.shared.array.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
i1-copy.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
icmp.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
image-waterfall-loop-O0.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
implicit-kernarg-backend-usage-global-isel.ll
[AMDGPU] Add regbankselect rules for G_ICMP/G_FCMP (#172048)
2026-01-14 12:37:16 -05:00
inline-asm-mismatched-size.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
inline-asm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
insertelement-stack-lower.ll
Revert "CodeGen: Record MMOs in finalizeBundle" (#166520)
2025-11-05 11:11:08 +01:00
insertelement.i8.ll
[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)
2026-01-30 15:13:33 +00:00
insertelement.i16.ll
[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)
2026-01-30 15:13:33 +00:00
insertelement.large.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)
2025-10-10 08:48:06 -07:00
insertelement.ll
[AMDGPU] Remove redundant s_cmp_* after add X, 1 (#176962)
2026-01-23 07:51:36 -06:00
inst-select-abs.mir
…
inst-select-add.mir
…
inst-select-add.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-amdgcn.class.mir
…
inst-select-amdgcn.class.s16.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-amdgcn.cos.mir
…
inst-select-amdgcn.cos.s16.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-amdgcn.cvt.pk.i16.mir
…
inst-select-amdgcn.cvt.pk.u16.mir
…
inst-select-amdgcn.cvt.pknorm.i16.mir
…
inst-select-amdgcn.cvt.pknorm.u16.mir
…
inst-select-amdgcn.cvt.pkrtz.mir
…
inst-select-amdgcn.ds.swizzle.mir
…
inst-select-amdgcn.exp.compr.mir
…
inst-select-amdgcn.exp.mir
…
inst-select-amdgcn.fcmp.constants.w32.mir
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00
inst-select-amdgcn.fcmp.constants.w64.mir
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00
inst-select-amdgcn.fmad.ftz.mir
…
inst-select-amdgcn.fmed3.mir
…
inst-select-amdgcn.fmed3.s16.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-amdgcn.fract.mir
…
inst-select-amdgcn.fract.s16.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-amdgcn.groupstaticsize.mir
…
inst-select-amdgcn.mbcnt.lo.mir
…
inst-select-amdgcn.mul.u24.mir
…
inst-select-amdgcn.mulhi.i24.mir
…
inst-select-amdgcn.mulhi.u24.mir
…
inst-select-amdgcn.rcp.legacy.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-amdgcn.rcp.mir
…
inst-select-amdgcn.rcp.s16.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-amdgcn.readfirstlane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
inst-select-amdgcn.reloc.constant.mir
…
inst-select-amdgcn.rsq.clamp.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-amdgcn.rsq.legacy.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-amdgcn.rsq.mir
…
inst-select-amdgcn.rsq.s16.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-amdgcn.s.barrier.mir
…
inst-select-amdgcn.s.sendmsg.mir
…
inst-select-amdgcn.sffbh.mir
…
inst-select-amdgcn.sin.mir
…
inst-select-amdgcn.sin.s16.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-amdgpu-atomic-cmpxchg-flat.mir
[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)
2025-08-12 09:35:19 +02:00
inst-select-amdgpu-atomic-cmpxchg-global.mir
…
inst-select-amdgpu-ffbh-u32.mir
…
inst-select-amdgpu-ffbl-b32.mir
…
inst-select-amdgpu-wave-address.mir
…
inst-select-and.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-anyext.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-ashr.mir
…
inst-select-ashr.s16.mir
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
inst-select-ashr.v2s16.mir
…
inst-select-atomic-cmpxchg-local.mir
…
inst-select-atomic-cmpxchg-region.mir
…
inst-select-atomicrmw-add-flat.mir
[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)
2025-08-12 09:35:19 +02:00
inst-select-atomicrmw-add-global.mir
…
inst-select-atomicrmw-fadd-local.mir
…
inst-select-atomicrmw-fadd-region.mir
…
inst-select-atomicrmw-xchg-local.mir
…
inst-select-atomicrmw-xchg-region.mir
…
inst-select-bitcast.mir
…
inst-select-bitreverse.mir
…
inst-select-br.mir
…
inst-select-brcond.mir
…
inst-select-bswap.mir
Reapply "[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and … (#149262)
2025-07-21 10:14:45 -07:00
inst-select-build-vector-trunc.v2s16.mir
…
inst-select-build-vector.mir
…
inst-select-concat-vectors.mir
…
inst-select-constant.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-copy-scc-vcc.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
inst-select-copy-scc-vcc.mir
[AMDGPU][GlobalISel] Clean up selectCOPY_SCC_VCC function (#165797)
2025-10-31 13:17:44 -07:00
inst-select-copy.mir
…
inst-select-ctlz-zero-undef.mir
…
inst-select-ctpop.mir
[TableGen][GISel] Import more "multi-level" patterns (#120332)
2024-12-18 14:44:55 +03:00
inst-select-cttz-zero-undef.mir
…
inst-select-extract-vector-elt.mir
[AMDGPU] Add missing cases for V_INDIRECT_REG_{READ/WRITE}_GPR_IDX and V/S_INDIRECT_REG_WRITE_MOVREL (#171835)
2025-12-12 15:45:34 +00:00
inst-select-extract.mir
…
inst-select-fabs.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fadd.s16.mir
…
inst-select-fadd.s32.mir
…
inst-select-fadd.s64.mir
…
inst-select-fcanonicalize.mir
[AMDGPU][True16][CodeGen] true16 codegen pattern for f16 canonicalize (#122000)
2025-01-24 10:44:00 -05:00
inst-select-fceil.mir
…
inst-select-fceil.s16.mir
…
inst-select-fcmp.mir
…
inst-select-fcmp.s16.gfx11plus-fake16.mir
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
2025-02-04 11:20:40 -05:00
inst-select-fcmp.s16.gfx11plus.mir
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
2025-02-04 11:20:40 -05:00
inst-select-fcmp.s16.mir
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
2025-02-04 11:20:40 -05:00
inst-select-fconstant.mir
…
inst-select-fexp2.mir
…
inst-select-ffloor.s16.mir
…
inst-select-ffloor.s32.mir
…
inst-select-ffloor.s64.mir
…
inst-select-fma.s32.mir
…
inst-select-fmad.s32.mir
…
inst-select-fmaxnum-ieee.mir
…
inst-select-fmaxnum-ieee.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fmaxnum-ieee.v2s16.mir
…
inst-select-fmaxnum.mir
…
inst-select-fmaxnum.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fmaxnum.v2s16.mir
…
inst-select-fminnum-ieee.mir
…
inst-select-fminnum-ieee.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fminnum-ieee.v2s16.mir
…
inst-select-fminnum.mir
…
inst-select-fminnum.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fminnum.v2s16.mir
…
inst-select-fmul.mir
…
inst-select-fmul.v2s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fneg.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fptosi.mir
…
inst-select-fptoui.mir
…
inst-select-fract.f64.mir
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
inst-select-frame-index.mir
…
inst-select-freeze.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-fshr.mir
Reapply "[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and … (#149262)
2025-07-21 10:14:45 -07:00
inst-select-i1-copy.mir
…
inst-select-icmp.mir
…
inst-select-icmp.s16.mir
[AMDGPU][True16][CodeGen] gisel true16 for ICMP (#128913)
2025-03-13 12:03:17 -04:00
inst-select-icmp.s64.mir
…
inst-select-implicit-def.mir
…
inst-select-insert-vector-elt.mir
[AMDGPU] Add missing cases for V_INDIRECT_REG_{READ/WRITE}_GPR_IDX and V/S_INDIRECT_REG_WRITE_MOVREL (#171835)
2025-12-12 15:45:34 +00:00
inst-select-insert.mir
…
inst-select-intrinsic-trunc.mir
…
inst-select-intrinsic-trunc.s16.mir
…
inst-select-inttoptr.mir
…
inst-select-load-atomic-flat.mir
[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)
2025-08-12 09:35:19 +02:00
inst-select-load-atomic-global.mir
[AMDGPU] More flatGVS gfx1250 patterns (#149410)
2025-07-17 16:10:59 -07:00
inst-select-load-atomic-local.mir
…
inst-select-load-constant.mir
…
inst-select-load-flat.mir
[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)
2025-08-12 09:35:19 +02:00
inst-select-load-global-old-legalization.mir
…
inst-select-load-global-saddr.mir
…
inst-select-load-global.mir
…
inst-select-load-global.s96.mir
…
inst-select-load-local-128.mir
…
inst-select-load-local.mir
…
inst-select-load-private.mir
…
inst-select-load-smrd.mir
…
inst-select-lshr.mir
…
inst-select-lshr.s16.mir
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
inst-select-lshr.v2s16.mir
…
inst-select-mad_64_32.mir
…
inst-select-merge-values.mir
…
inst-select-mul.mir
…
inst-select-or.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-pattern-add3.mir
…
inst-select-pattern-and-or.mir
…
inst-select-pattern-or3.mir
…
inst-select-pattern-smed3.mir
…
inst-select-pattern-smed3.s16.mir
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
inst-select-pattern-umed3.mir
…
inst-select-pattern-umed3.s16.mir
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
inst-select-pattern-xor3.mir
…
inst-select-phi.mir
…
inst-select-pseudo-scalar-transcendental.mir
…
inst-select-ptr-add.mir
…
inst-select-ptrmask.mir
…
inst-select-ptrtoint.mir
…
inst-select-returnaddress.mir
…
inst-select-sbfx.mir
…
inst-select-scalar-float-sop1.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
inst-select-scalar-float-sop2.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
inst-select-scalar-float-sopc.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
inst-select-scalar-packed.xfail.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-select.mir
…
inst-select-sext-inreg.mir
…
inst-select-sext.mir
…
inst-select-sextload-local.mir
…
inst-select-shl.mir
…
inst-select-shl.s16.mir
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
inst-select-shl.v2s16.mir
…
inst-select-sitofp.mir
…
inst-select-smax-64.mir
[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)
2025-08-25 14:32:08 -07:00
inst-select-smax.mir
…
inst-select-smin-64.mir
[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)
2025-08-25 14:32:08 -07:00
inst-select-smin.mir
[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)
2025-08-25 14:32:08 -07:00
inst-select-smulh.mir
…
inst-select-stacksave-stackrestore.invalid.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inst-select-stacksave-stackrestore.mir
…
inst-select-store-atomic-flat.mir
[AMDGPU] More flatGVS gfx1250 patterns (#149410)
2025-07-17 16:10:59 -07:00
inst-select-store-atomic-local.mir
…
inst-select-store-flat.mir
[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)
2025-08-12 09:35:19 +02:00
inst-select-store-global.mir
…
inst-select-store-global.s96.mir
…
inst-select-store-local.mir
…
inst-select-store-private.mir
…
inst-select-sub.mir
…
inst-select-trunc.mir
…
inst-select-trunc.v2s16.mir
…
inst-select-uadde.gfx10.mir
…
inst-select-uadde.mir
…
inst-select-uaddo.mir
…
inst-select-ubfx.mir
…
inst-select-uitofp.mir
…
inst-select-umax-64.mir
[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)
2025-08-25 14:32:08 -07:00
inst-select-umax.mir
…
inst-select-umin-64.mir
[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)
2025-08-25 14:32:08 -07:00
inst-select-umin.mir
…
inst-select-umulh.mir
…
inst-select-unmerge-values.mir
…
inst-select-usube.gfx10.mir
…
inst-select-usube.mir
…
inst-select-usubo.mir
…
inst-select-xor.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
inst-select-zext.mir
…
inst-select-zextload-local.mir
…
irtranslate-bf16.ll
AMDGPU: Directly use v2bf16 as register type for bf16 vectors. (#175761)
2026-01-13 17:48:38 +01:00
irtranslator-amdgcn-cs-chain.ll
[AMDGPU] Allow any SGPRs for chain callees (#168345)
2025-12-02 09:44:35 +01:00
irtranslator-amdgcn-sendmsg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
irtranslator-amdgpu_kernel-system-sgprs.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-amdgpu_kernel.ll
[GISel][CallLowering] Keep IR types longer (#179946)
2026-02-05 16:37:08 +01:00
irtranslator-amdgpu_ps.ll
AMDGPU: Replace undef with poison in tests using insertvalue (#130895)
2025-03-12 16:11:11 +07:00
irtranslator-amdgpu_vs.ll
AMDGPU: Replace some float undef test uses with poison (#131090)
2025-03-13 20:07:48 +07:00
irtranslator-assert-align.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
irtranslator-atomicrmw.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
irtranslator-call-abi-attribute-hints.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
irtranslator-call-implicit-args.ll
[GISel] Introduce MIFlags::InBounds (#150900)
2025-07-30 13:01:23 +02:00
irtranslator-call-non-fixed.ll
[GISel] Introduce MIFlags::InBounds (#150900)
2025-07-30 13:01:23 +02:00
irtranslator-call-return-values.ll
[GISel] Introduce MIFlags::InBounds (#150900)
2025-07-30 13:01:23 +02:00
irtranslator-call-sret.ll
[GISel] Introduce MIFlags::InBounds (#150900)
2025-07-30 13:01:23 +02:00
irtranslator-call.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
irtranslator-constant-fold-vector-op.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
irtranslator-constantexpr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
irtranslator-constrained-fp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
irtranslator-fast-math-flags.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-fence.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
irtranslator-fixed-function-abi-vgpr-args.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-function-args.ll
AMDGPU: Directly use v2bf16 as register type for bf16 vectors. (#175761)
2026-01-13 17:48:38 +01:00
irtranslator-function-args.v2i65.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-getelementptr.ll
…
irtranslator-indirect-call.ll
[GISel] Introduce MIFlags::InBounds (#150900)
2025-07-30 13:01:23 +02:00
irtranslator-inline-asm.ll
[GlobalISel] Add support for value/constants as inline asm memory operand (#161501)
2025-11-14 10:34:38 +01:00
irtranslator-invariant.ll
[GISel] Introduce MIFlags::InBounds (#150900)
2025-07-30 13:01:23 +02:00
irtranslator-memory-intrinsics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
irtranslator-metadata.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
irtranslator-non-integral-address-spaces-vectors.ll
[AMDGPULowerBufferFatPointers] Use InstSimplifyFolder during rewrites (#134137)
2025-04-03 10:12:18 -05:00
irtranslator-non-integral-address-spaces.ll
…
irtranslator-prefetch.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
irtranslator-ptrmask.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
irtranslator-readnone-intrinsic-callsite.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-sat.ll
…
irtranslator-sibling-call.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
irtranslator-struct-return-intrinsics.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
irtranslator-tail-call.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
irtranslator-zext-vec-index.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
is-safe-to-sink-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
known-bits-sbfe.mir
[AMDGPU] Compute GISel KnownBits for S_BFE instructions (#141588)
2025-07-16 09:56:45 +02:00
knownbits-ptrtoint.mir
[GISelValueTracking] Add test case for G_PTRTOINT
2025-06-11 10:47:17 -07:00
lds-global-value.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
lds-misaligned-bug.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)
2025-10-10 08:48:06 -07:00
lds-relocs.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BLOCK_ADDR and G_GLOBAL_VALUE (#165340)
2025-11-11 09:31:59 -08:00
lds-zero-initializer.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BLOCK_ADDR and G_GLOBAL_VALUE (#165340)
2025-11-11 09:31:59 -08:00
legalize-abs.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-add.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-addrspacecast.mir
AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)
2025-12-01 18:40:26 -05:00
legalize-amdgcn.if-invalid.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
legalize-amdgcn.if.xfail.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
legalize-amdgcn.rsq.clamp.mir
…
legalize-amdgcn.wavefrontsize.mir
…
legalize-amdgcn.workitem.id.mir
…
legalize-and.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-anyext.mir
…
legalize-ashr.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-atomic-cmpxchg-with-success.mir
…
legalize-atomic-cmpxchg.mir
…
legalize-atomicrmw-add.mir
…
legalize-atomicrmw-and.mir
…
legalize-atomicrmw-fadd-global.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
legalize-atomicrmw-fadd-local.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
legalize-atomicrmw-max.mir
…
legalize-atomicrmw-min.mir
…
legalize-atomicrmw-nand.mir
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
legalize-atomicrmw-or.mir
…
legalize-atomicrmw-sub.mir
…
legalize-atomicrmw-umax.mir
…
legalize-atomicrmw-umin.mir
…
legalize-atomicrmw-xchg-flat.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
legalize-atomicrmw-xchg.mir
…
legalize-atomicrmw-xor.mir
…
legalize-bitcast.mir
…
legalize-bitreverse.mir
…
legalize-block-addr.mir
…
legalize-brcond.mir
…
legalize-bswap.mir
…
legalize-build-vector-splat.mir
…
legalize-build-vector-trunc.mir
…
legalize-build-vector.mir
…
legalize-build-vector.s16.mir
…
legalize-concat-vectors.mir
…
legalize-constant.mir
…
legalize-ctlz-zero-undef.mir
…
legalize-ctlz.mir
…
legalize-ctpop.mir
…
legalize-cttz-zero-undef.mir
[GISel] handle CTTZ in computeKnownBits (#181474)
2026-02-15 15:43:05 -08:00
legalize-cttz.mir
[GISel] handle CTTZ in computeKnownBits (#181474)
2026-02-15 15:43:05 -08:00
legalize-divrem.mir
GlobalISel: Adjust insert point when expanding G_[SU]DIVREM
2025-09-25 11:00:53 +00:00
legalize-extract-vector-elt.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-extract.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-extractelement-crash.mir
…
legalize-fabs.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fadd.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fcanonicalize.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fceil.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fcmp-s32.mir
…
legalize-fcmp.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fconstant.mir
…
legalize-fcopysign.mir
…
legalize-fcos.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fdiv.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fexp2.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fexp.mir
…
legalize-ffloor.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-flog2.mir
…
legalize-flog10.mir
…
legalize-flog.mir
…
legalize-fma.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fmad.s16.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fmad.s32.mir
…
legalize-fmad.s64.mir
…
legalize-fmaximum.mir
[AMDGPU][GlobalISel] Lower G_FMINIMUM and G_FMAXIMUM (#151122)
2025-10-24 14:48:27 +02:00
legalize-fmaxnum.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fminimum.mir
[AMDGPU][GlobalISel] Lower G_FMINIMUM and G_FMAXIMUM (#151122)
2025-10-24 14:48:27 +02:00
legalize-fminnum.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fmul.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fneg.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fpext.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fpow.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-fpowi.mir
…
legalize-fptosi.mir
…
legalize-fptoui.mir
…
legalize-fptrunc.mir
[GlobalISel] Remove UnsafeFPMath references (#146319)
2025-07-29 12:11:52 +08:00
legalize-freeze.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fshl.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fshr.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fsin.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fsqrt.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-fsub.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-icmp.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-implicit-def-s1025.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-implicit-def.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-insert-vector-elt.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-insert.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-intrinsic-amdgcn-fdiv-fast.mir
…
legalize-intrinsic-round.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-intrinsic-trunc.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-inttoptr.mir
…
legalize-jump-table.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
legalize-llvm.amdgcn.image.dim.a16.ll
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-llvm.amdgcn.image.load.2d.d16.ll
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-llvm.amdgcn.image.load.2d.ll
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
…
legalize-llvm.amdgcn.image.load.3d.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
legalize-llvm.amdgcn.image.sample.a16.ll
…
legalize-llvm.amdgcn.image.sample.d.ll
…
legalize-llvm.amdgcn.image.sample.g16.a16.ll
…
legalize-llvm.amdgcn.image.sample.g16.ll
…
legalize-llvm.amdgcn.image.store.2d.d16.ll
…
legalize-llvm.amdgcn.s.buffer.load.mir
[AMDGPU] gfx1250 s_buffer_load tests. NFC. (#155295)
2025-08-25 14:32:50 -07:00
legalize-load-constant-32bit.mir
AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)
2025-12-01 18:40:26 -05:00
legalize-load-constant.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-load-flat.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-load-global.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-load-local.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-load-memory-metadata.mir
MachineVerifier: Fix check for range type (#124894)
2025-01-30 10:56:12 +07:00
legalize-load-private.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-lshr.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-memcpy.mir
[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)
2025-07-22 00:42:23 -07:00
legalize-memcpyinline.mir
[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)
2025-07-22 00:42:23 -07:00
legalize-memmove.mir
[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)
2025-07-22 00:42:23 -07:00
legalize-memset.mir
[GlobalISel] Allow Legalizer to lower volatile memcpy family. (#145997)
2025-07-22 00:42:23 -07:00
legalize-merge-values-build-vector.mir
…
legalize-merge-values.mir
…
legalize-mul.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-or.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-phi.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-ptr-add.mir
…
legalize-ptrmask.mir
…
legalize-ptrtoint.mir
…
legalize-rotl-rotr.mir
[AArch64][GlobalISel] Add disjoint to the G_OR when lowering G_ROTR/L (#172317)
2026-01-02 09:07:21 +00:00
legalize-sadde.mir
…
legalize-saddo.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-saddsat.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-sbfx.mir
…
legalize-sdiv.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-select.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-sext-inreg.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-sext.mir
[AMDGPU][Legalizer] Widen i16 G_SEXT_INREG (#131308)
2025-05-07 10:22:15 +02:00
legalize-sextload-constant-32bit.mir
AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)
2025-12-01 18:40:26 -05:00
legalize-sextload-flat.mir
…
legalize-sextload-global.mir
[GISel] Introduce MIFlags::InBounds (#150900)
2025-07-30 13:01:23 +02:00
legalize-sextload-local.mir
…
legalize-sextload-private.mir
…
legalize-shl.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-shuffle-vector.mir
[Legalizer] Cache extracted element when lowering G_SHUFFLE_VECTOR. (#163893)
2025-10-25 10:26:11 -05:00
legalize-shuffle-vector.s16.mir
[Legalizer] Cache extracted element when lowering G_SHUFFLE_VECTOR. (#163893)
2025-10-25 10:26:11 -05:00
legalize-sitofp.mir
Revert "[AMDGPU] Replace AMDGPUISD::FFBH_I32 with ISD::CTLS" (#178837)
2026-01-29 21:19:15 -08:00
legalize-smax.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-smin.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-smulh.mir
[GlobalISel] Add computeNumSignBits for ASHR (#139503)
2025-07-21 10:23:26 +01:00
legalize-smulo.mir
…
legalize-srem.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-sshlsat.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-ssube.mir
…
legalize-ssubo.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-ssubsat.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-store-global.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-store.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-strict_fsub.mir
…
legalize-sub.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-trap-gfx11.mir
…
legalize-trap.mir
…
legalize-trunc.mir
…
legalize-uadde.mir
…
legalize-uaddo.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-uaddsat.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-ubfx.mir
…
legalize-udiv.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-uitofp.mir
…
legalize-umax.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-umin.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-umulh.mir
…
legalize-umulo.mir
…
legalize-unmerge-values.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-urem.mir
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
legalize-ushlsat.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-usube.mir
…
legalize-usubo.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-usubsat.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-vector-args-gfx7.mir
…
legalize-vector-args-gfx8-plus.mir
…
legalize-xor.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-zext.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-zextload-constant-32bit.mir
AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)
2025-12-01 18:40:26 -05:00
legalize-zextload-flat.mir
…
legalize-zextload-global.mir
[GISel] Introduce MIFlags::InBounds (#150900)
2025-07-30 13:01:23 +02:00
legalize-zextload-local.mir
…
legalize-zextload-private.mir
…
llvm.abs.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)
2025-10-30 12:32:32 +05:30
llvm.amdgcn.ballot.i64.ll
[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)
2025-10-30 12:32:32 +05:30
llvm.amdgcn.dispatch.ptr.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
llvm.amdgcn.div.fmas.ll
[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)
2026-02-03 11:10:28 +09:00
llvm.amdgcn.div.scale.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.end.cf.i32.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.end.cf.i64.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for amd_gcn_end_cf (#175118)
2026-01-13 18:18:39 +05:30
llvm.amdgcn.fdot2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fmul.legacy.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
llvm.amdgcn.fract.ll
[AMDGPU][GlobalISel] Add frexp_mant/fract intrinsic RegBankLegalize r… (#177512)
2026-01-26 10:23:40 -08:00
llvm.amdgcn.frexp.mant.ll
[AMDGPU][GlobalISel] Add frexp_mant/fract intrinsic RegBankLegalize r… (#177512)
2026-01-26 10:23:40 -08:00
llvm.amdgcn.if.break.i32.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
llvm.amdgcn.if.break.i64.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for S64 amdgcn_if_break (#176496)
2026-01-19 11:25:01 -08:00
llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.image.atomic.dim.ll
[AMDGPU] Support image atomic no return instructions (#150742)
2025-10-29 10:42:15 +08:00
llvm.amdgcn.image.atomic.dim.mir
[AMDGPU] Support image atomic no return instructions (#150742)
2025-10-29 10:42:15 +08:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
2025-05-08 17:37:08 -04:00
llvm.amdgcn.image.gather4.dim.ll
…
llvm.amdgcn.image.gather4.o.dim.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.image.getresinfo.a16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.getresinfo.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.load.1d.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.load.1d.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.load.2d.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.load.2darraymsaa.a16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.load.2darraymsaa.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.load.3d.a16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.load.3d.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.cd.g16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.g16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.store.2d.d16.ll
…
llvm.amdgcn.image.store.2d.ll
…
llvm.amdgcn.implicit.ptr.buffer.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
llvm.amdgcn.interp.inreg.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
llvm.amdgcn.interp.p1.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.intersect_ray.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
llvm.amdgcn.make.buffer.rsrc.ll
[AMDGPU] Add the support for 45-bit buffer resource (#159702)
2025-09-24 11:12:02 -04:00
llvm.amdgcn.mfma.gfx90a.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mov.dpp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.mul24.ll
[AMDGPU][GlobalISel] Add RegBankLegalize mul24 and fmul.legacy (#173123)
2025-12-23 12:35:28 -08:00
llvm.amdgcn.queue.ptr.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
llvm.amdgcn.raw.buffer.atomic.add.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
AMDGPU/GlobalISel: RegBankLegalize rules for buffer atomic cmpswap (#180666)
2026-02-10 11:11:38 -08:00
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.buffer.atomic.integer-minmax.ll
[AMDGPU][NFC] Fix test by removing debug flag in llvm.amdgcn.raw.buffer.atomic.integer-minmax.ll (#181044)
2026-02-11 18:04:31 -06:00
llvm.amdgcn.raw.buffer.atomic.swap.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)
2026-02-09 09:04:17 -08:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU][GlobalISel] Fix D16 buffer load RegBankLegalize rules (#179982)
2026-02-06 08:01:30 -08:00
llvm.amdgcn.raw.buffer.load.format.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)
2025-09-30 07:56:23 -07:00
llvm.amdgcn.raw.buffer.load.ll
[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#172065)
2025-12-12 14:47:08 -06:00
llvm.amdgcn.raw.buffer.load.tfe.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for TFE buffer loads (#179529)
2026-02-05 13:42:11 -08:00
llvm.amdgcn.raw.buffer.store.format.f16.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.raw.buffer.store.format.f32.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU][GlobalISel] Add buffer store byte/short RegBankLegalize rules (#179367)
2026-02-05 07:18:39 -08:00
llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
AMDGPU/GlobalISel: RegBankLegalize rules for buffer atomic cmpswap (#180666)
2026-02-10 11:11:38 -08:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)
2026-02-09 09:04:17 -08:00
llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)
2026-02-04 09:20:41 -08:00
llvm.amdgcn.raw.ptr.buffer.load.format.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)
2025-09-30 07:56:23 -07:00
llvm.amdgcn.raw.ptr.buffer.load.ll
[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#172065)
2025-12-12 14:47:08 -06:00
llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.raw.ptr.buffer.store.ll
[AMDGPU][GlobalISel] Add buffer store byte/short RegBankLegalize rules (#179367)
2026-02-05 07:18:39 -08:00
llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)
2026-02-04 09:20:41 -08:00
llvm.amdgcn.raw.ptr.tbuffer.load.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)
2025-09-30 07:56:23 -07:00
llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
AMDGPU/GlobalISel: Fix buffer store RegBankLegalize rules (#179994)
2026-02-05 16:20:09 -08:00
llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.raw.ptr.tbuffer.store.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU][GlobalISel] Fix D16 buffer load RegBankLegalize rules (#179982)
2026-02-06 08:01:30 -08:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)
2025-09-30 07:56:23 -07:00
llvm.amdgcn.raw.tbuffer.store.f16.ll
AMDGPU/GlobalISel: Fix buffer store RegBankLegalize rules (#179994)
2026-02-05 16:20:09 -08:00
llvm.amdgcn.raw.tbuffer.store.i8.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.rsq.clamp.ll
[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180940)
2026-02-11 19:14:54 +00:00
llvm.amdgcn.s.buffer.load.ll
[AMDGPU][GFX1250] Implement offset handling in s.buffer.load (#178389)
2026-01-29 18:00:48 +09:00
llvm.amdgcn.s.setreg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.sleep.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_s_sleep (#178838)
2026-01-30 09:00:14 -08:00
llvm.amdgcn.sbfe.ll
[AMDGPU][GlobalISel] Add ubfe and sbfe intrinsic RegBankLegalize rules (#177276)
2026-01-22 09:01:52 -08:00
llvm.amdgcn.sdot2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sdot4.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sdot8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.set.inactive.ll
[CodeGen] MachineVerifier to check early-clobber constraint (#151421)
2025-11-04 18:39:31 -08:00
llvm.amdgcn.softwqm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.atomic.add.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
AMDGPU/GlobalISel: RegBankLegalize rules for buffer atomic cmpswap (#180666)
2026-02-10 11:11:38 -08:00
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.atomic.swap.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)
2026-02-09 09:04:17 -08:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)
2026-02-04 09:20:41 -08:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for TFE buffer loads (#179529)
2026-02-05 13:42:11 -08:00
llvm.amdgcn.struct.buffer.load.ll
[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#172065)
2025-12-12 14:47:08 -06:00
llvm.amdgcn.struct.buffer.load.tfe.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for TFE buffer loads (#179529)
2026-02-05 13:42:11 -08:00
llvm.amdgcn.struct.buffer.store.format.f16.ll
AMDGPU/GlobalISel: Fix buffer store RegBankLegalize rules (#179994)
2026-02-05 16:20:09 -08:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU][GlobalISel] Add buffer store byte/short RegBankLegalize rules (#179367)
2026-02-05 07:18:39 -08:00
llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
AMDGPU/GlobalISel: RegBankLegalize rules for buffer atomic cmpswap (#180666)
2026-02-10 11:11:38 -08:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)
2026-02-09 09:04:17 -08:00
llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)
2026-02-04 09:20:41 -08:00
llvm.amdgcn.struct.ptr.buffer.load.format.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for TFE buffer loads (#179529)
2026-02-05 13:42:11 -08:00
llvm.amdgcn.struct.ptr.buffer.load.ll
[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#172065)
2025-12-12 14:47:08 -06:00
llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
AMDGPU/GlobalISel: Fix buffer store RegBankLegalize rules (#179994)
2026-02-05 16:20:09 -08:00
llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.struct.ptr.buffer.store.ll
[AMDGPU][GlobalISel] Add buffer store byte/short RegBankLegalize rules (#179367)
2026-02-05 07:18:39 -08:00
llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)
2026-02-04 09:20:41 -08:00
llvm.amdgcn.struct.ptr.tbuffer.load.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)
2025-09-30 07:56:23 -07:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)
2026-02-04 09:20:41 -08:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)
2025-09-30 07:56:23 -07:00
llvm.amdgcn.sudot4.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sudot8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.trig.preop.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
llvm.amdgcn.ubfe.ll
[AMDGPU][GlobalISel] Add ubfe and sbfe intrinsic RegBankLegalize rules (#177276)
2026-01-22 09:01:52 -08:00
llvm.amdgcn.udot2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.udot4.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.udot8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.update.dpp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.wmma_32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.wmma_64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.workgroup.id.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
llvm.amdgcn.workitem.id.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)
2025-10-10 08:48:06 -07:00
llvm.amdgcn.wqm.demote.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
llvm.amdgcn.wqm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.writelane.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.wwm.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_wwm/strict_wwm (#178615)
2026-01-30 08:26:59 -08:00
llvm.atomic.cmpxchg.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ATOMIC_CMPXCHG (#178066)
2026-01-27 09:02:33 -08:00
llvm.memcpy.inline.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
llvm.memcpy.ll
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
2025-12-03 11:13:52 +01:00
llvm.memmove.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.memset.ll
[LowerMemIntrinsics] Optimize memset lowering (#169040)
2026-02-04 13:35:13 +01:00
llvm.powi.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
load-constant32bit.ll
AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)
2025-12-01 18:40:26 -05:00
load-constant.96.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
load-d16.ll
AMDGPU/GlobalISel: Import D16 load patterns and add combines for them (#153178)
2025-09-11 12:02:50 +02:00
load-divergent.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
load-legalize-range-metadata.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
load-local.96.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
load-local.128.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
load-unaligned.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
load-uniform-in-vgpr.ll
AMDGPU/GlobalISel: Combine S16 copy-trunc-readanylane-anyext (#168410)
2025-11-24 15:57:07 +01:00
load-uniform.ll
AMDGPU/GlobalISel: Combine S16 copy-trunc-readanylane-anyext (#168410)
2025-11-24 15:57:07 +01:00
load-zero-and-sign-extending-divergent.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
load-zero-and-sign-extending-uniform-in-vgpr.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
load-zero-and-sign-extending-uniform.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
localizer-wrong-insert-point.mir
…
localizer.ll
[AMDGPU] Add identity_combines to RegBankCombiner (#131305)
2025-03-17 10:11:28 +01:00
lshr.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
mad.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_MAD_U64_U32 (#176060)
2026-01-19 11:21:45 -08:00
madmix-constant-bus-violation.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
madmix-constant-bus-violation.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
memory-legalizer-atomic-fence.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FENCE (#165939)
2025-11-03 09:36:49 -08:00
merge-buffer-stores.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
minmaxabs-i64.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
minmaxabs.ll
…
mmra.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FENCE (#165939)
2025-11-03 09:36:49 -08:00
mubuf-global.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
mul-known-bits.i64.ll
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" (#169219)
2025-11-24 09:27:25 +08:00
mul-known-bits.i64.mir
…
mul.ll
Reland "[AMDGPU][GlobalISel] Add RegBankLegalize support for G_MUL (#… (#177481)
2026-01-22 14:59:52 -08:00
mul.v2i16.ll
…
no-cse-nonlocal-convergent-instrs.mir
…
no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
[GlobalISel] Check whether G_CTLZ is legal in matchUMulHToLShr (#126457)
2025-02-10 00:11:09 -05:00
no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
[GlobalISel] Check whether G_CTLZ is legal in matchUMulHToLShr (#126457)
2025-02-10 00:11:09 -05:00
no-legalize-atomic.mir
…
non-entry-alloca.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
or.ll
[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)
2025-10-24 17:25:00 +02:00
orn2.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
postlegalizer-combiner-buildvector-identities.mir
…
postlegalizer-combiner-divrem.mir
…
postlegalizer-combiner-fcanonicalize.mir
…
postlegalizer-combiner-freeze.mir
…
postlegalizer-combiner-merge.mir
[GlobalISel] Insert bitcast instead of register replacement when types don't match. (#177397)
2026-01-30 09:18:31 +00:00
postlegalizer-combiner-reassoc.mir
…
postlegalizer-combiner-sextload-from-sextinreg.mir
…
postlegalizer-combiner-trunc-bitcast-buildvector.mir
…
postlegalizer-combiner-unmerge-undef.mir
…
postlegalizer-combiner-zextload-from-and.mir
[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)
2025-08-20 17:32:29 +02:00
postlegalizercombiner-and.mir
…
postlegalizercombiner-ashr.mir
…
postlegalizercombiner-load-and-mask.mir
…
postlegalizercombiner-lshr.mir
…
postlegalizercombiner-mul.mir
…
postlegalizercombiner-sbfx.mir
[GlobalISel] Add computeNumSignBits for ASHR (#139503)
2025-07-21 10:23:26 +01:00
postlegalizercombiner-select.mir
…
postlegalizercombiner-shl.mir
…
postlegalizercombiner-ubfx.mir
…
prelegalizer-combiner-divrem.mir
AMDGPU: Replace more undef test pointer uses with poison (#131102)
2025-03-14 09:53:45 +07:00
prelegalizer-combiner-fptrunc_fpext.mir
…
prelegalizer-combiner-redundant-bitcast.mir
…
prelegalizer-combiner-sext_inreg-to-and.mir
…
prelegalizer-combiner-shuffle.mir
[GlobalISel] Make scalar G_SHUFFLE_VECTOR illegal. (#140508)
2025-10-24 08:21:35 +01:00
promote-dependency-on-invariant-result.ll
GlobalISel: Fix defined register of invariant.start (#125664)
2025-02-04 23:59:03 +07:00
readanylane-combines.ll
[AMDGPU][GlobalISel] Add readanylane combines for merge-like instruct… (#172546)
2025-12-18 08:04:06 -08:00
readanylane-combines.mir
[AMDGPU][GlobalISel] Add readanylane combines for merge-like instruct… (#172546)
2025-12-18 08:04:06 -08:00
regbankcombiner-clamp-fmed3-const.mir
…
regbankcombiner-clamp-minmax-const.mir
…
regbankcombiner-fmed3-minmax-const.mir
…
regbankcombiner-ignore-copies-crash.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
regbankcombiner-redundant-and.mir
…
regbankcombiner-smed3.mir
…
regbankcombiner-umed3.mir
…
regbankselect-abs.mir
…
regbankselect-add.mir
[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)
2025-10-30 11:45:02 -04:00
regbankselect-add.s16.mir
[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)
2025-10-30 11:45:02 -04:00
regbankselect-add.s32.mir
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
regbankselect-add.v2s16.mir
[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)
2025-10-30 11:45:02 -04:00
regbankselect-amdgcn-exp-compr.mir
…
regbankselect-amdgcn-exp.mir
…
regbankselect-amdgcn-s-buffer-load.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ballot.i64.mir
…
regbankselect-amdgcn.class.mir
…
regbankselect-amdgcn.cvt.pkrtz.mir
…
regbankselect-amdgcn.div.fmas.mir
…
regbankselect-amdgcn.div.scale.mir
…
regbankselect-amdgcn.ds.append.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.bpermute.mir
…
regbankselect-amdgcn.ds.consume.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.gws.init.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.gws.sema.v.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.ordered.add.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.ordered.swap.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.permute.mir
…
regbankselect-amdgcn.ds.swizzle.mir
…
regbankselect-amdgcn.else.32.mir
…
regbankselect-amdgcn.else.64.mir
…
regbankselect-amdgcn.fcmp.mir
…
regbankselect-amdgcn.fmul.legacy.mir
[AMDGPU][GlobalISel] Add RegBankLegalize mul24 and fmul.legacy (#173123)
2025-12-23 12:35:28 -08:00
regbankselect-amdgcn.groupstaticsize.mir
[AMDGPU][GlobalISel] Add RegBankLegalize rules for groupstaticsize (#178618)
2026-01-29 11:00:44 -08:00
regbankselect-amdgcn.icmp.mir
…
regbankselect-amdgcn.image.load.1d.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
regbankselect-amdgcn.image.sample.1d.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
regbankselect-amdgcn.interp.mov.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p1.f16.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p1.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p2.f16.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p2.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.kernarg.segment.ptr.mir
…
regbankselect-amdgcn.kill.mir
…
regbankselect-amdgcn.lds.direct.load.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.lds.param.load.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.live.mask.mir
…
regbankselect-amdgcn.mfma.gfx90a.mir
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
regbankselect-amdgcn.mfma.gfx942.mir
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
regbankselect-amdgcn.mfma.mir
…
regbankselect-amdgcn.ps.live.mir
…
regbankselect-amdgcn.raw.buffer.load.ll
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
regbankselect-amdgcn.raw.ptr.buffer.load.ll
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
regbankselect-amdgcn.readfirstlane.mir
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
regbankselect-amdgcn.readlane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.s.buffer.load.ll
[AMDGPU][GFX1250] Implement offset handling in s.buffer.load (#178389)
2026-01-29 18:00:48 +09:00
regbankselect-amdgcn.s.buffer.load.mir
…
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
…
regbankselect-amdgcn.s.getpc.mir
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
regbankselect-amdgcn.s.getreg.mir
…
regbankselect-amdgcn.s.memrealtime.mir
…
regbankselect-amdgcn.s.memtime.mir
…
regbankselect-amdgcn.s.sendmsg.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.s.sendmsghalt.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.struct.buffer.load.ll
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
regbankselect-amdgcn.struct.buffer.store.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
regbankselect-amdgcn.struct.ptr.buffer.load.ll
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
regbankselect-amdgcn.struct.ptr.buffer.store.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
regbankselect-amdgcn.update.dpp.mir
…
regbankselect-amdgcn.wqm.demote.mir
…
regbankselect-amdgcn.wqm.mir
…
regbankselect-amdgcn.wqm.vote.mir
…
regbankselect-amdgcn.writelane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.wwm.mir
[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_wwm/strict_wwm (#178615)
2026-01-30 08:26:59 -08:00
regbankselect-amdgpu-ffbh-u32.mir
…
regbankselect-amdgpu-ffbl-b32.mir
…
regbankselect-amdgpu-wave-address.mir
[AMDGPU][GISel] Add RegBankLegalize support for G_AMDGPU_WAVE_ADDRESS (#167456)
2025-11-11 16:37:42 -08:00
regbankselect-and-s1.mir
AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)
2025-07-23 16:44:53 +02:00
regbankselect-and.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (#132382)
2025-05-26 12:07:46 +02:00
regbankselect-anyext.mir
AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)
2025-07-23 16:44:53 +02:00
regbankselect-ashr.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
regbankselect-assert-align.mir
…
regbankselect-assert-sext.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)
2025-10-10 08:48:06 -07:00
regbankselect-assert-zext.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (#162728)
2025-10-10 08:48:06 -07:00
regbankselect-atomic-cmpxchg.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ATOMIC_CMPXCHG (#178066)
2026-01-27 09:02:33 -08:00
regbankselect-atomicrmw-add-sub.mir
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
regbankselect-atomicrmw-add.mir
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
regbankselect-atomicrmw-and.mir
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
regbankselect-atomicrmw-fadd.mir
[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)
2026-02-09 15:37:27 +00:00
regbankselect-atomicrmw-fadd.v2f16.mir
[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)
2026-02-09 15:37:27 +00:00
regbankselect-atomicrmw-max.mir
…
regbankselect-atomicrmw-min.mir
…
regbankselect-atomicrmw-minmax-uminmax.mir
[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)
2026-02-10 16:04:05 +05:30
regbankselect-atomicrmw-or.mir
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
regbankselect-atomicrmw-sub.mir
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
regbankselect-atomicrmw-uinc-udec-wrap.mir
[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)
2026-02-10 16:04:05 +05:30
regbankselect-atomicrmw-umax.mir
…
regbankselect-atomicrmw-umin.mir
…
regbankselect-atomicrmw-xchg.mir
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
regbankselect-atomicrmw-xor.mir
[AMDGPU] Add legalization rules for atomic ops (#175253)
2026-01-16 23:01:24 -05:00
regbankselect-bitcast.mir
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
regbankselect-bitreverse.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BITREVERSE (#172101)
2025-12-15 17:45:33 -08:00
regbankselect-block-addr.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BLOCK_ADDR and G_GLOBAL_VALUE (#165340)
2025-11-11 09:31:59 -08:00
regbankselect-brcond.mir
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
regbankselect-bswap.mir
…
regbankselect-build-vector.mir
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
regbankselect-concat-vector.mir
…
regbankselect-constant.mir
…
regbankselect-copy.mir
AMDGPU: Fixes for regbankselecting copies of i1 physregs to sgprs (#159283)
2025-09-17 19:48:39 +09:00
regbankselect-ctlz-zero-undef.mir
…
regbankselect-ctpop.mir
…
regbankselect-cttz-zero-undef.mir
…
regbankselect-default.mir
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
regbankselect-dyn-stackalloc.mir
[AMDGPU] Support divergent sized dynamic alloca (#121148)
2025-01-06 12:28:24 +07:00
regbankselect-extract-vector-elt.mir
…
regbankselect-extract.mir
…
regbankselect-fabs.mir
…
regbankselect-fadd.mir
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
regbankselect-fcanonicalize.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FCANONICALIZE (#174662)
2026-01-09 08:51:16 -08:00
regbankselect-fceil.mir
[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)
2026-02-05 16:35:31 +00:00
regbankselect-fcmp.mir
…
regbankselect-fexp2.mir
[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)
2026-02-05 16:35:31 +00:00
regbankselect-ffloor.mir
[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)
2026-02-05 16:35:31 +00:00
regbankselect-flog2.mir
[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)
2026-02-05 16:35:31 +00:00
regbankselect-fma.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMAD, G_FMA (#172941)
2025-12-22 09:05:31 -08:00
regbankselect-fmul.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMUL (#167847)
2025-11-17 08:45:49 -08:00
regbankselect-fneg.mir
…
regbankselect-fpext.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPEXT (#171483)
2025-12-10 08:58:27 -08:00
regbankselect-fptosi.mir
[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp (#176300)
2026-02-03 11:45:49 -06:00
regbankselect-fptoui.mir
[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp (#176300)
2026-02-03 11:45:49 -06:00
regbankselect-fptrunc.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPTRUNC (#171723)
2025-12-18 13:16:46 -08:00
regbankselect-frame-index.mir
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
regbankselect-freeze.mir
…
regbankselect-fshr.mir
…
regbankselect-fsqrt.mir
AMDGPU/GlobalISel: Regbanklegalize rules for G_FSQRT (#179817)
2026-02-09 18:24:28 -08:00
regbankselect-fsub.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FSUB (#171244)
2025-12-11 11:55:28 -08:00
regbankselect-icmp.mir
…
regbankselect-icmp.s16.mir
…
regbankselect-illegal-copy.mir
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
regbankselect-implicit-def.mir
…
regbankselect-insert-vector-elt.mir
…
regbankselect-insert.mir
…
regbankselect-intrinsic-roundeven.mir
[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)
2026-02-05 16:35:31 +00:00
regbankselect-intrinsic-trunc.mir
[AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (#179954)
2026-02-05 16:35:31 +00:00
regbankselect-inttoptr.mir
[AMDGPU] New RegBankSelect: Add rules for G_PTRTOINT and G_INTTOPTR (#142604)
2025-06-19 10:21:17 +02:00
regbankselect-load.mir
AMDGPU: Use ConstantPool as source value for DAG lowered kernarg loads (#168917)
2025-12-02 15:48:02 +00:00
regbankselect-lshr.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
regbankselect-mad_64_32.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-merge-values.mir
…
regbankselect-mui-regbanklegalize.mir
MachineUniformityAnalysis: Improve isConstantOrUndefValuePhi (#112866)
2025-01-24 12:43:40 +01:00
regbankselect-mui-regbankselect.mir
AMDGPU/GlobalISel: Disable LCSSA pass (#124297)
2025-03-12 11:09:50 +01:00
regbankselect-mui-salu-float.ll
AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)
2025-01-24 12:12:45 +01:00
regbankselect-mui-salu-float.mir
AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)
2025-01-24 12:12:45 +01:00
regbankselect-mui.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
regbankselect-mui.mir
AMDGPU/GlobalISel: Disable LCSSA pass (#124297)
2025-03-12 11:09:50 +01:00
regbankselect-mul.mir
Reland "[AMDGPU][GlobalISel] Add RegBankLegalize support for G_MUL (#… (#177481)
2026-01-22 14:59:52 -08:00
regbankselect-or.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (#132382)
2025-05-26 12:07:46 +02:00
regbankselect-phi-s1.mir
…
regbankselect-phi.mir
…
regbankselect-pseudo-scalar-transcendental.mir
…
regbankselect-ptr-add.mir
AMDGPU/GlobalISel: Add regbanklegalize rules for ptr-add (#153175)
2025-08-13 15:49:48 +02:00
regbankselect-ptrmask.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_PTRMASK (#174889)
2026-01-09 08:51:51 -08:00
regbankselect-ptrtoint.mir
[AMDGPU] New RegBankSelect: Add rules for G_PTRTOINT and G_INTTOPTR (#142604)
2025-06-19 10:21:17 +02:00
regbankselect-reg-sequence.mir
…
regbankselect-sadde.mir
[AMDGPU][GlobalISel] Add G_SADDE/SSUBE RegBankLegalize rule (#179603)
2026-02-04 09:41:27 -08:00
regbankselect-salu-float.mir
…
regbankselect-sbfx.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)
2025-05-26 11:58:57 +02:00
regbankselect-select.mir
[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule (#142560)
2025-06-19 09:56:07 +02:00
regbankselect-sext-inreg.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
regbankselect-sext.mir
[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)
2025-10-30 11:45:02 -04:00
regbankselect-sextload.mir
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
regbankselect-shl.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
regbankselect-sitofp.mir
[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp (#176300)
2026-02-03 11:45:49 -06:00
regbankselect-smax.mir
[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)
2025-10-10 14:34:15 +02:00
regbankselect-smin.mir
[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)
2025-10-10 14:34:15 +02:00
regbankselect-smulh.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_UMULH, G_SMULH (#174555)
2026-01-08 13:57:57 -08:00
regbankselect-split-scalar-load-metadata.mir
AMDGPU: Use ConstantPool as source value for DAG lowered kernarg loads (#168917)
2025-12-02 15:48:02 +00:00
regbankselect-ssube.mir
[AMDGPU][GlobalISel] Add G_SADDE/SSUBE RegBankLegalize rule (#179603)
2026-02-04 09:41:27 -08:00
regbankselect-sub.mir
[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)
2025-10-30 11:45:02 -04:00
regbankselect-trunc.mir
[AMDGPU][GlobalISel] Fix G_TRUNC S16 to VCC for pre-GFX8 targets (#176254)
2026-01-16 08:00:42 -08:00
regbankselect-uadde.mir
…
regbankselect-uaddo.mir
…
regbankselect-ubfx.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)
2025-05-26 11:58:57 +02:00
regbankselect-uitofp.mir
[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp (#176300)
2026-02-03 11:45:49 -06:00
regbankselect-umax.mir
[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)
2025-10-10 14:34:15 +02:00
regbankselect-umin.mir
[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)
2025-10-10 14:34:15 +02:00
regbankselect-umulh.mir
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_UMULH, G_SMULH (#174555)
2026-01-08 13:57:57 -08:00
regbankselect-uniform-load-noclobber.mir
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
regbankselect-unmerge-values.mir
…
regbankselect-usube.mir
…
regbankselect-usubo.mir
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regbankselect-waterfall-agpr.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-whole-wave-functions.mir
[AMDGPU] ISel & PEI for whole wave functions (#145858)
2025-07-21 10:39:09 +02:00
regbankselect-widen-scalar-loads.mir
AMDGPU: Use ConstantPool as source value for DAG lowered kernarg loads (#168917)
2025-12-02 15:48:02 +00:00
regbankselect-xor.mir
AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (#132382)
2025-05-26 12:07:46 +02:00
regbankselect-zext.mir
[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (#159860)
2025-10-30 11:45:02 -04:00
regbankselect-zextload.mir
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
regbankselect.mir
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
saddsat.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
sbfx.ll
AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)
2025-05-26 11:58:57 +02:00
sdiv.i32.ll
[GlobaISel] Allow expanding of sdiv -> mul by constant (#146504)
2025-07-14 15:01:12 +01:00
sdiv.i64.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
sdivrem.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
select-to-fmin-fmax.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
selected-inst-flags.mir
[GlobalISel] Fix silently dropped MIFlags on selected instructions (#138851)
2025-05-07 14:07:16 +02:00
sext_inreg.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
shader-epilogs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shl-ext-reduce.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
shl.ll
[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)
2026-01-30 15:13:33 +00:00
shufflevector-pointer-crash.mir
[GlobalISel] Make scalar G_SHUFFLE_VECTOR illegal. (#140508)
2025-10-24 08:21:35 +01:00
shufflevector.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
smed3.ll
[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)
2025-10-10 14:34:15 +02:00
smrd.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
smul.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_S_MUL_* (#176842)
2026-01-21 08:58:35 -08:00
srem.i32.ll
[GlobalISel] Allow expansion of srem by constant in prelegalizer (#148845)
2025-07-17 14:43:58 +01:00
srem.i64.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
ssubsat.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
store-divergent-addr.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
store-local.96.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
store-local.128.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
store-uniform-addr.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
store-weird-size.ll
[AMDGPU] Narrow only on store to pow of 2 mem location (#150093)
2025-08-19 00:04:27 +09:00
strict_fma.f16.ll
Adding support for G_STRICT_FMA in new reg bank select (#170330)
2026-02-06 15:43:37 +05:30
strict_fma.f32.ll
Adding support for G_STRICT_FMA in new reg bank select (#170330)
2026-02-06 15:43:37 +05:30
strict_fma.f64.ll
Adding support for G_STRICT_FMA in new reg bank select (#170330)
2026-02-06 15:43:37 +05:30
sub.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
sub.v2i16.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
subo.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
trunc.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
twoaddr-extract-dyn-v7f64.mir
…
uaddsat.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)
2026-02-02 17:55:42 +01:00
ubfx.ll
AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (#132381)
2025-05-26 11:58:57 +02:00
udiv.i32.ll
…
udiv.i64.ll
[GlobalISel] add KnownBits tracking for G_UMULH and G_SMULH (#158445)
2025-10-10 18:42:14 +09:00
udivrem.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
umed3.ll
[AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (#159821)
2025-10-10 14:34:15 +02:00
unmerge-sgpr-s16.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)
2026-02-02 17:55:42 +01:00
unmerge-sgpr-s16.mir
AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize (#179441)
2026-02-04 10:20:30 +00:00
unsupported-load.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
unsupported-ptr-add.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
urem.i32.ll
[GlobalISel] Allow expansion of urem by constant in prelegalizer (#145914)
2025-07-02 13:46:36 +01:00
urem.i64.ll
[GlobalISel] add KnownBits tracking for G_UMULH and G_SMULH (#158445)
2025-10-10 18:42:14 +09:00
usubsat.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)
2026-02-02 17:55:42 +01:00
v_bfe_i32.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
vni8-across-blocks.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
widen-i8-i16-scalar-loads.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w32-imm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w32-iu-modifiers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w32-swmmac-index_key.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w64-imm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w64-iu-modifiers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w64-swmmac-index_key.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
xnor.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
xor.ll
[GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (#138574)
2025-05-08 19:31:28 +02:00
zextload.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00