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llvm-project/llvm/test/CodeGen/AMDGPU
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Ivan Kosarev 9e55d81c68
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316) 
And rework the lit64() support to use it.

The rules for when to add lit64() can be simplified and
improved. In this change, however, we just follow the existing
conventions on the assembler and disassembler sides.

In codegen we do not (and normally should not need to) add explicit
lit() and lit64() modifiers, so the codegen tests lose them. The change
is an NFCI otherwise.

Simplifies printing operands.
2025-09-24 12:35:50 +01:00
..
GlobalISel
[GlobalISel] Add G_ABS computeKnownBits (#154413)
2025-09-21 11:55:08 +01:00
32-bit-local-address-space.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
a-v-ds-atomic-cmpxchg.ll
AMDGPU: Add agpr variants of multi-data DS instructions (#156420)
2025-09-04 09:13:36 +09:00
a-v-ds-atomicrmw.ll
AMDGPU: Add tests for atomics with AGPR operands (#155820)
2025-08-28 22:21:07 +09:00
a-v-flat-atomic-cmpxchg.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
a-v-flat-atomicrmw.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
a-v-global-atomic-cmpxchg.ll
AMDGPU: Fix using wrong type in i32 atomic cmpxchg test (#156988)
2025-09-05 00:56:11 +00:00
a-v-global-atomicrmw.ll
AMDGPU: Add more tests for flat/global atomicrmw with agprs (#156874)
2025-09-05 08:38:58 +09:00
aa-as-infer.ll
[Attributor] Use known non-flat AS before getAssumedAddrSpace (#143221)
2025-06-09 10:11:34 -04:00
aa-points-to-constant-memory.ll
…
abi-attribute-hints-undefined-behavior.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
abs_i16.ll
[AMDGPU][True16][CodeGen] enable true16 for more codegen test patch 1 (#131206)
2025-03-14 14:57:42 -04:00
acc-ldst.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
accvgpr-copy.mir
AMDGPU: Fix introducing use of killed vgpr in gfx908 agpr copy (#149291)
2025-07-18 15:34:47 +09:00
accvgpr-spill-scc-clobber.mir
[AMDGPU] Remove implicit definition of register group when restoring the last sub-register after a spill (#133986)
2025-05-05 20:17:36 +02:00
add3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
add64-low-32-bits-known-zero.ll
Reapply "[AMDGPU] Insert readfirstlane in the function returns in sgpr." (#136678)
2025-04-22 17:48:55 +05:30
add_i1.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
add_i64.ll
[AMDGPU] Update codegen tests for PR #154069 (#154862)
2025-08-22 07:58:21 -06:00
add_i128.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
add_shl.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
add_sub_u64_pseudos.mir
…
add_u64.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
add-debug.ll
…
add-max.ll
[AMDGPU] Add gfx1250 V_ADD_{MIN|MAX}_{U|I}32 instructions (#151379)
2025-07-30 13:12:14 -07:00
add.i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
add.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
add.v2i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
addrspacecast-captured.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
addrspacecast-constantexpr.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
addrspacecast-gas.ll
[AMDGPU] Fold copies of constant physical registers into their uses (#154410)
2025-09-17 10:49:34 -07:00
addrspacecast-initializer-unsupported.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
addrspacecast-initializer.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
addrspacecast-known-non-null.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
addrspacecast.gfx6.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
addrspacecast.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
addrspacecast.r600.ll
AMDGPU: Replace ptr undef in tests with poison (#131050)
2025-03-13 13:34:52 +07:00
addsub64_carry.ll
[NFC][AMDGPU] Pre-commit test for setcc removal by using add/sub carryout (#155118)
2025-09-04 09:27:11 -05:00
adjust-writemask-cse.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
adjust-writemask-invalid-copy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
adjust-writemask-vectorized.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
agpr-copy-no-free-registers-assertion-after-ra-failure.ll
AMDGPU: Replace amdgpu-no-agpr with amdgpu-agpr-alloc (#129893)
2025-03-06 09:17:51 +07:00
agpr-copy-no-free-registers.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
agpr-copy-no-vgprs.mir
…
agpr-copy-propagation.mir
…
agpr-copy-reuse-writes.mir
[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM (#130550)
2025-04-29 13:13:45 +05:30
agpr-copy-sgpr-no-vgprs.mir
…
agpr-csr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
agpr-register-count.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
agpr-remat.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
agpr-spill-copy.mir
[AMDGPU] Remove implicit definition of register group when restoring the last sub-register after a spill (#133986)
2025-05-05 20:17:36 +02:00
agpr-to-agpr-copy.mir
[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)
2025-02-11 11:09:38 +05:30
alignbit-pat.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
alloc-aligned-tuples-gfx90a.mir
[CodeGen][NPM] Port VirtRegRewriter to NPM (#130564)
2025-04-30 14:10:46 +05:30
alloc-aligned-tuples-gfx908.mir
…
alloc-aligned-tuples-gfx1250.mir
[AMDGPU] Require aligned VGPRs for gfx1250 (#145561)
2025-06-24 12:16:01 -07:00
alloc-all-regs-reserved-in-class.mir
RegAlloc: Do not fatal error if there are no registers in the alloc order (#119640)
2024-12-16 10:52:49 +09:00
alloca.ll
…
allow-check.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
always-uniform.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amd.endpgm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgcn-call-whole-wave.ll
[AMDGPU] Tail call support for whole wave functions (#145860)
2025-09-04 10:34:43 +02:00
amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
amdgcn-ieee.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgcn-load-offset-from-reg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgcn.bitcast.16bit.ll
[AMDGPU][True16][Codegen] remove packed build_vector pattern from true16 (#148715)
2025-07-18 12:55:11 -04:00
amdgcn.bitcast.32bit.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
amdgcn.bitcast.48bit.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
amdgcn.bitcast.64bit.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
amdgcn.bitcast.96bit.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
amdgcn.bitcast.128bit.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
amdgcn.bitcast.160bit.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
amdgcn.bitcast.192bit.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
amdgcn.bitcast.224bit.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
amdgcn.bitcast.256bit.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
amdgcn.bitcast.288bit.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
amdgcn.bitcast.320bit.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
amdgcn.bitcast.352bit.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
amdgcn.bitcast.384bit.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
amdgcn.bitcast.448bit.ll
[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)
2025-05-16 10:31:03 +02:00
amdgcn.bitcast.512bit.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
amdgcn.bitcast.576bit.ll
[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)
2025-07-09 16:17:14 -04:00
amdgcn.bitcast.640bit.ll
[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)
2025-07-09 16:17:14 -04:00
amdgcn.bitcast.704bit.ll
[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)
2025-07-09 16:17:14 -04:00
amdgcn.bitcast.768bit.ll
[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)
2025-07-09 16:17:14 -04:00
amdgcn.bitcast.832bit.ll
[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)
2025-07-09 16:17:14 -04:00
amdgcn.bitcast.896bit.ll
[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)
2025-07-09 16:17:14 -04:00
amdgcn.bitcast.960bit.ll
[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)
2025-07-09 16:17:14 -04:00
amdgcn.bitcast.1024bit.ll
Greedy: Take copy hints involving subregisters (#159570)
2025-09-19 09:37:36 +09:00
amdgcn.bitcast.ptr.ll
AMDGPU: Add sgpr bit convert tests (#136112)
2025-05-14 09:55:37 +08:00
amdgcn.private-memory.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgpu-alias-analysis.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
[AMDGPU] Remove AAInstanceInfo from the AMDGPUAttributor (#150232)
2025-07-24 17:12:04 +02:00
amdgpu-attributor-no-agpr.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
amdgpu-branch-weight-metadata.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
amdgpu-codegenprepare-break-large-phis-heuristics.ll
AMDGPU: Replace tests using undef in shufflevector with poison (#130899)
2025-03-12 20:45:02 +07:00
amdgpu-codegenprepare-break-large-phis.ll
AMDGPU: Replace undef phi inputs with poison in tests (#130267)
2025-03-08 07:14:29 +07:00
amdgpu-codegenprepare-fdiv.ll
AMDGPU: Replace some float undef test uses with poison (#131090)
2025-03-13 20:07:48 +07:00
amdgpu-codegenprepare-fold-binop-select.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
amdgpu-codegenprepare-idiv.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
amdgpu-codegenprepare-mul24.ll
Re apply 130577 narrow math for and operand (#133896)
2025-04-17 17:03:32 +08:00
amdgpu-codegenprepare-sqrt.ll
…
amdgpu-cs-chain-cc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgpu-cs-chain-preserve-cc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgpu-export-kernel-runtime-handles.ll
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
amdgpu-function-calls-option.ll
…
amdgpu-inline.ll
AMDGPU: Mark workitem ID intrinsics with range attribute (#136196)
2025-04-18 12:27:38 +02:00
amdgpu-late-codegenprepare-crash-splat.ll
[AMDGPU] Visit all PHIs in each call to optimizeLiveType (#147522)
2025-07-10 09:29:48 +02:00
amdgpu-late-codegenprepare.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
amdgpu-libcall-sincos-pass-ordering.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
amdgpu-llvm-debuginfo-analyzer.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
amdgpu-max-num-workgroups-load-annotate.ll
AMDGPU: Mark grid size loads with range metadata (#113019)
2024-12-09 11:01:55 -05:00
amdgpu-mul24-knownbits.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgpu-no-agprs-violations.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
amdgpu-nsa-threshold.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgpu-num-agpr.ll
AMDGPU: Replace amdgpu-no-agpr with amdgpu-agpr-alloc (#129893)
2025-03-06 09:17:51 +07:00
amdgpu-prepare-agpr-alloc.mir
AMDGPU: Start using AV_MOV_B64_IMM_PSEUDO (#154500)
2025-08-22 13:59:36 +09:00
amdgpu-reloc-const.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgpu-shader-calling-convention.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgpu-simplify-libcall-ceil.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-copysign.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-exp2.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-exp.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-fabs.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-floor.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-fma.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-fmax-splat.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-fmax.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-fmin-splat.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-fmin.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-image-function-signatures.ll
AMDGPU: Fix libcall recognition of image array types (#119832)
2024-12-16 15:04:53 +09:00
amdgpu-simplify-libcall-ldexp-splat.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-ldexp.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-log2.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-log10.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-log.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-mad.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-pow-codegen.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
amdgpu-simplify-libcall-pow.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-pown.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-powr.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-rint.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-rootn.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-round.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-sincos.defined.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-sincos.defined.nobuiltin.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
amdgpu-simplify-libcall-sincos.defined.sin.cos.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-sincos.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-sincos.nobuiltins.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-sincos.weak.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-sqrt.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-trunc.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
amdgpu-simplify-libcall-unexpected-types.ll
AMDGPU: Do not assert on unhandled types when demangling libcalls (#120068)
2024-12-16 20:27:06 +07:00
amdgpu-snop-padding.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
…
amdgpu-sw-lower-lds-dynamic-indirect-access.ll
…
amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
…
amdgpu-sw-lower-lds-dynamic-lds-test.ll
…
amdgpu-sw-lower-lds-lower-all.ll
[AMDGPU] Lower LDS in functions without sanitize_address in amdgpu-sw-lower-lds. (#131147)
2025-04-09 11:55:55 +05:30
amdgpu-sw-lower-lds-lower-none.ll
[AMDGPU] Lower LDS in functions without sanitize_address in amdgpu-sw-lower-lds. (#131147)
2025-04-09 11:55:55 +05:30
amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
…
amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access.ll
…
amdgpu-sw-lower-lds-multiple-blocks-return-asan.ll
…
amdgpu-sw-lower-lds-multiple-blocks-return.ll
…
amdgpu-sw-lower-lds-non-kernel-declaration.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
…
amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
…
amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
…
amdgpu-sw-lower-lds-static-dynamic-lds-test.ll
…
amdgpu-sw-lower-lds-static-indirect-access-asan.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
…
amdgpu-sw-lower-lds-static-indirect-access-function-param.ll
…
amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
[AMDGPU] Lower LDS in functions without sanitize_address in amdgpu-sw-lower-lds. (#131147)
2025-04-09 11:55:55 +05:30
amdgpu-sw-lower-lds-static-indirect-access-lower-none.ll
[AMDGPU] Lower LDS in functions without sanitize_address in amdgpu-sw-lower-lds. (#131147)
2025-04-09 11:55:55 +05:30
amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-indirect-access-nested.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-indirect-access.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
[AMDGPU] Remove amdgpu-no-heap-ptr and amdgpu-no-lds-kernel-id attributes from lowered kernels in amdgpu-sw-lower-lds pass (#120887)
2024-12-23 12:42:31 +05:30
amdgpu-sw-lower-lds-static-lds-O0.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-sw-lower-lds-static-lds-test-asan.ll
…
amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
…
amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
…
amdgpu-sw-lower-lds-static-lds-test.ll
[AMDGPU] Add amdgpu-sw-lower-lds pass to NPM codegen addIRPasses. (#124102)
2025-01-24 11:15:30 +05:30
amdgpu-sw-lower-lds-static-lds-vector-ptrs.ll
[AMDGPU] Handle lowering addrspace casts from LDS to FLAT address in amdgpu-sw-lower-lds. (#121214)
2025-02-19 08:50:23 +05:30
amdgpu-unroll-threshold.ll
…
amdgpu.private-memory.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdgpu.work-item-intrinsics.deprecated.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdhsa-kernarg-preload-num-sgprs.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
amdhsa-trap-num-sgprs.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
amdpal_scratch_mergedshader.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-callable.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-chain-metadata.ll
…
amdpal-cs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-elf.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
amdpal-es.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-gs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-hs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-ls.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-metadata-agpr-register-count.ll
…
amdpal-msgpack-cs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-default.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-denormal.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-dx10-clamp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-es.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-gs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-hs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-ieee.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-ls.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-ps.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-psenable.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-msgpack-vs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-ps.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-psenable.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-usersgpr-init.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal-vs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
amdpal.ll
[AMDGPU] Promote nestedGEP allocas to vectors (#141199)
2025-06-02 16:20:14 +08:00
and_or.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
and-gcn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
and.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
and.r600.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
andorbitset.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
andorn2.ll
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
2025-09-03 20:04:01 +01:00
andorxorinvimm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
annotate-existing-abi-attributes.ll
[AMDGPU][Attributor] Remove final update of waves-per-eu after the attributor run (#155246)
2025-08-27 14:11:03 -04:00
annotate-kernel-features-hsa-call.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
annotate-kernel-features-hsa.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
annotate-kernel-features.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
annotate-noclobber.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
anonymous-gv.ll
…
any_extend_vector_inreg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
anyext.ll
[AMDGPU] Use "v_bfi_b32 x, 0, z" to implement (z & ~x) (#156636)
2025-09-03 11:00:03 +00:00
are-loads-from-same-base-ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
array-ptr-calc-i32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
array-ptr-calc-i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
artificial-terminators.mir
…
ashr64_reduce_flags.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
ashr64_reduce.ll
[AMDGPU] Convert 64-bit sra to 32-bit if shift amt >= 32 (#144421)
2025-06-26 14:22:59 -04:00
ashr.v2i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
asm-printer-check-vcc.mir
Register assembly printer passes (#138348)
2025-05-06 18:01:17 -07:00
at-least-one-def-value-assert.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
atomic_cmp_swap_local.ll
[AMDGPU] Update codegen tests for PR #154069 (#154862)
2025-08-22 07:58:21 -06:00
atomic_load_add.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomic_load_local.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomic_load_sub.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomic_optimization_split_dt_update.ll
…
atomic_optimizations_buffer.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomic_optimizations_global_pointer.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
atomic_optimizations_local_pointer.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
atomic_optimizations_pixelshader.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomic_optimizations_raw_buffer.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomic_optimizations_struct_buffer.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomic_store_local.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomic-optimizer-promote-i8.ll
AMDGPU: Fix creating illegally typed readfirstlane in atomic optimizer (#128388)
2025-02-24 18:39:49 +07:00
atomic-optimizer-strict-wqm.ll
…
atomicrmw-bf16-gfx11plus.ll
[AMDGPU][True16][Codegen] remove packed build_vector pattern from true16 (#148715)
2025-07-18 12:55:11 -04:00
atomicrmw-expand.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
atomicrmw-nand.ll
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
2025-09-03 20:04:01 +01:00
atomics_cond_sub.ll
[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)
2025-08-12 09:35:19 +02:00
atomics-cas-remarks-gfx90a.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomics-hw-remarks-gfx90a.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
atomics-system-scope.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
attr-amdgpu-flat-work-group-size-vgpr-limit.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
attr-amdgpu-flat-work-group-size.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
attr-amdgpu-max-num-workgroups-propagate.ll
[AMDGPU][Attributor] Remove final update of waves-per-eu after the attributor run (#155246)
2025-08-27 14:11:03 -04:00
attr-amdgpu-max-num-workgroups.ll
…
attr-amdgpu-num-sgpr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
attr-amdgpu-num-vgpr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
attr-amdgpu-num-workgroups_error_check.ll
…
attr-amdgpu-waves-per-eu.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
attr-unparseable.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
attributor-flatscratchinit-globalisel.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
attributor-flatscratchinit-undefined-behavior2.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
attributor-flatscratchinit-undefined-behavior.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
attributor-flatscratchinit.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
attributor-loop-issue-58639.ll
[AMDGPU][Attributor] Remove final update of waves-per-eu after the attributor run (#155246)
2025-08-27 14:11:03 -04:00
attributor-noalias-addrspace.ll
Revert "[AMDGPU][Attributor] Infer inreg attribute in AMDGPUAttributor (#146720)"
2025-08-18 22:59:52 -04:00
attributor-noopt.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
av_movimm_pseudo_expansion.mir
AMDGPU: Special case align requirement for AV_MOV_B64_IMM_PSEUDO
2025-09-04 09:55:39 +09:00
av_spill_cross_bb_usage.mir
[AMDGPU] Remove implicit definition of register group when restoring the last sub-register after a spill (#133986)
2025-05-05 20:17:36 +02:00
av-spill-expansion-with-machine-cp.mir
[AMDGPU] Mark AGPR tuple implicit in the first instr of AGPR spills. (#115285)
2024-12-12 19:47:17 +05:30
av-split-dead-valno-crash.ll
Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)
2025-09-23 17:36:02 +01:00
back-off-barrier-subtarget-feature.ll
[AMDGPU] Reenable BackOffBarrier on GFX11/12 (#155370)
2025-09-02 09:37:43 +02:00
bad-agpr-vgpr-regalloc-priority.mir
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
barrier-elimination-gfx12.ll
[AMDGPU] Optimize out s_barrier_signal/_wait (#116993)
2024-11-26 10:04:32 +01:00
barrier-elimination.ll
…
basic-branch.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
basic-call-return.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
basic-loop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bb-prolog-spill-during-regalloc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bf16-conversions.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
bf16-math.ll
[AMDGPU] Removed extra blank lines from tests. NFC. (#152612)
2025-08-08 00:53:00 -07:00
bf16-ops.ll
…
bf16.ll
[AMDGPU] Add gfx1250 runline to bf16.ll. NFC (#160241)
2025-09-23 00:37:13 -07:00
bfe_uint.ll
…
bfe-combine.ll
…
bfe-patterns.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bfi_int.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
bfi_int.r600.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
bfi_nested.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bfm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
big_alu.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
bit-op-reduce-width-known-bits.ll
AMDGPU: Try constant fold after folding immediate (#141862)
2025-06-10 11:44:44 +09:00
bitcast_vector_bigint.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
bitcast-constant-to-vector.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bitcast-v4f16-v4i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bitcast-vector-extract.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bitop3.ll
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
2025-09-03 20:04:01 +01:00
bitreverse-inline-immediates.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bitreverse.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
blender-coalescer-verifier-error-empty-subrange.mir
[CodeGen][NewPM] Port RegisterCoalescer to NPM (#124698)
2025-02-03 13:41:51 +07:00
blender-no-live-segment-at-def-implicit-def.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
block-should-not-be-in-alive-blocks.mir
…
br_cc.f16.ll
AMDGPU: Replace copy-to-mov-imm folding logic with class compat checks (#154501)
2025-08-26 23:41:35 +09:00
branch-condition-and.ll
AMDGPU: Replace ptr addrspace(3) undef in tests with poison (#131049)
2025-03-13 13:28:55 +07:00
branch-folder-requires-no-phis.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
branch-folding-implicit-def-subreg.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
branch-relax-bundle.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
branch-relax-indirect-branch.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
branch-relax-no-terminators.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
branch-relax-spill.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
branch-relaxation-debug-info.mir
AMDGPU: Replace more undef test pointer uses with poison (#131102)
2025-03-14 09:53:45 +07:00
branch-relaxation-gfx10-branch-offset-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
branch-relaxation-gfx1250.ll
[AMDGPU] Add gfx1250 v_wmma_scale[16]_f32_16x16x128_f8f6f4 MC support (#152014)
2025-08-04 14:20:12 -07:00
branch-relaxation-inst-size-gfx10.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
branch-relaxation-inst-size-gfx11.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
branch-relaxation.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
branch-uniformity.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
break-smem-soft-clauses.mir
[CodeGen][NPM] Port PostRAHazardRecognizer to NPM (#130066)
2025-04-09 16:36:22 +05:30
break-vmem-soft-clauses.mir
…
bswap.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-atomic-fadd.f32-no-rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-atomic-fadd.f32-rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-atomic-fadd.f64.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
buffer-atomic-fadd.v2f16-no-rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-atomic-fadd.v2f16-rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-fat-pointer-atomicrmw-fadd.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
buffer-fat-pointer-atomicrmw-fmax.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
buffer-fat-pointer-atomicrmw-fmin.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
buffer-fat-pointer-unsupported-errors.ll
AMDGPU: Start using LLVMContext errors in buffer fat pointer lowering (#142014)
2025-05-30 07:52:45 +02:00
buffer-fat-pointers-contents-legalization.ll
Reland: [GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements (#144661)
2025-06-18 13:04:24 +02:00
buffer-fat-pointers-memcpy.ll
AMDGPU: Always use AV spill pseudos on targets with AGPRs (#149099)
2025-07-18 15:31:50 +09:00
buffer-intrinsic-mmo-type.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
buffer-intrinsics-mmo-offsets.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-rsrc-ptr-ops.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
buffer-schedule.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bug-cselect-b64.ll
AMDGPU: Fix overly conservative immediate operand check (#127563)
2025-02-27 08:42:09 +07:00
bug-deadlanes.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bug-multi-operands-to-update-after-fold.mir
AMDGPU: Fix assert when multi operands to update after folding imm (#148205)
2025-07-16 06:37:08 -05:00
bug-sdag-emitcopyfromreg.ll
…
bug-sdag-scheduler-cycle.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bug-undef-spilled-agpr.mir
[AMDGPU] Ensure non-reserved CSR spilled regs are live-in (#146427)
2025-08-01 11:54:25 -05:00
bug-v4f64-subvector.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
bug-vopc-commute.ll
AMDGPU: Switch a test to generated checks which only tested labels (#131257)
2025-03-14 14:54:46 +07:00
build_vector-r600.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
build_vector.gfx11plus.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
build_vector.ll
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
build-vector-insert-elt-infloop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
build-vector-packed-partial-undef.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
bundle-breaks-phy-liveness.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
bundle-latency.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
bypass-div.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
byval-frame-setup.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
call_fs.ll
…
call-alias-register-usage0.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
call-alias-register-usage1.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
call-alias-register-usage2.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
call-alias-register-usage3.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
call-alias-register-usage-agpr.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
call-args-inreg-no-sgpr-for-csrspill-xfail.ll
[NFC][FIX] Add -verify-machineinstrs=0 explicitly to some test files
2025-07-23 19:12:46 -04:00
call-args-inreg.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
call-argument-types.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
call-c-function.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
call-constant.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
call-constexpr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
call-defs-mode-register.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
call-encoding.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
call-graph-register-usage.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
call-preserved-registers.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
call-reqd-group-size.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
call-return-types.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
call-skip.ll
…
call-waitcnt.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
call-waw-waitcnt.mir
[AMDGPU][NPM] Port SIInsertWaitcnts to NPM (#130061)
2025-03-24 21:36:45 +05:30
callee-frame-setup.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
callee-special-input-sgprs-fixed-abi.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
callee-special-input-vgprs-packed.ll
[AMDGPU] callee-special-input-vgprs.ll / callee-special-input-vgprs-packed.ll - regenerate test coverage (#159587)
2025-09-18 15:19:48 +00:00
callee-special-input-vgprs.ll
[AMDGPU] callee-special-input-vgprs.ll / callee-special-input-vgprs-packed.ll - regenerate test coverage (#159587)
2025-09-18 15:19:48 +00:00
calling-conventions.ll
[AMDGPU] Add few missing gfx1250 codegen tests. NFC (#155314)
2025-08-25 15:22:33 -07:00
captured-frame-index.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
carryout-selection.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
cayman-loop-bug.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
cc-sgpr-limit.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cc-sgpr-over-limit.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
cc-update.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
cf_end.ll
…
cf-loop-on-constant.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cf-stack-bug.ll
…
cgp-addressing-modes-flat.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
cgp-addressing-modes-gfx908.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
cgp-addressing-modes-gfx1030.ll
DAG: Use phi to create vregs instead of the constant input (#129464)
2025-03-04 14:44:54 +07:00
cgp-addressing-modes-smem.ll
…
cgp-addressing-modes.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
cgp-bitfield-extract.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
chain-hi-to-lo.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
change-scc-to-vcc.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
check-subtarget-features.ll
…
clamp-modifier.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
clamp-omod-special-case.mir
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
clamp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cluster_stores.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cluster-dims.ll
[AMDGPU] Add the support for .cluster_dims code object metadata (#158721)
2025-09-15 16:13:07 -04:00
cluster-flat-loads-postra.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
cluster-flat-loads.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
cmp_shrink.mir
[AMDGPU] Fix wrong reverse operations for v_cmpx_le_u32 (#146398)
2025-07-01 11:48:08 -04:00
cndmask-no-def-vcc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
coalesce-copy-to-agpr-to-av-registers.mir
[AMDGPU] Add aperture classes to VS_64 (#158823)
2025-09-16 11:15:50 -07:00
coalesce-identity-copies-undef-subregs.mir
…
coalesce-into-dead-subreg-copies.mir
…
coalesce-liveout-undef-copy.mir
…
coalesce-vgpr-alignment.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
coalescer_distribute.ll
AMDGPU: Use generated checks in coalescer_distribute.ll (#131276)
2025-03-14 18:21:55 +07:00
coalescer_remat.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
coalescer-early-clobber-subreg.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
coalescer-extend-pruned-subrange.mir
…
coalescer-identical-values-undef.mir
…
coalescer-remat-dead-use.mir
…
coalescer-removepartial-extend-undef-subrange.mir
…
coalescer-subranges-another-copymi-not-live.mir
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
coalescer-subranges-another-prune-error.mir
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
coalescer-subranges-prune-kill-copy.mir
…
coalescer-subreg-join.mir
…
coalescer-subregjoin-fullcopy.mir
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
coalescer-undef-subreg-use-invalid-lanemask.mir
RegisterCoalescer: Fix creating full / empty subrange on undef subreg use (#117936)
2024-11-28 11:12:19 -05:00
coalescer-with-subregs-bad-identical.mir
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
coalescing_makes_lanes_undef.mir
…
coalescing-subreg-was-undef-but-became-def.mir
…
coalescing-with-subregs-in-loop-bug.mir
[CodeGen][NewPM] Port RenameIndependentSubregs to NPM (#125192)
2025-02-05 17:54:57 +05:30
code-object-v3.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
code-size-estimate-gfx1250.ll
[AMDGPU] Add v_cvt_sr|pk_bf8|fp8_f16 gfx1250 instructions (#151415)
2025-07-30 17:24:45 -07:00
code-size-estimate.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
code-size-estimate.mir
[AMDGPU] Respect MBB alignment in the getFunctionCodeSize() (#127142)
2025-02-18 13:19:33 -08:00
codegen-internal-only-func.ll
…
codegen-prepare-addrmode-sext.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
codegen-prepare-addrspacecast-non-null-vector.ll
…
codegen-prepare-addrspacecast-non-null.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
collapse-endcf2.mir
…
collapse-endcf-broken.mir
[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)
2025-02-20 17:35:56 +05:30
collapse-endcf.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
collapse-endcf.mir
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
combine_andor_with_cmps.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
combine_vloads.ll
[AMDGPU] combine_vloads.ll regenerate test checks
2025-05-12 12:33:53 +01:00
combine-add-zext-xor.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
combine-and-sext-bool.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
combine-cond-add-sub.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
combine-ftrunc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
combine-reg-or-const.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
combine-sreg64-inits.mir
[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)
2025-02-11 11:09:38 +05:30
combine-vload-extract.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
comdat.ll
…
commute_modifiers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
commute-compares-scalar-float.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
commute-compares.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
commute-frame-index-operand.mir
…
commute-op-sel.mir
[AMDGPU] Add commute for some VOP3 inst (#121326)
2025-01-22 11:08:26 +07:00
commute-shifts.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
commute-vop3.mir
…
complex-folding.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
computeKnownBits-scalar-to-vector-crash.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
computeNumSignBits-mul.ll
…
concat_vectors.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
constant-address-space-32bit.ll
[SeparateConstOffsetFromGEP] Don't set unsound inbounds flag (#130616)
2025-03-18 12:30:20 +01:00
constant-fold-imm-immreg.mir
AMDGPU: Try constant fold after folding immediate (#141862)
2025-06-10 11:44:44 +09:00
constant-fold-mi-operands.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
constrained-shift.ll
AMDGPU: Check for subreg match when folding through reg_sequence (#140582)
2025-05-19 21:44:44 +02:00
control-flow-fastregalloc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
control-flow-optnone.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
convergence-laneops.ll
[AMDGPU] Correct -mcpu processor name in test (#145493)
2025-06-25 14:34:38 +05:30
convergence-tokens.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
convergent-inlineasm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
copy_phys_vgpr64.mir
[AMDGPU] Use v_mov_b64 in codegen on gfx1250 (#148272)
2025-07-11 22:16:50 -07:00
copy_to_scc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
copy-hoist-no-spills.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
copy-illegal-type.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
copy-overlap-sgpr-kill.mir
…
copy-overlap-vgpr-kill.mir
…
copy-phys-reg-implicit-operand-kills-subregs.mir
…
copy-to-reg-frameindex.ll
MachineLICM: Merge logic for implicit and explicit definitions.
2025-07-09 13:02:15 -07:00
copy-to-reg-scc-clobber.ll
…
copy-to-reg.ll
AMDGPU: Switch a test to generated checks
2025-03-07 13:18:50 +07:00
copy-vgpr-clobber-spill-vgpr.mir
AMDGPU: Replace amdgpu-no-agpr with amdgpu-agpr-alloc (#129893)
2025-03-06 09:17:51 +07:00
copyprop_regsequence_with_undef.mir
…
copysign-simplify-demanded-bits.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
couldnt-join-subrange-3.mir
…
cross-block-use-is-not-abi-copy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cse-convergent.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cse-phi-incoming-val.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
csr-gfx10.ll
…
csr-sgpr-spill-live-ins.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
ctlz_zero_undef.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ctlz.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ctpop16.ll
[DAG] Always use stack to promote bitcast when the source is vector (#151065)
2025-08-02 15:32:10 -07:00
ctpop64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ctpop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cttz_zero_undef.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cttz.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cube.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cvt_f32_ubyte.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
cvt_flr_i32_f32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
cvt_rpi_i32_f32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dag-divergence-atomic.ll
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
2025-09-03 20:04:01 +01:00
dag-divergence.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dag-preserve-disjoint-flag.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
dagcomb-extract-vec-elt-different-sizes.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
dagcomb-mullohi.ll
[AMDGPU] Extend SRA i64 simplification for shift amts in range [33:62] (#138913)
2025-05-30 16:21:38 +02:00
dagcomb-shuffle-vecextend-non2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dagcombine-fma-crash.ll
AMDGPU: Replace undef phi inputs with poison in tests (#130267)
2025-03-08 07:14:29 +07:00
dagcombine-fma-fmad.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dagcombine-fmul-sel.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
dagcombine-lshr-and-cmp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dagcombine-reassociate-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dagcombine-select.ll
[AMDGPU] Implement IR expansion for frem instruction (#130988)
2025-09-03 16:27:15 +02:00
dagcombine-setcc-select.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dagcombine-v1i8-extractvecelt-crash.ll
…
dagcombiner-bug-illegal-vec4-int-to-fp.ll
AMDGPU: Replace tests using undef in shufflevector with poison (#130899)
2025-03-12 20:45:02 +07:00
dbg-info-inline-at.ll
Reland: [MC] output inlined-at debug info (#106230) (#130306)
2025-03-11 09:43:14 -04:00
dbg-value-ends-sched-region.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
dbg-value-starts-sched-region.mir
[AMDGPU] Fix a crash by skipping DBG instrs at start of sched region (#131167)
2025-03-19 09:31:54 -04:00
dce-disjoint-intervals.mir
…
dead_bundle.mir
…
dead_copy.mir
[CodeGen][NewPM] Port MachineCopyPropagation to NPM (#125202)
2025-02-04 15:45:03 +05:30
dead-lane.mir
…
dead-machine-elim-after-dead-lane.ll
Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#136701)
2025-04-22 17:36:41 -04:00
debug_frame.ll
…
debug-value2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
debug-value-scheduler-crash.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
debug-value-scheduler-liveins.mir
[MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (#128739)
2025-02-27 11:27:07 +01:00
debug-value-scheduler.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
debug-value.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
debug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
default_amdhsa_code_object_version.ll
Reapply "[AMDGPU] Use COV6 by default (#118515)" (#130963)
2025-03-21 15:26:45 -04:00
default-flat-work-group-size-overrides-waves-per-eu.ll
…
default-fp-mode.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
detect-dead-lanes.mir
[CodeGen][NPM] Port DetectDeadLanes to NPM (#130567)
2025-03-12 11:22:02 +05:30
direct-indirect-call.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
directive-amdgcn-target.ll
[AMDGPU] Add gfx1251 subtarget (#159430)
2025-09-17 13:02:02 -07:00
disable_form_clauses.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
disable-preload-kernargs.ll
[AMDGPU] Add an option to completely disable kernel argument preload (#153975)
2025-08-18 09:44:20 -04:00
disconnected-predset-break-bug.ll
…
div_i128.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
div_v2i128.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
div-rem-by-constant-64.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
diverge-extra-formal-args.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
diverge-interp-mov-lower.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
diverge-switch-default.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
divergence-at-use.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
divergence-driven-abs.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
divergence-driven-bfe-isel.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
divergence-driven-bitreverse.ll
…
divergence-driven-buildvector.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
divergence-driven-ctlz-cttz.ll
…
divergence-driven-ctpop.ll
[InstrEmitter] Use AddOperand in EmitCopyToRegClassNode. (#146637)
2025-07-02 09:44:54 -07:00
divergence-driven-min-max.ll
…
divergence-driven-negsubinlineconst.ll
…
divergence-driven-not-isel.ll
…
divergence-driven-sext-inreg.ll
…
divergence-driven-trunc-to-i1.ll
…
divergence-driven-xnor.ll
…
divergent-branch-uniform-condition.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
divrem24-assume.ll
…
do-not-fold-copy.mir
[AMDGPU] Do not fold COPY with implicit operands (#136003)
2025-04-22 13:33:06 +02:00
do-not-unify-divergent-exit-nodes-with-musttail.ll
[AMDGPU] Don't unify divergent exit nodes with musttail calls (#126395)
2025-02-09 21:48:24 -05:00
dpp64_combine.ll
[AMDGPU] gfx1251 VOP3 dpp support (#159654)
2025-09-18 16:18:09 -07:00
dpp64_combine.mir
[AMDGPU] gfx1251 VOP1 dpp support (#159637)
2025-09-18 13:42:06 -07:00
dpp_combine_gfx11.mir
AMDGPU: Fix DPP combiner using isOperandLegal on incomplete inst (#155595)
2025-09-03 01:19:01 +09:00
dpp_combine_gfx1250.mir
[AMDGPU] Fix DPP combining into V_BITOP3_B32 (#153083)
2025-08-11 15:39:02 -07:00
dpp_combine-true16.mir
[AMDGPU][True16][CodeGen] Skip combineDpp with t16 instructions (#128918)
2025-03-31 10:18:25 -04:00
dpp_combine.ll
[AMDGPU] gfx1251 VOP2 dpp support (#159641)
2025-09-18 15:38:29 -07:00
dpp_combine.mir
…
drop-mem-operand-move-smrd.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ds_gws_align.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ds_permute_a_v.ll
AMDGPU: Define agpr versions of ds permute instructions (#156695)
2025-09-04 15:13:59 +09:00
ds_read2_offset_order.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ds_read2_superreg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ds_read2-gfx1250.ll
[AMDGPU] ds_read2/ds_write2 gfx1250 tests. NFC (#159824)
2025-09-19 14:27:30 -07:00
ds_read2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ds_read2st64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ds_write2_a_v.ll
AMDGPU: Add tests for ds_write2 formation with agprs (#155765)
2025-09-03 01:27:18 +00:00
ds_write2.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
ds_write2st64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ds-alignment.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
ds-combine-large-stride.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ds-combine-with-dependence.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ds-negative-offset-addressing-mode-loop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ds-sub-offset.ll
[DAG] Remove AssertZext if the input is masked (#146052)
2025-07-29 13:05:30 +02:00
ds-vectorization-alignment.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dst-sel-hazard.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
dual-source-blend-export.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
dummy-regalloc-priority-advisor.mir
RegAllocGreedy: Add dummy priority advisor for writing MIR tests (#121207)
2025-01-02 23:04:44 +07:00
dumpcode.ll
[AMDGPU] Add a regression test for -mattr=dumpcode (#116982)
2025-02-13 11:04:08 +00:00
duplicate-attribute-indirect.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
dvgpr_sym_fail_too_many_block_size_16_anon.ll
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
dvgpr_sym_fail_too_many_block_size_16.ll
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
dvgpr_sym.ll
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
dwarf-multi-register-use-crash.ll
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
dynamic_stackalloc.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
dynamic-vgpr-reserve-stack-for-cwsr.ll
[AMDGPU] AMDGPUPromoteAlloca: increase default max-regs to 32 (#155076)
2025-08-26 09:30:16 +09:00
early-if-convert-cost.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
early-if-convert.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
early-inline-alias.ll
…
early-inline.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
early-lis-two-address-partial-def.mir
…
early-tailduplicator-nophis.mir
…
early-tailduplicator-terminator.mir
…
early-term.mir
[AMDGPU][NPM] Port SILateBranchLowering to NPM (#130063)
2025-03-26 19:28:19 +05:30
eh_frame.ll
…
elf-header-flags-mach.ll
[AMDGPU] Add gfx1251 subtarget (#159430)
2025-09-17 13:02:02 -07:00
elf-header-flags-sramecc.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
elf-header-flags-xnack.ll
…
elf-header-osabi.ll
…
elf-notes.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
elf.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
elf.metadata.ll
…
elf.r600.ll
…
eliminate-frame-index-s-add-i32.mir
[AMDGPU] frame index elimination hit assertion for scavenged nonreg (#130287)
2025-03-17 19:33:07 +05:30
eliminate-frame-index-s-add-u32.mir
AMDGPU: Handle s_add_u32 in eliminateFrameIndex (#129628)
2025-03-05 08:09:46 +07:00
eliminate-frame-index-s-mov-b32.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
eliminate-frame-index-scalar-bit-ops.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
eliminate-frame-index-v-add-co-u32-wave32.mir
…
eliminate-frame-index-v-add-co-u32.mir
AMDGPU: Correct legal literal operand logic for multiple uses (#127594)
2025-02-18 19:58:42 +07:00
eliminate-frame-index-v-add-u32.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
else.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
emit-high-vgprs.mir
[AMDGPU] High VGPR emission tests. NFC. (#157534)
2025-09-08 16:17:22 -07:00
empty-function.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
empty-text.ll
MC,AMDGPU: Don't pad .text with s_code_end if it would otherwise be empty (#147980)
2025-08-06 13:25:45 +01:00
enable-no-signed-zeros-fp-math.ll
…
enable-scratch-only-dynamic-stack.ll
…
endcf-loop-header.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
endpgm-dce.mir
…
exceed-max-sgprs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
exec-mask-opt-cannot-create-empty-or-backward-segment.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
expand-atomicrmw-syncscope.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
expand-scalar-carry-out-select-user.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
expand-si-indirect.mir
…
expand-variadic-call.ll
[IR] Remove size argument from lifetime intrinsics (#150248)
2025-08-08 11:09:34 +02:00
export-cluster-postra.mir
[AMDGPU] Cluster export instructions in PostRA Scheduler (#141399)
2025-05-26 18:00:43 +09:00
extend-bit-ops-i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extend-phi-subrange-not-in-parent.mir
…
extend-wwm-virt-reg-liveness.mir
…
extload-align.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extload-private.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extload.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extra-lds-size.ll
[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)
2025-08-14 12:52:00 -07:00
extra-sroa-after-unroll.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
extract_subvector_vec4_vec3.ll
AMDGPU: Replace some test i32 undef uses with poison (#131092)
2025-03-13 20:10:17 +07:00
extract_vector_dynelt.ll
Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#135243)
2025-04-10 22:18:21 +02:00
extract_vector_elt-f16.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
extract_vector_elt-f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extract_vector_elt-i8.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
extract_vector_elt-i16.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
extract_vector_elt-i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extract-load-i1.ll
…
extract-lowbits.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extract-subvector-16bit.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extract-subvector-equal-length.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extract-subvector.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extract-vector-elt-build-vector-combine.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
extractelt-to-trunc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fabs-r600.ll
…
fabs.bf16.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
fabs.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fabs.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fabs.ll
…
fadd64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fadd-fma-fmul-combine.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fadd.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fadd.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fast-ra-kills-vcc.mir
…
fast-regalloc-bundles.mir
…
fast-unaligned-load-store.global.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
fast-unaligned-load-store.private.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
fastregalloc-illegal-subreg-physreg.mir
…
fastregalloc-self-loop-heuristic.mir
…
fastregalloc-sgpr-only.mir
…
fcanonicalize-elimination.bf16.ll
[AMDGPU] Mark amdgcn_tanh as canonicalized (#150059)
2025-07-22 20:03:39 -04:00
fcanonicalize-elimination.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fcanonicalize.f16.ll
[AMDGPU][True16][GlobalISel] Fix v2*16 build_vector patterns (#151496)
2025-08-04 13:06:06 +02:00
fcanonicalize.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fceil64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fceil.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fcmp64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fcmp.ll
…
fconst64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fcopysign.bf16.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
fcopysign.f16.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
fcopysign.f32.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
fcopysign.f32.r600.ll
…
fcopysign.f64.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
fcopysign.gfx11plus.ll
[AMDGPU][True16][CodeGen] Fixed two lit tests (#157684)
2025-09-09 11:13:23 -04:00
fdiv32-to-rcp-folding.ll
…
fdiv_flags.f32.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
fdiv-nofpexcept.ll
…
fdiv.bf16.ll
[AMDGPU] Add support for safe bfloat16 fdiv on targets with bf16 trans instructions (#154373)
2025-08-19 16:03:45 -04:00
fdiv.f16.ll
[AMDGPU] Remove UnsafeFPMath uses (#151079)
2025-07-31 17:36:57 +08:00
fdiv.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fdiv.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
fdot2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fence-barrier.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fence-lds-read2-write2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
ffloor.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ffloor.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
finalize-isel-kill-scc-vcc.mir
[AMDGPU] Fix undefined scc register in successor block of SI_KILL terminators (#134718)
2025-04-30 09:02:45 -05:00
finalizebundle.mir
[CodeGen] Fix handling dead redefs in finalizeBundle (#157427)
2025-09-10 12:48:12 +01:00
fix-crash-valu-hazard.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-frame-ptr-reg-copy-livein.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fix-frame-reg-in-custom-csr-spills.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fix-sgpr-copies-f16-fake16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-f16-gfx12-fake16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-f16-gfx12-true16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-f16-true16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-f16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-nondeterminism.ll
DAG: Use phi to create vregs instead of the constant input (#129464)
2025-03-04 14:44:54 +07:00
fix-sgpr-copies-phi-block-end-iterator-debugloc.ll
[AMDGPU] Select (xor i1 (divergent trunc:i32 x), -1) -> cmp_neq x, 1 (#133698)
2025-04-11 13:03:01 +02:00
fix-sgpr-copies-phi-regression-issue130646-issue130119.ll
Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#135243)
2025-04-10 22:18:21 +02:00
fix-sgpr-copies-phi-regression-issue130646.mir
Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#135243)
2025-04-10 22:18:21 +02:00
fix-sgpr-copies-vgpr16-to-spgr32.ll
[AMDGPU][True16][CodeGen] readfirstlane for vgpr16 copy to sgpr32 (#118037)
2025-05-05 15:17:34 -04:00
fix-sgpr-copies-wwm.ll
[AMDGPU] Fix SIFixSGPRCopies handling of STRICT_WWM and friends (#142122)
2025-05-30 16:32:56 +01:00
fix-sgpr-copies-wwm.mir
[AMDGPU] Fix SIFixSGPRCopies handling of STRICT_WWM and friends (#142122)
2025-05-30 16:32:56 +01:00
fix-sgpr-copies.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-vgpr-copies.mir
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)
2025-01-21 15:27:46 +05:30
fix-wwm-vgpr-copy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
flat_atomics_i32_system.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
flat_atomics_i64_noprivate.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
flat_atomics_i64_system_noprivate.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
flat_atomics_i64_system.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
flat_atomics_i64.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
flat_atomics.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
flat-address-space.ll
[AMDGPU][True16][CodeGen] reopen "FLAT_load using D16 pseudo instruction" (#127673)
2025-02-18 18:16:23 -05:00
flat-atomic-fadd.f32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
flat-atomic-fadd.f64.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
flat-atomicrmw-fadd.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
flat-atomicrmw-fmax.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
flat-atomicrmw-fmin.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
flat-atomicrmw-fsub.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
flat-error-unsupported-gpu-hsa.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
flat-for-global-subtarget-feature.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
flat-load-clustering.mir
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
flat-load-saddr-to-vaddr.ll
[AMDGPU] gfx1250 SADDR tests update. NFC (#155307)
2025-08-25 15:07:15 -07:00
flat-offset-bug.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
flat-saddr-atomics.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
flat-saddr-load.ll
[AMDGPU] Disable SGPR read hazard mitigation for gfx1250 (#150344)
2025-07-24 00:05:58 -07:00
flat-saddr-store.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
flat-scratch-fold-fi-gfx1250.mir
[AMDGPU] Prevent folding of FI with scale_offset on gfx1250 (#149894)
2025-07-21 15:05:43 -07:00
flat-scratch-fold-fi.mir
…
flat-scratch-i8-i16.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
flat-scratch-init.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
flat-scratch-reg.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
flat-scratch-svs.ll
[AMDGPU] Select scale_offset for scratch instructions on gfx1250 (#150111)
2025-07-22 15:24:55 -07:00
flat-scratch.ll
Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)
2025-09-23 17:36:02 +01:00
floor.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
fma-combine.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fma.f16.gfx11plus.ll
[AMDGPU][True16][CodeGen] insert proper register for 16bit data type in vop3p insts (#153143)
2025-08-14 12:02:15 -04:00
fma.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fma.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fma.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmac.sdwa.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmad-formation-fmul-distribute-denormal-mode.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
fmad.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
fmax3-maximumnum.ll
[AMDGPU][True16][Codegen] remove packed build_vector pattern from true16 (#148715)
2025-07-18 12:55:11 -04:00
fmax3.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmax3.ll
[AMDGPU] Support V_PK_MIN3/MAX3_NUM_F16 on gfx1250 (#150326)
2025-07-23 15:15:19 -07:00
fmax_legacy.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmax_legacy.f64.ll
…
fmax_legacy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmax.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
fmaximum3.ll
Add FABS to canCreateUndefOrPoison (#149440)
2025-07-18 14:17:15 +08:00
fmaximum3.v2f16.ll
AMDGPU: Support V_PK_MAXIMUM3_F16 and V_PK_MINIMUM3_F16 on gfx1250 (#150307)
2025-07-23 13:45:01 -07:00
fmaximum.ll
[AMDGPU][True16][GlobalISel] Fix v2*16 build_vector patterns (#151496)
2025-08-04 13:06:06 +02:00
fmaxnum.f64.ll
…
fmaxnum.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
fmaxnum.r600.ll
…
fmed3-cast-combine.ll
…
fmed3.bf16.ll
[AMDGPU][True16][Codegen] remove packed build_vector pattern from true16 (#148715)
2025-07-18 12:55:11 -04:00
fmed3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmin3-minimumnum.ll
[AMDGPU][True16][Codegen] remove packed build_vector pattern from true16 (#148715)
2025-07-18 12:55:11 -04:00
fmin3.ll
[AMDGPU] Support V_PK_MIN3/MAX3_NUM_F16 on gfx1250 (#150326)
2025-07-23 15:15:19 -07:00
fmin_fmax_legacy.amdgcn.ll
…
fmin_legacy.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmin_legacy.f64.ll
…
fmin_legacy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmin.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
fminimum3.ll
Add FABS to canCreateUndefOrPoison (#149440)
2025-07-18 14:17:15 +08:00
fminimum3.v2f16.ll
AMDGPU: Support V_PK_MAXIMUM3_F16 and V_PK_MINIMUM3_F16 on gfx1250 (#150307)
2025-07-23 13:45:01 -07:00
fminimum.ll
[AMDGPU][True16][GlobalISel] Fix v2*16 build_vector patterns (#151496)
2025-08-04 13:06:06 +02:00
fminnum.f64.ll
AMDGPU: Replace ptr addrspace(3) undef in tests with poison (#131049)
2025-03-13 13:28:55 +07:00
fminnum.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
fminnum.r600.ll
…
fmul64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmul-2-combine-multi-use.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmul-to-ldexp.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
fmul.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmul.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
fmuladd.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmuladd.f32.ll
[AMDGPU] fmuladd.f32.ll - clean up prefixes and regenerate checks (#151832)
2025-08-03 09:13:34 +01:00
fmuladd.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fmuladd.v2f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fncall-implicitdef.ll
[LiveVariables] Mark use without implicit if defined at instr (#119446)
2025-08-18 08:34:59 -04:00
fnearbyint.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fneg-combines-gfx1200.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fneg-combines.f16.ll
[SelectionDAG] Remove UnsafeFPMath check in visitFADDForFMACombine (#127770)
2025-06-25 12:31:23 +08:00
fneg-combines.legal.f16.ll
…
fneg-combines.ll
[AMDGPU] fneg-combines.ll - regenerate test checks
2025-07-10 10:23:09 +01:00
fneg-combines.new.ll
[SelectionDAG] Remove UnsafeFPMath check in visitFADDForFMACombine (#127770)
2025-06-25 12:31:23 +08:00
fneg-combines.si.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fneg-fabs-divergence-driven-isel.ll
[InstrEmitter] Use AddOperand in EmitCopyToRegClassNode. (#146637)
2025-07-02 09:44:54 -07:00
fneg-fabs-r600.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
fneg-fabs.bf16.ll
[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)
2025-07-09 16:17:14 -04:00
fneg-fabs.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fneg-fabs.f64.ll
…
fneg-fabs.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
fneg-fold-legalize-dag-increase-insts.ll
AMDGPU: Replace undef with poison in tests using insertvalue (#130895)
2025-03-12 16:11:11 +07:00
fneg-modifier-casting.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
fneg.bf16.ll
[AMDGPU] Make <2 x bfloat> fneg legal (#142870)
2025-06-04 22:09:25 -07:00
fneg.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fneg.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fneg.ll
DAG: Check libcall function is supported before emission (#144314)
2025-06-27 18:09:04 +09:00
fold_acc_copy_into_valu.mir
…
fold-agpr-phis.mir
AMDGPU: Try to perform copy to agpr from reg_sequence at the copy (#129463)
2025-03-04 14:41:56 +07:00
fold-cndmask-wave32.mir
…
fold-cndmask.mir
…
fold-commute-sgpr.mir
[AMDGPU] Check legality of both operands before swap (#148843)
2025-07-15 15:55:26 -04:00
fold-fabs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fold-fi-mubuf.mir
…
fold-fi-operand-shrink.mir
…
fold-fmaak-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fold-fmul-to-neg-abs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fold-freeze-fmul-to-fma.ll
[DAGCombiner] Allow freeze to sink through fmul by adding it to AllowMultipleMaybePoisonOperands (#142250)
2025-06-08 19:38:57 +08:00
fold-gep-offset.ll
[AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns (#143881)
2025-09-18 15:01:07 +02:00
fold-imm-copy-agpr.mir
AMDGPU: Fold 64-bit immediate into copy to AV class (#155615)
2025-09-03 09:29:59 +09:00
fold-imm-copy.mir
AMDGPU: Fold 64-bit immediate into copy to AV class (#155615)
2025-09-03 09:29:59 +09:00
fold-imm-f16-f32.mir
AMDGPU: Replace more undef test pointer uses with poison (#131102)
2025-03-14 09:53:45 +07:00
fold-immediate-operand-shrink-with-carry.mir
…
fold-immediate-operand-shrink.mir
…
fold-immediate-output-mods.mir
[CodeGen][NewPM] Port PeepholeOptimizer to NPM (#116326)
2024-11-18 11:02:01 +05:30
fold-implicit-operand.mir
…
fold-int-pow2-with-fmul-or-fdiv.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
fold-literal-multiple-gfx10.mir
AMDGPU: Correct legal literal operand logic for multiple uses (#127594)
2025-02-18 19:58:42 +07:00
fold-multiple-commute.mir
…
fold-multiple.mir
…
fold-omod-crash.mir
…
fold-operands-frame-index.gfx10.mir
…
fold-operands-frame-index.mir
[AMDGPU] Do not fold an immediate into instructions with frame indexes (#151263)
2025-08-06 11:47:37 -07:00
fold-operands-order.mir
…
fold-operands-remove-m0-redef.mir
…
fold-operands-s-add-copy-to-vgpr.mir
AMDGPU: Make frame index folding logic consistent with eliminateFrameIndex (#129633)
2025-03-05 10:09:30 +07:00
fold-operands-scalar-fmac.mir
AMDGPU: Fix overly conservative immediate operand check (#127563)
2025-02-27 08:42:09 +07:00
fold-over-exec.mir
…
fold-readlane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
fold-reload-into-exec.mir
…
fold-reload-into-m0.mir
…
fold-restore-undef-use.mir
[CodeGen][NPM] Port VirtRegRewriter to NPM (#130564)
2025-04-30 14:10:46 +05:30
fold-sgpr-copy.mir
AMDGPU: Relax legal register operand constraint (#157989)
2025-09-12 08:57:47 +09:00
fold-sgpr-multi-imm.mir
[AMDGPU] Do not fold an immediate into instructions with frame indexes (#151263)
2025-08-06 11:47:37 -07:00
fold-short-64-bit-literals.mir
AMDGPU: Add baseline tests for #139317 (#140607)
2025-05-29 19:41:57 +02:00
fold-vgpr-copy.mir
AMDGPU: Correct legal literal operand logic for multiple uses (#127594)
2025-02-18 19:58:42 +07:00
fold-vgpr-phyreg.mir
…
fold-zero-high-bits-clear-kill-flags.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
fold-zero-high-bits-skips-non-reg.mir
AMDGPU: Try constant fold after folding immediate (#141862)
2025-06-10 11:44:44 +09:00
folding-of-i32-as-i64.mir
…
force-alwaysinline-lds-global-address-codegen.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
force-alwaysinline-lds-global-address.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
force-wait-after-always-gds.mir
[AMDGPU] Insert before and after instructions that always use GDS (#131338)
2025-03-21 09:33:04 +00:00
fp16_to_fp32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp16_to_fp64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp32_to_fp16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp64-atomics-gfx90a.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
fp64-min-max-buffer-atomics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp64-min-max-buffer-ptr-atomics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp_to_sint.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp_to_sint.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp_to_uint.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp_to_uint.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp_trunc_store_fp32_to_bf16.ll
…
fp_trunc_store_fp64_to_bf16.ll
[CodeGen] Simplify expandRoundInexactToOdd (#134988)
2025-04-10 09:45:38 +01:00
fp-atomic-to-s_denormmode.mir
AMDGPU: Replace more undef test pointer uses with poison (#131102)
2025-03-14 09:53:45 +07:00
fp-atomics-gfx942.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
fp-atomics-gfx950.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
fp-atomics-gfx1200.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
fp-classify.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp-min-max-buffer-atomics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp-min-max-buffer-ptr-atomics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp-min-max-image-atomics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp-min-max-num-flat-atomics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fp-min-max-num-global-atomics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fpenv.ll
…
fpext-free.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fpext.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fpext.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fpow.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
fptoi.i128.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
fptosi.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fptoui.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fptrunc.f16.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
fptrunc.ll
[AMDGPU] Remove UnsafeFPMath uses (#151079)
2025-07-31 17:36:57 +08:00
fptrunc.v2f16.no.fast.math.ll
AMDGPU: Custom lower fptrunc vectors for f32 -> f16 (#141883)
2025-06-06 15:15:24 -07:00
fract-match.ll
Add FABS to canCreateUndefOrPoison (#149440)
2025-07-18 14:17:15 +08:00
fract.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fract.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
frame-index-elimination-tied-operand.mir
…
frame-index-elimination.ll
[AMDGPU] Do not fold an immediate into instructions with frame indexes (#151263)
2025-08-06 11:47:37 -07:00
frame-index.mir
AMDGPU: Handle s_add_u32 in eliminateFrameIndex (#129628)
2025-03-05 08:09:46 +07:00
frame-lowering-entry-all-sgpr-used.mir
…
frame-lowering-fp-adjusted.mir
…
frame-setup-without-sgpr-to-vgpr-spills.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
freeze-binary.ll
[AMDGPU] Implement IR expansion for frem instruction (#130988)
2025-09-03 16:27:15 +02:00
freeze.ll
[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDValue with just the frozen node (#150017)
2025-08-05 09:24:09 +01:00
frem.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
frexp-constant-fold.ll
AMDGPU: Directly check if shrink-instructions run is post-RA (#142009)
2025-05-30 15:52:18 +02:00
fshl.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fshr.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
fsqrt.f32.ll
[AMDGPU] Remove ApproxFuncFPMath uses (#155578)
2025-08-28 11:09:01 +08:00
fsqrt.f64.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
fsqrt.r600.ll
…
fsub64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fsub-as-fneg-src-modifier.ll
…
fsub.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fsub.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ftrunc.f64.ll
Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#135243)
2025-04-10 22:18:21 +02:00
ftrunc.ll
…
function-args-inreg.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
function-args.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
function-call-relocs.ll
…
function-resource-usage.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
function-returns.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
fused-bitlogic.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
gcn-reg-pressure-true16-integer-overflow.mir
[AMDGPU] Fix a potential integer overflow in GCNRegPressure when true16 is enabled (#144968)
2025-06-20 12:29:32 -04:00
gds-allocation.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
gds-atomic.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
gds-unsupported.ll
…
generic-targets-require-v6.ll
…
gep-address-space.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
gep-const-address-space.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
gep-flags-stack-offsets.ll
…
gfx10-twoaddr-fma.mir
…
gfx10-vop-literal.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
gfx10plus-wavefront-sgpr-count.ll
[AMDGPU] Set GRANULATED_WAVEFRONT_SGPR_COUNT of compute_pgm_rsrc1 to 0 for gfx10+ (#154666)
2025-08-27 09:48:42 +08:00
gfx11-twoaddr-fma.mir
[AMDGPU][True16][CodeGen] update more GFX11Plus codegen test with true16 mode (#138600)
2025-05-12 12:19:46 -04:00
gfx11-user-sgpr-init16-bug.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
gfx12_scalar_subword_loads.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
gfx90a-enc.ll
AMDGPU: Fix -amdgpu-mfma-vgpr-form flag on gfx908 (#150599)
2025-07-25 19:49:56 +09:00
gfx902-without-xnack.ll
…
gfx942-hazards.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
gfx1250-scratch-scope-se.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
gfx-call-non-gfx-func.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
gfx-callable-argument-types.ll
AMDGPU: Replace copy-to-mov-imm folding logic with class compat checks (#154501)
2025-08-26 23:41:35 +09:00
gfx-callable-preserved-registers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
gfx-callable-return-types.ll
AMDGPU: Replace copy-to-mov-imm folding logic with class compat checks (#154501)
2025-08-26 23:41:35 +09:00
global_atomic_optimizer_fp_rtn.ll
…
global_atomics_i32_system.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
global_atomics_i64_system.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
global_atomics_i64.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
global_atomics_iterative_scan_fp.ll
…
global_atomics_iterative_scan.ll
…
global_atomics_optimizer_fp_no_rtn.ll
…
global_atomics_scan_fadd.ll
AMDGPU: Fix using underaligned atomicrmw in atomic scan tests
2025-07-07 21:43:48 +09:00
global_atomics_scan_fmax.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global_atomics_scan_fmin.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global_atomics_scan_fsub.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global_atomics.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
global_smrd_cfg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global_smrd.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global-address.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global-alias.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
global-atomic-fadd.f32-no-rtn.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
global-atomic-fadd.f32-rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global-atomic-fadd.f64.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
global-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-atomic-fadd.v2f16-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-atomic-scan.ll
…
global-atomicrmw-fadd-wrong-subtarget.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
global-atomicrmw-fadd.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
global-atomicrmw-fmax.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
global-atomicrmw-fmin.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
global-atomicrmw-fsub.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
global-atomics-fp-wrong-subtarget.ll
…
global-constant.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global-directive.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global-extload-gfx11plus.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
global-extload-i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global-i16-load-store.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
global-load-saddr-to-vaddr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
global-load-xcnt.ll
[AMDGPU] Don't allow wgp mode on gfx1250 (#153680)
2025-08-14 15:16:56 -07:00
global-saddr-atomics-min-max-system.ll
[AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (#135340)
2025-04-22 14:53:55 +02:00
global-saddr-atomics.gfx908.ll
…
global-saddr-atomics.gfx1030.ll
…
global-saddr-atomics.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
global-saddr-load.ll
AMDGPU/GlobalISel: Import D16 load patterns and add combines for them (#153178)
2025-09-11 12:02:50 +02:00
global-saddr-store.ll
[AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (#135340)
2025-04-22 14:53:55 +02:00
global-smrd-unknown.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
global-variable-relocs.ll
…
greedy-alloc-fail-sgpr1024-spill.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
greedy-broken-ssa-verifier-error.mir
…
greedy-global-heuristic.mir
…
greedy-instruction-split-subrange.mir
…
greedy-liverange-priority.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
greedy-remark-crash-unassigned-reg.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
greedy-reverse-local-assignment.ll
AMDGPU: Replace tests using undef in shufflevector with poison (#130899)
2025-03-12 20:45:02 +07:00
group-image-instructions.ll
[AMDGPU] Make max dwords of memory cluster configurable (#119342)
2024-12-18 14:17:27 +08:00
gv-const-addrspace.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
gv-offset-folding.ll
…
gws-hazards.mir
…
half-alloca-promotion.ll
…
half.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
hard-clause-limit-attr.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clause-limit.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clauses-gfx1250.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clauses-img-gfx10.mir
[AMDGPU][NPM] Port SIInsertHardClauses to NPM (#130062)
2025-03-25 15:33:32 +05:30
hard-clauses-img-gfx11.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clauses-img-gfx12.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clauses-load-monitor.mir
[AMDGPU] Update hard-clauses-load-monitor.mir. NFC (#157546)
2025-09-08 16:19:10 -07:00
hard-clauses.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hazard-buffer-store-v-interp.mir
…
hazard-flat-instruction-valu-check.mir
[CodeGen][NPM] Port PostRAHazardRecognizer to NPM (#130066)
2025-04-09 16:36:22 +05:30
hazard-getreg-waitalu.mir
[AMDGPU] Handle S_GETREG_B32 hazard on gfx1250 (#153848)
2025-08-15 11:38:22 -07:00
hazard-hidden-bundle.mir
…
hazard-in-bundle.mir
…
hazard-inlineasm.mir
…
hazard-kill.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
hazard-lds-addtid.mir
…
hazard-pass-ordering.mir
…
hazard-pseudo-machineinstrs.mir
…
hazard-recognizer-meta-insts.mir
…
hazard-recognizer-src-shared-base.ll
…
hazard-shift64.mir
…
hazard.mir
…
hazards-gfx950.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
hazards-gfx1250.mir
[AMDGPU] w/a for s_setreg_b32 gfx1250 hazard with MODE register (#153879)
2025-08-15 16:08:13 -07:00
high-bits-zeroed-16-bit-ops.mir
…
high-RP-reschedule.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
hip.extern.shared.array.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
hoist-cond.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
hsa-default-device.ll
…
hsa-fp-mode.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
hsa-func-align.ll
…
hsa-func.ll
…
hsa-generic-target-features.ll
…
hsa-globals.ll
…
hsa-group-segment.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
hsa-metadata-agpr-register-count.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
hsa-metadata-agpr-small.ll
…
hsa-metadata-deduced-arg-attr.ll
…
hsa-metadata-dynlds-func-hidden-args-v5.ll
…
hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
…
hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
…
hsa-metadata-enqueue-kernel-.ll
…
hsa-metadata-from-llvm-ctor-dtor-list.ll
…
hsa-metadata-from-llvm-ir-full.ll
AMDGPU: Replace some undef uses in test metadata with poison (#131052)
2025-03-13 13:43:48 +07:00
hsa-metadata-heap-v5.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
hsa-metadata-hidden-args-v4.ll
…
hsa-metadata-hidden-args-v5.ll
…
hsa-metadata-hostcall-present-asan.ll
…
hsa-metadata-hostcall-v4.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
hsa-metadata-hostcall-v5.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
hsa-metadata-images.ll
…
hsa-metadata-invalid-ocl-version-1.ll
…
hsa-metadata-invalid-ocl-version-3.ll
…
hsa-metadata-kernel-code-props.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
hsa-metadata-multigrid-sync-arg-v5.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
hsa-metadata-queue-ptr-v4.ll
AMDGPU: Fix attributor not handling all trap intrinsics (#131758)
2025-03-19 10:17:28 +07:00
hsa-metadata-queue-ptr-v5.ll
AMDGPU: Fix attributor not handling all trap intrinsics (#131758)
2025-03-19 10:17:28 +07:00
hsa-metadata-queueptr-v5.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
hsa-metadata-resource-usage-function-ordering.ll
…
hsa-metadata-uniform-workgroup-size-v5.ll
…
hsa-metadata-wavefrontsize.ll
…
hsa-metadata-workgroup-processor-mode-v5.ll
…
hsa-note-no-func.ll
…
hsa.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
huge-number-operand-folds.mir
…
huge-private-buffer.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
i1_copy_phi_with_phi_incoming_value.mir
…
i1-copies-rpo.mir
…
i1-copy-from-loop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
i1-copy-implicit-def.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
i1-copy-phi-uniform-branch.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
i1-copy-phi.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
i1-divergent-phi-fix-sgpr-copies-assert.mir
AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (#128903)
2025-02-27 06:49:47 +07:00
i1-to-bf16.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
i8-to-double-to-float.ll
…
icmp64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
idemponent-atomics.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
identical-subrange-spill-infloop.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
idiv-licm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
idot2.ll
AMDGPU: Use default shouldRewriteCopySrc (#125535)
2025-02-07 12:31:14 +07:00
idot4s.ll
[AMDGPU][True16][CodeGen] sext i16 inreg in true16 mode (#144024)
2025-06-18 11:30:53 -04:00
idot4u.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
idot8s.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
idot8u.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
iglp-no-clobber.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
iglp.opt.reentry.ll
[AMDGPU] Teach iterative schedulers about IGLP (#134953)
2025-04-11 15:34:49 -07:00
illegal-eviction-assert.mir
RegAlloc: Use new approach to handling failed allocations (#128469)
2025-02-26 15:34:47 +07:00
illegal-sgpr-to-vgpr-copy.ll
[NFC][FIX] Add -verify-machineinstrs=0 explicitly to some test files
2025-07-23 19:12:46 -04:00
image-attributes.ll
…
image-load-d16-tfe.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
image-resource-id.ll
…
image-sample-waterfall.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
image-schedule.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
img-nouse-adjust.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
imm16.ll
AMDGPU: Replace copy-to-mov-imm folding logic with class compat checks (#154501)
2025-08-26 23:41:35 +09:00
imm.ll
Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)
2025-09-23 17:36:02 +01:00
immv216.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
implicit-arg-v5-opt.ll
[InstCombine] Infer nusw + nneg -> nuw for getelementptr (#111144)
2024-12-05 14:36:40 +01:00
implicit-def-muse.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
implicit-kernarg-backend-usage.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
implicit-kernel-argument-alignment.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
implicitarg-attributes.ll
…
implicitarg-offset-attributes.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
indirect-addressing-si-gfx9.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
indirect-addressing-si.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
indirect-addressing-term.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
indirect-call-known-callees.ll
AMDGPU: Replace some test i32 undef uses with poison (#131092)
2025-03-13 20:10:17 +07:00
indirect-call-set-from-other-function.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
indirect-call.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
indirect-private-64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
infer-addrpace-pipeline.ll
…
infer-addrspace-flat-atomic.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
infer-uniform-load-shader.ll
…
infinite-loop-evergreen.ll
AMDGPU: Remove a FileCheck from an XFAILed test
2025-03-12 12:18:57 +07:00
infinite-loop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
inflate-av-remat-imm.mir
AMDGPU: Add pseudoinstruction for 64-bit agpr or vgpr constants (#154499)
2025-08-20 22:54:37 +09:00
inflate-reg-class-vgpr-mfma-to-agpr-negative-tests.mir
AMDGPU: Handle rewriting VGPR MFMA to AGPR with subregister copies (#153019)
2025-08-21 01:17:03 +00:00
inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
[AMDGPU] Add aperture classes to VS_64 (#158823)
2025-09-16 11:15:50 -07:00
inflate-reg-class-vgpr-mfma-to-av.mir
AMDGPU: Add more baseline tests for VGPR MFMA rewrite pass (#148173)
2025-07-14 19:10:49 +09:00
inflated-reg-class-snippet-copy-use-after-free.mir
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
infloop-subrange-spill-inspect-subrange.mir
…
infloop-subrange-spill.mir
…
init-whole-wave-vgpr-count-large.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
init-whole-wave-vgpr-count-leaf.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
init-whole-wave-vgpr-count-use-inactive.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
init-whole-wave-vgpr-count.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
inline-asm-av-constraint-err.ll
AMDGPU: Add new VA inline asm constraint for AV registers (#152665)
2025-08-12 10:17:28 +09:00
inline-asm-av-constraint.ll
AMDGPU: Add new VA inline asm constraint for AV registers (#152665)
2025-08-12 10:17:28 +09:00
inline-asm-out-of-bounds-register.ll
[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)
2025-09-03 16:25:18 -07:00
inline-asm-reserved-regs.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inline-asm.i128.ll
[AMDGPU] Add aperture classes to VS_64 (#158823)
2025-09-16 11:15:50 -07:00
inline-asm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
inline-attr.ll
[AMDGPU][Attributor] Remove final update of waves-per-eu after the attributor run (#155246)
2025-08-27 14:11:03 -04:00
inline-calls.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
inline-constraints.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
inline-maxbb.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
inlineasm-16-fake16.ll
[AMDGPU][True16][CodeGen] select vgpr16 for asm inline 16bit vreg (#140946)
2025-05-21 17:47:28 -04:00
inlineasm-16-true16.ll
[AMDGPU][True16][CodeGen] select vgpr16 for asm inline 16bit vreg (#140946)
2025-05-21 17:47:28 -04:00
inlineasm-16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
inlineasm-illegal-type.ll
[AMDGPU] Fix crash for inline-asm inputs of type MVT::Other (#153425)
2025-08-13 17:27:31 +02:00
inlineasm-mismatched-size-error.ll
[AMDGPU] Reject misaligned SGPR constraints for inline asm (#123590)
2025-01-20 15:47:11 +01:00
inlineasm-mismatched-size.ll
…
inlineasm-packed.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
inlineasm-v16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
InlineAsmCrash.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
input-mods.r600.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
insert_subreg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
insert_vector_dynelt.ll
Reland "[SelectionDAG] Make (a & x) | (~a & y) -> (a & (x ^ y)) ^ y available for all targets" (#143651)
2025-06-11 15:56:37 +08:00
insert_vector_elt.ll
Reland "[SelectionDAG] Make (a & x) | (~a & y) -> (a & (x ^ y)) ^ y available for all targets" (#143651)
2025-06-11 15:56:37 +08:00
insert_vector_elt.v2bf16.ll
[AMDGPU] Add few missing gfx1250 codegen tests. NFC (#155314)
2025-08-25 15:22:33 -07:00
insert_vector_elt.v2i16.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
insert_vector_elt.v2i16.subtest-saddr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
insert_waitcnt_for_precise_memory.ll
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
2025-09-03 20:04:01 +01:00
insert-branch-w32.mir
…
insert-delay-alu-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
insert-delay-alu-literal.mir
[AMDGPU][NewPM] Port AMDGPUInsertDelayAlu to NPM (#128003)
2025-02-26 09:50:09 +05:30
insert-delay-alu-parse.mir
…
insert-delay-alu-wmma-xdl.mir
AMDGPU: Remove the dot4 test in insert-delay-alu-wmma-xdl.mir, NFC (#149375)
2025-07-17 14:26:09 -07:00
insert-delay-alu.mir
Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)
2025-03-13 10:26:20 +01:00
insert-handle-flat-vmem-ds.mir
[AMDGPU][NPM] Port SIPreEmitPeephole to NPM (#130065)
2025-04-08 17:58:48 +05:30
insert-skip-from-vcc.mir
…
insert-skips-gfx10.mir
…
insert-skips-gfx12.mir
[AMDGPU] Add s_barrier_init|join|leave instructions (#153296)
2025-08-12 15:07:07 -07:00
insert-skips-gws.mir
…
insert-skips-ignored-insts.mir
…
insert-subvector-unused-scratch.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
insert-waitcnts-callee.mir
…
insert-waitcnts-crash.ll
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
insert-waitcnts-exp.mir
AMDGPU: Replace more undef test pointer uses with poison (#131102)
2025-03-14 09:53:45 +07:00
insert-waitcnts-fence-soft.mir
[AMDGPU] introduce S_WAITCNT_LDS_DIRECT in the memory legalizer (#150887)
2025-07-30 11:23:28 +05:30
insert-waitcnts-gfx12-wbinv.mir
[AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (#135340)
2025-04-22 14:53:55 +02:00
insert-waitcnts-hang.mir
[AMDGPU][NPM] Port SIInsertWaitcnts to NPM (#130061)
2025-03-24 21:36:45 +05:30
inserted-wait-states.mir
…
inst-prefetch-hint.ll
[AMDGPU] Set inst_pref_size to maximum (#126981)
2025-03-03 10:40:31 -08:00
integer-canonicalizing-src-modifiers.ll
[AMDGPU] Add additional test cases to integer src mod test (#152692)
2025-08-08 23:14:36 +01:00
integer-mad-patterns.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
integer-select-src-modifiers.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
internalize.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
invalid-addrspacecast.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
invalid-cast-load-i1.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
invalid-hidden-kernarg-in-kernel-signature.ll
AMDGPU: Replace amdgpu-no-agpr with amdgpu-agpr-alloc (#129893)
2025-03-06 09:17:51 +07:00
invalid-inline-asm-constraint-crash.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
invariant-image-load.ll
…
invariant-load-no-alias-store.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
invert-br-undef-vcc.mir
AMDGPU: Replace undef references with poison in some MIR tests (#131254)
2025-03-14 14:45:49 +07:00
ipra-regmask.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
ipra-return-address-save-restore.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ipra.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
irtranslator-whole-wave-functions.ll
Reapply "[AMDGPU] Intrinsic for launching whole wave functions" (#153584)
2025-08-15 10:12:47 +02:00
isel-amdgcn-cs-chain-intrinsic-w32.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
isel-amdgcn-cs-chain-intrinsic-w64.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
isel-amdgpu-cs-chain-cc.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
isel-amdgpu-cs-chain-preserve-cc.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
isel-whole-wave-functions.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
issue48473.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
issue92561-restore-undef-scc-verifier-error.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
issue98474-assigned-physreg-interference.mir
…
issue98474-need-live-out-undef-subregister-def.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
issue98474-virtregrewriter-live-out-undef-subregisters.mir
…
issue120256-annotate-constexpr-addrspacecast.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
issue121601-combine-concat-vectors-assumes-f16.ll
DAG: Fix assuming f16 is the only 16-bit fp type in concat vector combine (#121637)
2025-01-06 10:38:54 +07:00
issue130120-eliminate-frame-index.ll
[AMDGPU] Do not fold an immediate into instructions with frame indexes (#151263)
2025-08-06 11:47:37 -07:00
issue139317-bad-opsel-reg-sequence-fold.ll
AMDGPU: Fix tracking subreg defs when folding through reg_sequence (#140608)
2025-06-26 07:42:55 +09:00
issue153808-extract-subvector-legalize.ll
DAG: Handle half spanning extract_subvector in type legalization (#154101)
2025-08-21 00:05:12 +00:00
itofp.i128.bf.ll
Rename ExpandLargeFpConvertPass to ExpandFpPass (#131128)
2025-03-14 13:11:45 +01:00
itofp.i128.ll
[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)
2025-08-20 17:32:29 +02:00
jump-address.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
kcache-fold.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
kernarg-size.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
kernarg-stack-alignment.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
kernel_code_t_recurse.ll
…
kernel-args.ll
[DAG] Always use stack to promote bitcast when the source is vector (#151065)
2025-08-02 15:32:10 -07:00
kernel-argument-dag-lowering.ll
[AMDGPU] kernel-argument-dag-lowering.ll - regenerate test coverage (#159526)
2025-09-18 09:34:38 +00:00
kernel-mubuf-with-voffset.mir
…
kernel-vgpr-spill-mubuf-with-voffset.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
kill-infinite-loop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
kill-true-in-return-block.ll
[AMDGPU] Select (xor i1 (divergent trunc:i32 x), -1) -> cmp_neq x, 1 (#133698)
2025-04-11 13:03:01 +02:00
known-never-nan.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
known-never-snan.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
knownbits-recursion.ll
…
large-alloca-compute.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
large-alloca-graphics.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
large-avgpr-assign-last.mir
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
large-constant-initializer.ll
…
large-work-group-promote-alloca.ll
…
lcssa-optnone.ll
…
lds-alignment.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
lds-bounds.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lds-branch-vmem-hazard.mir
…
lds-direct-hazards-gfx11.mir
…
lds-direct-hazards-gfx12.mir
…
lds-dma-hazards.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
lds-dma-waitcnt.mir
AMDGPU: Replace undef references with poison in some MIR tests (#131254)
2025-03-14 14:45:49 +07:00
lds-dma-waits.ll
[AMDGPU] Relax lds dma waitcnt with no aliasing pair (#131842)
2025-03-24 10:38:47 -07:00
lds-dma-workgroup-release.ll
[AMDGPU] Reenable BackOffBarrier on GFX11/12 (#155370)
2025-09-02 09:37:43 +02:00
lds-frame-extern.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lds-global-non-entry-func.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lds-initializer.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
lds-limit-diagnostics-gfx1250.ll
[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)
2025-08-14 12:52:00 -07:00
lds-limit-diagnostics.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
lds-m0-init-in-loop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lds-misaligned-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lds-mixed-absolute-addresses-unused.ll
…
lds-mixed-absolute-dynlds.ll
…
lds-no-realign-allocated-variables.ll
…
lds-oqap-crash.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lds-output-queue.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lds-reject-anonymous-kernels.ll
AMDGPU: Use reportFatalUsageError in AMDGPULowerModuleLDS (#145130)
2025-06-21 12:18:25 +09:00
lds-reject-mixed-absolute-addresses.ll
AMDGPU: Use reportFatalUsageError for LDS mixed absolute addresses (#145135)
2025-06-21 23:54:27 +09:00
lds-relocs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lds-run-twice-absolute-md.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
lds-run-twice.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
lds-size-hsa-gfx950.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lds-size-hsa-gfx1250.ll
[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)
2025-08-14 12:52:00 -07:00
lds-size-pal-gfx950.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lds-size-pal-gfx1250.ll
[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)
2025-08-14 12:52:00 -07:00
lds-size-pal-metadata.ll
[AMDGPU] Fix hw stage metadata setting for unsigned values (#154502)
2025-09-02 10:42:11 +02:00
lds-size.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
lds-zero-initializer.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
legalize-amdgcn.dead.mir
[AMDGPU] Support arbitrary types in amdgcn.dead (#134841)
2025-05-05 14:08:00 +02:00
legalize-amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.load.format.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.load.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.store.format.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.store.format.f32.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.store.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.ptr.buffer.load.format.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.ptr.buffer.load.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.ptr.buffer.store.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.ptr.tbuffer.load.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.ptr.tbuffer.store.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.tbuffer.load.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.tbuffer.store.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.tbuffer.store.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-fp-load-invariant.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
legalize-soffset-mbuf.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalizedag-bug-expand-setcc.ll
…
licm-regpressure.mir
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
licm-valu.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
licm-wwm.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
limit-coalesce.mir
…
limit-soft-clause-reg-pressure.mir
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
lit.local.cfg
…
literal64.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
literal-constant-like-operand-instruction-size.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
literals.ll
…
live-interval-bug-in-rename-independent-subregs.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
liveness.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
liveout-implicit-def-subreg-redef-blender-verifier-error.mir
…
livevars-implicitdef.mir
[LiveVariables] Mark use without implicit if defined at instr (#119446)
2025-08-18 08:34:59 -04:00
llc-pipeline-npm.ll
[AMDGPU] Change expand-fp opt level argument syntax (#157408)
2025-09-10 10:44:28 +02:00
llc-pipeline.ll
[AMDGPU] High VGPR lowering on gfx1250 (#156965)
2025-09-04 16:20:47 -07:00
llvm.amdgcn.addrspacecast.nonnull.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
llvm.amdgcn.alignbyte.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.atomic.cond.sub.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.atomic.dec.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.atomic.inc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ballot.i32.ll
DAG: Use phi to create vregs instead of the constant input (#129464)
2025-03-04 14:44:54 +07:00
llvm.amdgcn.ballot.i64.ll
DAG: Use phi to create vregs instead of the constant input (#129464)
2025-03-04 14:44:54 +07:00
llvm.amdgcn.ballot.i64.wave32.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
llvm.amdgcn.bitop3.ll
[AMDGPU] Bitop3 opcodes for gfx1250 (#151235)
2025-07-29 15:36:56 -07:00
llvm.amdgcn.bitreplicate.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.buffer.load-last-use.ll
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
2025-07-23 16:47:00 +02:00
llvm.amdgcn.buffer.load.dwordx3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.buffer.load.lds.err.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.buffer.store.dwordx3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.bvh8_intersect_ray.ll
[AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (#130041)
2025-03-19 16:08:08 +01:00
llvm.amdgcn.class.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.class.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cluster.id.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
llvm.amdgcn.cluster.load.async.to.lds.ll
[AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns (#143881)
2025-09-18 15:01:07 +02:00
llvm.amdgcn.cluster.load.ll
[AMDGPU] Support cluster load instructions for gfx1250 (#156548)
2025-09-02 16:34:20 -07:00
llvm.amdgcn.cluster.workgroup.id.ll
[AMDGPU] Support lowering of cluster related instrinsics (#157978)
2025-09-12 21:11:17 -04:00
llvm.amdgcn.cluster.workgroup.max.flat.id.ll
[AMDGPU] Support lowering of cluster related instrinsics (#157978)
2025-09-12 21:11:17 -04:00
llvm.amdgcn.cluster.workgroup.max.id.ll
[AMDGPU] Support lowering of cluster related instrinsics (#157978)
2025-09-12 21:11:17 -04:00
llvm.amdgcn.cooperative.atomic-agent.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
llvm.amdgcn.cooperative.atomic-basic.ll
[AMDGPU] Add gfx1251 runlines to cooperative atomcis tests. NFC (#159437)
2025-09-17 14:08:05 -07:00
llvm.amdgcn.cooperative.atomic-singlethread.ll
[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)
2025-09-04 09:19:25 +00:00
llvm.amdgcn.cooperative.atomic-system.ll
[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)
2025-09-04 09:19:25 +00:00
llvm.amdgcn.cooperative.atomic-wavefront.ll
[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)
2025-09-04 09:19:25 +00:00
llvm.amdgcn.cooperative.atomic-workgroup.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
llvm.amdgcn.cos.bf16.ll
[AMDGPU] Add support for v_cos_bf16 on gfx1250 (#149355)
2025-07-17 14:43:34 -04:00
llvm.amdgcn.cos.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cos.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cubeid.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cubema.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cubesc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cubetc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cvt.f16.fp8.ll
[NFC][AMDGPU] Add an IR test for v_cvt_f16_bf8 (#149627)
2025-07-21 10:54:55 -04:00
llvm.amdgcn.cvt.f32.fp8.err.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.cvt.fp8.dpp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cvt.fp8.dpp.mir
…
llvm.amdgcn.cvt.fp8.e5m3.ll
[AMDGPU] Add gfx1250 cvt_pk|sr_fp8|bf8_f32 instructions (#151595)
2025-07-31 16:04:46 -07:00
llvm.amdgcn.cvt.fp8.f16.ll
[AMDGPU] Add v_cvt_sr|pk_bf8|fp8_f16 gfx1250 instructions (#151415)
2025-07-30 17:24:45 -07:00
llvm.amdgcn.cvt.fp8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cvt.off.f32.i4.ll
[Clang][AMDGPU] Add __builtin_amdgcn_cvt_off_f32_i4 (#133741)
2025-04-02 19:51:40 +02:00
llvm.amdgcn.cvt.pk.f16.ll
[AMDGPU] v_cvt_sr_pk_f16_f32 gfx1250 instruction (#151482)
2025-07-31 12:25:55 -07:00
llvm.amdgcn.cvt.pk.i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cvt.pk.u16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cvt.pknorm.i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cvt.pknorm.u16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cvt.pkrtz.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cvt.sat.pk.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
llvm.amdgcn.cvt.scale.pk.ll
[AMDGPU] Change scale_sel to be 4 bits (#157900)
2025-09-16 15:36:45 -04:00
llvm.amdgcn.cvt.scalef32.pk8.ll
[AMDGPU] gfx1250 v_cvt_scalef32_pk8_* instructions (#151758)
2025-08-01 18:29:45 -07:00
llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
[AMDGPU] v_cvt_scalef32_pk16_* gfx1250 instructions (#151807)
2025-08-02 12:42:12 -07:00
llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
[AMDGPU] Fix destination op_sel for v_cvt_scale32_* and v_cvt_sr_* (#151411)
2025-07-30 16:15:50 -07:00
llvm.amdgcn.cvt.scalef32.pk.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cvt.scalef32.sr.ll
[AMDGPU] Fix destination op_sel for v_cvt_scale32_* and v_cvt_sr_* (#151411)
2025-07-30 16:15:50 -07:00
llvm.amdgcn.cvt.scalef32.sr.pk16.ll
[AMDGPU] v_cvt_scalef32_sr_pk16_* gfx1250 instructions (#151810)
2025-08-02 15:21:59 -07:00
llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
[AMDGPU] Fix destination op_sel for v_cvt_scale32_* and v_cvt_sr_* (#151411)
2025-07-30 16:15:50 -07:00
llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
[AMDGPU] gfx1250 v_cvt_scalef32_sr_pk8_* instructions (#151765)
2025-08-01 19:25:57 -07:00
llvm.amdgcn.cvt.scalef32.sr.pk.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.cvt.sr.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.cvt.sr.pk.bf16.ll
[AMDGPU] Add gfx1250 v_cvt_sr_pk_bf16_f32 instruction (#151385)
2025-07-30 14:02:03 -07:00
llvm.amdgcn.dead.ll
[AMDGPU] Support arbitrary types in amdgcn.dead (#134841)
2025-05-05 14:08:00 +02:00
llvm.amdgcn.dispatch.id.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
llvm.amdgcn.dispatch.ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.div.fixup.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.div.fixup.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.div.fmas.ll
[AMDGPU] Update codegen tests for PR #154069 (#154862)
2025-08-22 07:58:21 -06:00
llvm.amdgcn.div.scale.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.dot4.f32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.add.gs.reg.rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.append.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
llvm.amdgcn.ds.bpermute.fi.b32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.bpermute.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
[AMDGPU] Add intrinsics and MIs for ds_bvh_stack_* (#130007)
2025-03-17 09:13:20 +01:00
llvm.amdgcn.ds.bvh.stack.rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.consume.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.gws.barrier.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.gws.init.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.gws.sema.br.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.gws.sema.p.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.gws.sema.release.all.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.gws.sema.v.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.ordered.add-errors.ll
AMDGPU: Avoid report_fatal_error on ds ordered intrinsics (#145202)
2025-06-23 13:09:09 +09:00
llvm.amdgcn.ds.ordered.add-unsupported.ll
AMDGPU: Avoid report_fatal_error for unsupported ds_ordered_count (#145172)
2025-06-26 14:06:05 +09:00
llvm.amdgcn.ds.ordered.add.gfx10.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.ordered.add.gfx11.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.ordered.add.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.ordered.swap.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.permute.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.read.tr.gfx950.ll
AMDGPU: Add test which shows unnecessary register alignment (#158168)
2025-09-13 10:10:59 +09:00
llvm.amdgcn.ds.sub.gs.reg.rtn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ds.swizzle.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.dual_intersect_ray.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.exp2.ll
…
llvm.amdgcn.exp.bf16.ll
[AMDGPU] Add support for v_exp_bf16 on gfx1250 (#149229)
2025-07-17 08:46:01 -04:00
llvm.amdgcn.exp.compr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.exp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.exp.prim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.exp.row.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fcmp.w32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fcmp.w64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fdiv.fast.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fdot2.bf16.bf16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fdot2.f16.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fdot2.f32.bf16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fdot2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.flat.prefetch.ll
[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)
2025-08-12 09:35:19 +02:00
llvm.amdgcn.fma.legacy.ll
…
llvm.amdgcn.fmad.ftz.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fmad.ftz.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fmed3.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fmed3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fmul.legacy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fract.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.fract.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.frexp.exp.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.frexp.exp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.frexp.mant.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.frexp.mant.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.global.atomic.csub.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.global.atomic.ordered.add.b64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.global.load.async.to.lds.ll
[AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns (#143881)
2025-09-18 15:01:07 +02:00
llvm.amdgcn.global.load.lds.err.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.global.load.lds.gfx950.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.global.load.lds.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.global.load.tr-w32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.global.load.tr-w64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.global.prefetch.ll
[AMDGPU][GISel] Add inbounds flag to FLAT GISel tests (#153000)
2025-08-12 09:35:19 +02:00
llvm.amdgcn.global.store.async.from.lds.ll
[AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns (#143881)
2025-09-18 15:01:07 +02:00
llvm.amdgcn.groupstaticsize.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.icmp.w32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.icmp.w64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
llvm.amdgcn.iglp.opt.exp.large.mir
[AMDGPU]: Unpack packed instructions overlapped by MFMAs post-RA scheduling (#157968)
2025-09-19 09:41:02 -07:00
llvm.amdgcn.iglp.opt.exp.simple.ll
[AMDGPU] Add iglp_opt(3) for simple mfma / exp interleaving (#117269)
2024-12-06 15:19:07 -08:00
llvm.amdgcn.iglp.opt.exp.small.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.iglp.opt.ll
[DAG] Remove AssertZext if the input is masked (#146052)
2025-07-29 13:05:30 +02:00
llvm.amdgcn.iglp.opt.single.2b.mir
…
llvm.amdgcn.iglp.opt.single.2c.mir
…
llvm.amdgcn.image.a16.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.a16.encode.ll
[AMDGPU] Rename TH_STORE_RT_WB to TH_STORE_WB (#135171)
2025-04-10 16:01:55 +02:00
llvm.amdgcn.image.atomic.dim.gfx90a.ll
AMDGPU: Remove MIMG special case in adjustAllocatableRegClass (#158184)
2025-09-12 09:02:24 +00:00
llvm.amdgcn.image.atomic.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.atomic.flt.ll
…
llvm.amdgcn.image.atomic.pk.add.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.d16.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.dim.gfx90a.ll
Greedy: Make eviction broken hint cost use CopyCost units (#160084)
2025-09-23 08:03:01 +09:00
llvm.amdgcn.image.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Regenerate test case to cover gfx10 check lines. (#154909)
2025-08-22 15:00:28 +05:30
llvm.amdgcn.image.gather4.d16.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.gather4.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.gather4.o.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.getlod.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.load.2dmsaa.ll
[AMDGPU] Change placeholder from undef to poison (#130853)
2025-03-12 12:52:38 +00:00
llvm.amdgcn.image.load.a16.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.load.a16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.msaa.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.msaa.load.x.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.nsa.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.a16.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.cd.a16.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.cd.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.cd.g16.encode.ll
…
llvm.amdgcn.image.sample.cd.g16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.d16.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.dim.gfx90a.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.g16.a16.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.g16.encode.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
llvm.amdgcn.image.sample.g16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.sample.noret.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
llvm.amdgcn.image.sample.o.dim.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.store.a16.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.image.store.a16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.implicit.ptr.buffer.hsa.ll
…
llvm.amdgcn.implicit.ptr.buffer.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.implicitarg.ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.init.exec.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.init.exec.wave32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.init.whole.wave-w32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.init.whole.wave-w64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.interp.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.interp.inreg.ll
AMDGPU: Replace copy-to-mov-imm folding logic with class compat checks (#154501)
2025-08-26 23:41:35 +09:00
llvm.amdgcn.interp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.intersect_ray.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.inverse.ballot.i32.ll
AMDGPU: llvm.amdgcn.inverse.ballot needs to be convergent (#155725)
2025-08-27 19:40:27 -07:00
llvm.amdgcn.inverse.ballot.i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.is.private.ll
[AMDGPU] Fold copies of constant physical registers into their uses (#154410)
2025-09-17 10:49:34 -07:00
llvm.amdgcn.is.shared.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
llvm.amdgcn.kernarg.segment.ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.kill.ll
[AMDGPU] Generate some WQM/WWM tests (NFC) (#152635)
2025-08-08 14:10:13 +09:00
llvm.amdgcn.lds.direct.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.lds.kernel.id.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.lds.param.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.lerp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.load.monitor.gfx1250.ll
[AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns (#143881)
2025-09-18 15:01:07 +02:00
llvm.amdgcn.load.to.lds.gfx950.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.load.to.lds.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.load.tr.gfx1250.w32.ll
AMDGPU: Add test which shows unnecessary register alignment (#158168)
2025-09-13 10:10:59 +09:00
llvm.amdgcn.log.bf16.ll
[AMDGPU] Add support for v_log_bf16 on gfx1250 (#149201)
2025-07-16 19:09:34 -04:00
llvm.amdgcn.log.clamp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.log.ll
…
llvm.amdgcn.make.buffer.rsrc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.mbcnt.ll
…
llvm.amdgcn.mfma.bf16.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.mfma.form.ll
[AMDGPU] Provide control to force VGPR MFMA form (#148079)
2025-07-18 13:53:17 -07:00
llvm.amdgcn.mfma.gfx90a.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.mfma.gfx942.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.mfma.gfx950.bf16.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.mfma.gfx950.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.mfma.i8.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.mfma.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.mfma.xf32.gfx942.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.mov.dpp8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.mov.dpp.gfx1251.ll
[AMDGPU] gfx1251 VOP1 dpp support (#159637)
2025-09-18 13:42:06 -07:00
llvm.amdgcn.mov.dpp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.mqsad.pk.u16.u8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.mqsad.u32.u8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.msad.u8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.mul.i24.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.mul.u24.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.mulhi.i24.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.mulhi.u24.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.perm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.perm.pk.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
llvm.amdgcn.permlane16.swap.ll
[AMDGPU] Add support for v_permlane16_swap_b32 on gfx1250 (#149518)
2025-07-18 13:05:08 -04:00
llvm.amdgcn.permlane16.var.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.permlane32.swap.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.permlane64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.permlane64.ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.permlane.gfx1250.ll
[AMDGPU] gfx1250 v_permlane_* instructions (#151749)
2025-08-01 16:14:19 -07:00
llvm.amdgcn.permlane.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.permlane.ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.pops.exiting.wave.id.ll
…
llvm.amdgcn.prng.ll
[AMDGPU] Combine prng(undef) -> undef (#154160)
2025-08-18 12:13:16 -07:00
llvm.amdgcn.ps.live.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.qsad.pk.u16.u8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.quadmask.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.queue.ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.atomic.buffer.load.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.buffer.atomic.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.buffer.load.format.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.buffer.load.format.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.buffer.load.lds.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.buffer.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.buffer.load.tfe.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.buffer.store.format.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.ptr.buffer.atomic.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.ptr.buffer.load.bf16.xfail.ll
…
llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.load.format.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.raw.ptr.buffer.load.lds.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.ptr.buffer.store.bf16.xfail.ll
…
llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.store.format.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.store.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
Reapply [IR] Remove options to make scalable TypeSize access a warning (#156336)
2025-09-03 11:12:11 +02:00
llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.tbuffer.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.ptr.tbuffer.store.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.tbuffer.load.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.tbuffer.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.raw.tbuffer.store.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.rcp.bf16.ll
Reapply "[AMDGPU] gfx1250 trans instructions bf16 codegen tests update. NFC (#155310)" (#155515)
2025-08-27 09:13:34 +09:00
llvm.amdgcn.rcp.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.rcp.legacy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.rcp.ll
[AMDGPU] Remove UnsafeFPMath uses (#151079)
2025-07-31 17:36:57 +08:00
llvm.amdgcn.readfirstlane.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.readfirstlane.m0.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.readfirstlane.ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.readlane.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.readlane.ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.reduce.add.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.and.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.max.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.min.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.or.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.sub.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.umax.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.umin.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.xor.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.rsq.bf16.ll
[NFC][AMDGPU] Re-enable two tests previously disabled due to missing upstream features (#149568)
2025-07-18 17:04:34 -04:00
llvm.amdgcn.rsq.clamp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.rsq.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.rsq.legacy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.rsq.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.barrier.ll
AMDGPU/GFX12: Do not wait unnecessarily before barriers (#154970)
2025-08-23 00:07:59 -07:00
llvm.amdgcn.s.barrier.signal.isfirst.ll
[AMDGPU][SIInsertWaitcnts] Track SCC. Insert KM_CNT waits for SCC writes. (#157843)
2025-09-18 14:41:01 +02:00
llvm.amdgcn.s.barrier.signal.isfirst.mir
[AMDGPU][SIInsertWaitcnts] Track SCC. Insert KM_CNT waits for SCC writes. (#157843)
2025-09-18 14:41:01 +02:00
llvm.amdgcn.s.buffer.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.buffer.prefetch.data.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
llvm.amdgcn.s.dcache.inv.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
llvm.amdgcn.s.dcache.inv.vol.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
llvm.amdgcn.s.dcache.wb.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
llvm.amdgcn.s.dcache.wb.vol.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
llvm.amdgcn.s.decperflevel.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.get.waveid.in.workgroup.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.getpc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.getreg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.incperflevel.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.memrealtime.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.memtime.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.monitor.sleep.ll
AMDGPU: support s_monitor_sleep on gfx1250 (#146293)
2025-06-29 21:01:47 -07:00
llvm.amdgcn.s.nop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.prefetch.data.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
llvm.amdgcn.s.sethalt.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.setprio.inc.wg.ll
[AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (#145152)
2025-06-22 12:52:05 -07:00
llvm.amdgcn.s.setprio.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.setreg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.sleep.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.sleep.var.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.ttracedata.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.wait.event.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.wait.gfx12.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.s.wait.gfx1250.ll
AMDGPU: Implement s_wait_asynccnt and s_wait_tensorcnt for gfx1250 (#148292)
2025-07-11 15:07:21 -07:00
llvm.amdgcn.s.waitcnt_gfx1250.ll
[AMDGPU] gfx1250 waitcnt related codegen tests update. NFC (#155317)
2025-08-25 15:23:59 -07:00
llvm.amdgcn.s.waitcnt.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sad.hi.u8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sad.u8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sad.u16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sbfe.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sched.barrier.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sched.group.barrier.gfx11.ll
[DAG] Remove AssertZext if the input is masked (#146052)
2025-07-29 13:05:30 +02:00
llvm.amdgcn.sched.group.barrier.gfx12.ll
[DAG] Remove AssertZext if the input is masked (#146052)
2025-07-29 13:05:30 +02:00
llvm.amdgcn.sched.group.barrier.iterative.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.sched.group.barrier.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.sdot2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sdot4.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sdot8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sendmsg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sendmsg.rtn.ll
[AMDGPU] Add MSG_RTN_GET_CLUSTER_BARRIER_STATE (#157549)
2025-09-08 16:22:43 -07:00
llvm.amdgcn.set.inactive.chain.arg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.set.inactive.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sffbh.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sin.bf16.ll
[AMDGPU] Add support for v_sin_bf16 on gfx1250 (#149241)
2025-07-17 08:49:45 -04:00
llvm.amdgcn.sin.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sin.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.smfmac.gfx950.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
llvm.amdgcn.softwqm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sqrt.bf16.ll
[AMDGPU] Add support for v_sqrt_bf16 on gfx1250 (#148921)
2025-07-15 16:15:47 -04:00
llvm.amdgcn.sqrt.f16.ll
[AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)
2025-02-26 10:50:49 -05:00
llvm.amdgcn.sqrt.ll
…
llvm.amdgcn.struct.atomic.buffer.load.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
…
llvm.amdgcn.struct.buffer.atomic.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.load.format.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.load.format.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.load.format.v3f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.load.lds.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.load.tfe.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.struct.buffer.store.format.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.store.format.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] Adjust hard clause rules for gfx1250 (#152592)
2025-08-07 14:59:31 -07:00
llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
[AMDGPU] Fix bad removal of s_delay_alu (#145728)
2025-06-27 16:15:10 +02:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.load.format.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.amdgcn.struct.ptr.buffer.load.lds.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.store.format.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.buffer.store.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.tbuffer.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.ptr.tbuffer.store.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.tbuffer.load.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.tbuffer.load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.struct.tbuffer.store.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sudot4.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.sudot8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.tanh.ll
[AMDGPU] Add support for v_tanh_f16 on gfx1250 (#149439)
2025-07-18 00:21:04 -04:00
llvm.amdgcn.tbuffer.load.dwordx3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.tbuffer.store.dwordx3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.tensor.load.store.ll
AMDGPU: Implement tensor load and store instructions for gfx1250 (#146636)
2025-07-03 13:49:34 -07:00
llvm.amdgcn.trig.preop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.ubfe.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.udot2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.udot4.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.udot8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.unreachable.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
llvm.amdgcn.update.dpp.gfx90a.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.update.dpp.ll
[AMDGPU] Reenable BackOffBarrier on GFX11/12 (#155370)
2025-09-02 09:37:43 +02:00
llvm.amdgcn.waitcnt.out.order.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.wave.barrier.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.wave.id.ll
[AMDGPU] gfx1250 intrinscs codegen tests update. NFC (#155312)
2025-08-25 15:18:27 -07:00
llvm.amdgcn.wavefrontsize.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.wmma_32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.wmma_64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.wmma.gfx1250.w32.ll
[AMDGPU] Restrict scale operands of WMMA to low 256 VGPRs (#157526)
2025-09-08 15:44:51 -07:00
llvm.amdgcn.wmma.imm.gfx1250.w32.ll
[AMDGPU] Restrict scale operands of WMMA to low 256 VGPRs (#157526)
2025-09-08 15:44:51 -07:00
llvm.amdgcn.wmma.imod.gfx1250.w32.ll
[AMDGPU] Add gfx1250 wmma_scale[16]_f32_32x16x128_f4 instructions (#152194)
2025-08-05 15:15:21 -07:00
llvm.amdgcn.wmma.index.gfx1250.w32.ll
AMDGPU: Support intrinsic selection for gfx1250 wmma instructions (#148957)
2025-07-15 15:25:05 -07:00
llvm.amdgcn.workgroup.id.ll
…
llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
AMDGPU: Mark workitem ID intrinsics with range attribute (#136196)
2025-04-18 12:27:38 +02:00
llvm.amdgcn.workitem.id.ll
…
llvm.amdgcn.wqm.demote.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.wqm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.wqm.vote.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.writelane.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.amdgcn.writelane.ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.ceil.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.cos.bf16.ll
Reapply "[AMDGPU] gfx1250 trans instructions bf16 codegen tests update. NFC (#155310)" (#155515)
2025-08-27 09:13:34 +09:00
llvm.cos.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.cos.ll
…
llvm.dbg.value.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.exp2.bf16.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
llvm.exp2.ll
[NFC] #155740 post cleanup (#155966)
2025-08-29 12:45:38 +08:00
llvm.exp10.ll
[AMDGPU] Remove ApproxFuncFPMath uses (#155578)
2025-08-28 11:09:01 +08:00
llvm.exp.ll
[AMDGPU] Remove ApproxFuncFPMath uses (#155578)
2025-08-28 11:09:01 +08:00
llvm.floor.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.fma.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.fmuladd.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.fptrunc.round.err.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
llvm.fptrunc.round.ll
…
llvm.frexp.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
llvm.get.fpmode.ll
…
llvm.get.rounding.ll
[AMDGPU] Move GCNPreRAOptimizations after MachineScheduler (#116211)
2024-11-16 09:40:46 +00:00
llvm.is.fpclass.bf16.ll
[AMDGPU][True16][CodeGen] srl pattern for true16 mode (#132987)
2025-03-26 18:38:20 -04:00
llvm.is.fpclass.f16.ll
[AMDGPU][True16][CodeGen] Implement sgpr folding in true16 (#128929)
2025-04-02 16:08:26 -04:00
llvm.is.fpclass.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.ldexp.ll
[AMDGPU][True16][GlobalISel] Fix v2*16 build_vector patterns (#151496)
2025-08-04 13:06:06 +02:00
llvm.log2.bf16.ll
[AMDGPU] Add support for v_log_bf16 on gfx1250 (#149201)
2025-07-16 19:09:34 -04:00
llvm.log2.ll
[NFC] #155740 post cleanup (#155966)
2025-08-29 12:45:38 +08:00
llvm.log10.ll
[AMDGPU] Remove ApproxFuncFPMath uses (#155578)
2025-08-28 11:09:01 +08:00
llvm.log.ll
[AMDGPU] Remove ApproxFuncFPMath uses (#155578)
2025-08-28 11:09:01 +08:00
llvm.maximum.f16.ll
AMDGPU: Combine nnan fminimum/fmaximum to fminnum_ieee/fmaxnum_ieee (#142217)
2025-06-17 21:55:57 +09:00
llvm.maximum.f32.ll
AMDGPU: Combine nnan fminimum/fmaximum to fminnum_ieee/fmaxnum_ieee (#142217)
2025-06-17 21:55:57 +09:00
llvm.maximum.f64.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
llvm.maxnum.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.memcpy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.minimum.f16.ll
AMDGPU: Combine nnan fminimum/fmaximum to fminnum_ieee/fmaxnum_ieee (#142217)
2025-06-17 21:55:57 +09:00
llvm.minimum.f32.ll
AMDGPU: Combine nnan fminimum/fmaximum to fminnum_ieee/fmaxnum_ieee (#142217)
2025-06-17 21:55:57 +09:00
llvm.minimum.f64.ll
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
llvm.minnum.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.mulo.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.pow-gfx9.ll
…
llvm.pow.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
llvm.powi.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
llvm.prefetch.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
llvm.r600.cube.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
llvm.r600.dot4.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll
…
llvm.r600.recipsqrt.clamped.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.r600.recipsqrt.ieee.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.r600.tex.ll
…
llvm.rint.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.rint.f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.rint.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.round.f64.ll
[AMDGPU] Use "v_bfi_b32 x, 0, z" to implement (z & ~x) (#156636)
2025-09-03 11:00:03 +00:00
llvm.round.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
llvm.set.rounding.ll
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
2025-02-25 20:32:24 +05:30
llvm.sin.bf16.ll
Reapply "[AMDGPU] gfx1250 trans instructions bf16 codegen tests update. NFC (#155310)" (#155515)
2025-08-27 09:13:34 +09:00
llvm.sin.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.sin.ll
[DAGCombiner] Remove most UnsafeFPMath references (#146295)
2025-08-22 15:27:25 +08:00
llvm.sqrt.bf16.ll
[NFC][AMDGPU] Re-enable two tests previously disabled due to missing upstream features (#149568)
2025-07-18 17:04:34 -04:00
llvm.sqrt.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
llvm.trunc.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lo16-hi16-illegal-copy.mir
…
lo16-hi16-physreg-copy.mir
…
lo16-lo16-physreg-copy-agpr.mir
…
lo16-lo16-physreg-copy-sgpr.mir
…
load-constant-always-uniform.ll
Revert "[AMDGPU] SelectionDAG divergence tracking should take into account Target divergency. (#147560)" (#152548)
2025-08-08 09:05:59 +01:00
load-constant-f32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-constant-f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-constant-i1.ll
[AMDGPU] gfx1250 codegen load tests update. NFC. (#155305)
2025-08-25 15:09:41 -07:00
load-constant-i8.ll
[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDValue with just the frozen node (#150017)
2025-08-05 09:24:09 +01:00
load-constant-i16.ll
[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDValue with just the frozen node (#150017)
2025-08-05 09:24:09 +01:00
load-constant-i32.ll
[AMDGPU] gfx1250 codegen load tests update. NFC. (#155305)
2025-08-25 15:09:41 -07:00
load-constant-i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-global-f32.ll
[NFC][AMDGPU] Update tests to use autogened CHECKs (#140311)
2025-05-16 17:22:19 -07:00
load-global-f64.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
load-global-i1.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
load-global-i8.ll
[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDValue with just the frozen node (#150017)
2025-08-05 09:24:09 +01:00
load-global-i16.ll
Greedy: Take copy hints involving subregisters (#159570)
2025-09-19 09:37:36 +09:00
load-global-i32.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
load-global-i64.ll
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
2024-11-26 12:59:15 -05:00
load-hi16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-input-fold.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
load-lo16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-local-f32-no-ds128.ll
…
load-local-f32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-local-f64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-local-i1.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-local-i8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-local-i16.ll
Greedy: Take copy hints involving subregisters (#159570)
2025-09-19 09:37:36 +09:00
load-local-i32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-local-i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-local-redundant-copies.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-local.96.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-local.128.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-range-metadata-assert.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-range-metadata-sign-bits.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
load-select-ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
load-store-cnt.ll
[AMDGPU] Create new option for force flush load counter (#124974)
2025-01-30 11:14:38 -08:00
load-store-opt-addc0.mir
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
load-store-opt-dlc.mir
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
load-store-opt-ds-regclass-constrain.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
load-store-opt-scale-offset.mir
[AMDGPU] Prohibit load/store merge if scale_offset is set on gfx1250 (#149895)
2025-07-21 15:41:24 -07:00
load-store-opt-scc.mir
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
load-weird-sizes.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
local-64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
local-atomicrmw-fadd.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
local-atomicrmw-fmax.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
local-atomicrmw-fmin.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
local-atomicrmw-fsub.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
local-atomics64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
local-atomics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
local-memory.amdgcn.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
local-memory.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
local-memory.r600.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
local-stack-alloc-add-references.gfx8.mir
[AMDGPU] Fix the magic number RegisterClass for SReg_32 in test (#159761)
2025-09-19 14:14:33 +02:00
local-stack-alloc-add-references.gfx9.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
local-stack-alloc-add-references.gfx10.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
local-stack-alloc-block-sp-reference.ll
[AMDGPU] Do not fold an immediate into instructions with frame indexes (#151263)
2025-08-06 11:47:37 -07:00
local-stack-slot-offset.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
long-branch-reserve-register.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
loop_break.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
loop_exit_with_xor.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
loop_header_nopred.mir
[CodeGen][NPM] Port MachineBlockPlacement to NPM (#129828)
2025-03-14 10:31:53 +05:30
loop-address.ll
…
loop-idiom.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
loop-live-out-copy-undef-subrange.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
loop-on-function-argument.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
loop-prefetch-data.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
loop-prefetch.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lower-brcond-with-xor.ll
[AMDGPU] Support xor cond, -1 when lowering BRCOND (#160341)
2025-09-23 17:16:21 -04:00
lower-buffer-fat-pointers-calls.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
lower-buffer-fat-pointers-constants.ll
[AMDGPU][LowerBufferFatPointers] Fix lack of rewrite when loading/storing null (#154128)
2025-08-18 12:32:54 -05:00
lower-buffer-fat-pointers-contents-legalization.ll
[AMDGPULowerBufferFatPointers] Use InstSimplifyFolder during rewrites (#134137)
2025-04-03 10:12:18 -05:00
lower-buffer-fat-pointers-control-flow.ll
[AMDGPU] Prevent re-visits in LowerBufferFatPointers (#159168)
2025-09-16 18:02:18 -07:00
lower-buffer-fat-pointers-lastuse-metadata.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
lower-buffer-fat-pointers-mem-transfer.ll
[AMDGPU] Add a new amdgcn.load.to.lds intrinsic (#137425)
2025-05-19 07:15:04 -07:00
lower-buffer-fat-pointers-memops.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
lower-buffer-fat-pointers-nontemporal-metadata.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lower-buffer-fat-pointers-p7-in-memory.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
lower-buffer-fat-pointers-pointer-ops.ll
[AMDGPULowerBufferFatPointers] Handle ptrtoaddr by extending the offset
2025-08-09 16:28:12 -07:00
lower-buffer-fat-pointers-unoptimized-debug-data.ll
[RemoveDIs][AMDGPU] Replace defunct getAssignmentMarkers call (#153212)
2025-08-12 17:20:38 +01:00
lower-control-flow-live-intervals.mir
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
lower-control-flow-live-variables-update.mir
…
lower-control-flow-live-variables-update.xfail.mir
…
lower-control-flow-other-terminators.mir
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
lower-ctor-dtor-constexpr-alias.ll
…
lower-ctor-dtor-declaration.ll
…
lower-ctor-dtor-existing.ll
…
lower-ctor-dtor.ll
…
lower-empty-ctor-dtor.ll
…
lower-i1-copies-clear-kills.mir
…
lower-i1-copies-implicit-def-unstructured-loop.mir
…
lower-indirect-lds-references.ll
[AMDGPU][Verifier] Check address space of alloca instruction (#135820)
2025-04-26 00:54:00 -04:00
lower-intrinsics-barriers.ll
AMDGPU: Refactor lowering of s_barrier to split barriers (#154648)
2025-08-28 07:01:20 -07:00
lower-intrinsics-cluster-barrier.ll
[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)
2025-09-16 14:49:48 -07:00
lower-intrinsics-split-barriers.ll
AMDGPU: Refactor lowering of s_barrier to split barriers (#154648)
2025-08-28 07:01:20 -07:00
lower-kernargs.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
lower-kernel-and-module-lds.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
lower-kernel-lds-constexpr.ll
…
lower-kernel-lds-super-align.ll
…
lower-kernel-lds.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
lower-lds-struct-aa-memcpy.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
lower-lds-struct-aa-merge.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
lower-lds-struct-aa.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
lower-lds-with-alias-scope.ll
[AMDGPU] Correctly merge noalias scopes during lowering of LDS data. (#131664)
2025-04-28 14:02:18 -05:00
lower-lds-with-noalias.ll
[AMDGPU] Correctly merge noalias scopes during lowering of LDS data. (#131664)
2025-04-28 14:02:18 -05:00
lower-mem-intrinsics-threshold.ll
…
lower-mem-intrinsics.ll
[AMDGPU] Remove special cases in TTI::getMemcpyLoop(Residual)LoweringType (#125507)
2025-02-04 08:18:24 +01:00
lower-module-lds-all-indirect-accesses.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
lower-module-lds-check-metadata.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
lower-module-lds-constantexpr-phi.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
lower-module-lds-constantexpr.ll
…
lower-module-lds-inactive.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
lower-module-lds-indirect-extern-uses-max-reachable-alignment.ll
Revert "[AMDGPU] Add flag to prevent reruns of LowerModuleLDS (#129520)"
2025-05-17 21:41:59 -04:00
lower-module-lds-offsets.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lower-module-lds-single-var-ambiguous.ll
AMDGPU: Use reportFatalUsageError in AMDGPULowerModuleLDS (#145130)
2025-06-21 12:18:25 +09:00
lower-module-lds-single-var-unambiguous.ll
[AMDGPU] Correctly merge noalias scopes during lowering of LDS data. (#131664)
2025-04-28 14:02:18 -05:00
lower-module-lds-used-list.ll
…
lower-module-lds-via-hybrid.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lower-module-lds-via-table.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lower-module-lds-zero-size-arr.ll
…
lower-module-lds.ll
…
lower-multiple-ctor-dtor.ll
…
lower-range-metadata-intrinsic-call.ll
…
lower-term-opcodes.mir
[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)
2025-01-20 16:34:01 +05:30
lower-work-group-id-intrinsics-hsa.ll
[AMDGPU] Support lowering of cluster related instrinsics (#157978)
2025-09-12 21:11:17 -04:00
lower-work-group-id-intrinsics-opt.ll
[AMDGPU] Support lowering of cluster related instrinsics (#157978)
2025-09-12 21:11:17 -04:00
lower-work-group-id-intrinsics-pal.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lower-work-group-id-intrinsics.ll
[AMDGPU] Support lowering of cluster related instrinsics (#157978)
2025-09-12 21:11:17 -04:00
lrint.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
lround.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
lshl64-to-32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lshl-add-u64.ll
[AMDGPU] Add few missing gfx1250 codegen tests. NFC (#155314)
2025-08-25 15:22:33 -07:00
lshr.v2i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
lto-lower-module-lds.ll
…
machine-cse-commute-target-flags.mir
…
machine-cse-ssa.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
machine-function-info-cwsr.ll
[AMDGPU] AMDGPUPromoteAlloca: increase default max-regs to 32 (#155076)
2025-08-26 09:30:16 +09:00
machine-scheduler-sink-trivial-remats-attr.mir
[AMDGPU][Scheduler] Consistent occupancy calculation during rematerialization (#149224)
2025-08-08 14:26:04 +02:00
machine-scheduler-sink-trivial-remats-debug.mir
Reapply "[AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during scheduling (#125885)" (#139548)
2025-05-13 11:11:00 +02:00
machine-scheduler-sink-trivial-remats.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
machine-sink-cycle.mir
[MachineSink] Fix typo in loop sinking (#127133)
2025-03-03 17:30:12 -08:00
machine-sink-ignorable-exec-use.mir
[AMDGPU] Fix to prevent sinking of PERMLANE_SWAP instruction (#144423)
2025-06-20 20:44:23 +09:00
machine-sink-lane-mask.mir
[MachineSink] Extend loop sinking capability (#117247)
2025-01-23 17:08:23 -08:00
machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
[AMDGPU] Select (xor i1 (divergent trunc:i32 x), -1) -> cmp_neq x, 1 (#133698)
2025-04-11 13:03:01 +02:00
machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
…
machine-sink-temporal-divergence-swdev407790.ll
[SeparateConstOffsetFromGEP] propagate const offset through GEP chains (#143470)
2025-08-21 13:37:24 -07:00
machine-sink-temporal-divergence-swdev407790.mir
[CodeGen][NewPM] Port MachineSink to NPM (#115434)
2025-03-03 15:49:37 +05:30
machinelicm-convergent.mir
…
machinelicm-copy-like-instrs.mir
…
machinelicm-undef-use.mir
…
macro-fusion-cluster-vcc-uses.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
mad24-get-global-id.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mad_64_32.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
mad_int24.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mad_u64_u32.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
mad_uint24.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mad-combine.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
mad-mix-bf16.ll
[AMDGPU] Removed extra blank lines from tests. NFC. (#152612)
2025-08-08 00:53:00 -07:00
mad-mix-hi-bf16.ll
[AMDGPU][gfx12] Clean-up implementation of waits before SCOPE_SYS stores (#150587)
2025-07-28 15:38:46 +02:00
mad-mix-hi.ll
[AMDGPU][True16][GlobalISel] Fix v2*16 build_vector patterns (#151496)
2025-08-04 13:06:06 +02:00
mad-mix-lo-bf16.ll
[AMDGPU] Removed extra blank lines from tests. NFC. (#152612)
2025-08-08 00:53:00 -07:00
mad-mix-lo.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
mad-mix.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mad.u16.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
madak-inline-constant.mir
[AMDGPU] Skip debug uses in SIInstrInfo::foldImmediate (#160102)
2025-09-22 15:22:09 +01:00
madak.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
madmk.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mai-hazards-gfx90a.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mai-hazards-gfx942.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mai-hazards-mfma-scale.gfx950.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mai-hazards.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mai-inline.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
make-buffer-rsrc-lds-fails.ll
[AMDGPU] Generalize amdgcn.make.buffer.rsrc to fat pointers (#126828)
2025-02-18 14:15:28 -06:00
masked-load-vectortypes.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
match-perm-extract-vector-elt-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
materialize-frame-index-sgpr.gfx10.ll
Re-apply "[AMDGPU] Fix test failures when expensive checks are enabled (#130644)"
2025-03-14 09:49:20 +01:00
materialize-frame-index-sgpr.ll
Re-apply "[AMDGPU] Fix test failures when expensive checks are enabled (#130644)"
2025-03-14 09:49:20 +01:00
max3.ll
AMDGPU: Support V_PK_ADD_{MIN|MAX}_{I|U}16 and V_{MIN|MAX}3_{I|U}16 on gfx1250 (#150155)
2025-07-23 00:17:22 -07:00
max-hard-clause-length.ll
…
max-literals.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
max-sgprs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
max.i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
max.ll
[AMDGPU] gfx1250 V_{MIN|MAX}_{I|U}64 opcodes (#151256)
2025-07-29 19:13:51 -07:00
maximumnum.bf16.ll
[AMDGPU][True16][Codegen] remove packed build_vector pattern from true16 (#148715)
2025-07-18 12:55:11 -04:00
maximumnum.ll
AMDGPU: Directly select minimumnum/maximumnum with ieee_mode=0 (#141903)
2025-06-18 00:27:41 +09:00
mcexpr-knownbits-assign-crash-gh-issue-110930.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
mcp-aligned-vgprs.mir
…
mcp-implicit-clobber.mir
…
mcp-overlap-after-propagation.mir
…
mcp-use-before-def.mir
…
mdt-preserving-crash.ll
MachineLICM: Merge logic for implicit and explicit definitions.
2025-07-09 13:02:15 -07:00
med3-knownbits.ll
…
med3-no-simplify.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mem-builtins.ll
…
memcpy-crash-issue63986.ll
Revert "[InstSimplify] Fold getelementptr inbounds null, idx -> null (#130742)" (#138168)
2025-05-01 14:21:59 -07:00
memcpy-fixed-align.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memcpy-inline-fails.ll
…
memcpy-libcall.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memcpy-param-combinations.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memcpy-scalar-load.ll
…
memcpy-scoped-aa.ll
…
memintrinsic-unroll.ll
[LICM] Do not reassociate constant offset GEP (#151492)
2025-08-01 09:43:15 +02:00
memmove-param-combinations.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memmove-scalar-load.ll
…
memmove-var-size.ll
[LICM] Do not reassociate constant offset GEP (#151492)
2025-08-01 09:43:15 +02:00
memory_clause.ll
[DAG] Remove AssertZext if the input is masked (#146052)
2025-07-29 13:05:30 +02:00
memory_clause.mir
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
memory-legalizer-atomic-insert-end.mir
[AMDGPU] auto update some tests to prepare for future changes
2025-07-23 10:34:53 +05:30
memory-legalizer-barriers-mmra.ll
[AMDGPU] Insert waitcnt for non-global fence release in GFX12 (#159282)
2025-09-23 11:52:38 +02:00
memory-legalizer-barriers.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-fence-mmra-global.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-fence-mmra-local.ll
[AMDGPU] Insert waitcnt for non-global fence release in GFX12 (#159282)
2025-09-23 11:52:38 +02:00
memory-legalizer-fence.ll
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
memory-legalizer-flat-agent.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-flat-cluster.ll
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
memory-legalizer-flat-lastuse.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-flat-nontemporal.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-flat-singlethread.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-flat-system.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-flat-volatile.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-flat-wavefront.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-flat-workgroup.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-global-agent.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-global-cluster.ll
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
memory-legalizer-global-lastuse.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-global-nontemporal.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-global-singlethread.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-global-system.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-global-volatile.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-global-wavefront.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-global-workgroup.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-invalid-addrspace.mir
AMDGPU: Migrate more tests away from undef (#131314)
2025-03-17 15:57:47 +07:00
memory-legalizer-invalid-syncscope.ll
…
memory-legalizer-local-agent.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-local-cluster.ll
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
memory-legalizer-local-nontemporal.ll
[AMDGPU][gfx1250] Add memory legalizer tests (NFC) (#154725)
2025-08-22 10:14:09 +02:00
memory-legalizer-local-singlethread.ll
[AMDGPU][gfx1250] Add memory legalizer tests (NFC) (#154725)
2025-08-22 10:14:09 +02:00
memory-legalizer-local-system.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-local-volatile.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-local-wavefront.ll
[AMDGPU][gfx1250] Add memory legalizer tests (NFC) (#154725)
2025-08-22 10:14:09 +02:00
memory-legalizer-local-workgroup.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
memory-legalizer-local.mir
[AMDGPU] auto update some tests to prepare for future changes (#147256)
2025-07-08 15:00:27 +05:30
memory-legalizer-multiple-mem-operands-atomics.mir
[AMDGPU] auto update some tests to prepare for future changes
2025-07-23 10:34:53 +05:30
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
memory-legalizer-private-agent.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-private-cluster.ll
[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)
2025-09-10 11:41:43 +02:00
memory-legalizer-private-lastuse.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
memory-legalizer-private-nontemporal.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
memory-legalizer-private-singlethread.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-private-system.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-private-volatile.ll
[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)
2025-04-15 15:17:33 -07:00
memory-legalizer-private-wavefront.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-private-workgroup.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
memory-legalizer-region.mir
[AMDGPU] auto update some tests to prepare for future changes (#147256)
2025-07-08 15:00:27 +05:30
memory-legalizer-store-infinite-loop.ll
[NFC][AMDGPU] Auto generate check lines for some codegen tests (#137534)
2025-04-28 09:25:05 -04:00
merge-buffer-gfx12.mir
…
merge-buffer.mir
…
merge-consecutive-wait-alus.mir
[AMDGPU] Merge consecutive wait_alu instruction (#128916)
2025-03-12 10:27:27 +01:00
merge-flat-load-store.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
merge-flat-saddr-load-store.mir
[AMDGPU] Support merging of flat GVS ops (#154200)
2025-08-18 14:31:41 -07:00
merge-flat-with-global-load-store.mir
AMDGPU: Replace undef references with poison in some MIR tests (#131254)
2025-03-14 14:45:49 +07:00
merge-global-load-store.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
merge-image-load-gfx10.mir
…
merge-image-load-gfx11.mir
…
merge-image-load-gfx12.mir
…
merge-image-load.mir
…
merge-image-sample-gfx10.mir
…
merge-image-sample-gfx11.mir
…
merge-image-sample-gfx12.mir
…
merge-image-sample.mir
…
merge-load-store-agpr.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
merge-load-store-physreg.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
merge-load-store-vreg.mir
AMDGPU: Migrate more tests away from undef (#131314)
2025-03-17 15:57:47 +07:00
merge-load-store.mir
AMDGPU: Replace some test i32 undef uses with poison (#131092)
2025-03-13 20:10:17 +07:00
merge-m0.mir
…
merge-out-of-order-ldst.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
merge-out-of-order-ldst.mir
AMDGPU: Replace more undef test pointer uses with poison (#131102)
2025-03-14 09:53:45 +07:00
merge-s-load.mir
…
merge-sbuffer-load.mir
…
merge-store-crash.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
merge-store-usedef.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
merge-stores.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
merge-tbuffer-gfx9.mir
[NFC][AMDGPU] Split merge-tbuffer.mir into separate tests for gfx9, gfx10, and gfx11 (#148786)
2025-07-16 10:29:02 +08:00
merge-tbuffer-gfx10.mir
[NFC][AMDGPU] Split merge-tbuffer.mir into separate tests for gfx9, gfx10, and gfx11 (#148786)
2025-07-16 10:29:02 +08:00
merge-tbuffer-gfx11.mir
[AMDGPU] Support merging 16-bit and 8-bit TBUFFER load/store instruction (#145078)
2025-08-20 21:16:25 +08:00
merge-tbuffer-gfx12.mir
…
merged-bfx-opt.ll
[DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences (#146054)
2025-07-30 10:27:19 +02:00
mesa3d.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mesa_regression.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mfma-bf16-vgpr-cd-select.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mfma-cd-select.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mfma-loop.ll
AMDGPU: Add more mfma loop test cases (#159492)
2025-09-19 09:36:46 +09:00
mfma-no-register-aliasing.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mfma-vgpr-cd-select-gfx942.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mfma-vgpr-cd-select.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
min3.ll
AMDGPU: Support V_PK_ADD_{MIN|MAX}_{I|U}16 and V_{MIN|MAX}3_{I|U}16 on gfx1250 (#150155)
2025-07-23 00:17:22 -07:00
min-waves-per-eu-not-respected.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
min.ll
[DAG] Always use stack to promote bitcast when the source is vector (#151065)
2025-08-02 15:32:10 -07:00
minimummaximum.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
minimumnum.bf16.ll
[AMDGPU][True16][Codegen] remove packed build_vector pattern from true16 (#148715)
2025-07-18 12:55:11 -04:00
minimumnum.ll
AMDGPU: Directly select minimumnum/maximumnum with ieee_mode=0 (#141903)
2025-06-18 00:27:41 +09:00
minmax.ll
[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)
2025-08-25 14:32:08 -07:00
mir-print-dead-csr-fi.mir
…
misched-killflags.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
missing-store.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mixed_wave32_wave64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mixed-vmem-types.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mixed-wave32-wave64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mmo-target-flags-folding.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
mmra.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
mode-register-fpconstrain.ll
…
mode-register-fptrunc.gfx11plus-fake16.mir
[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)
2025-03-04 10:51:03 +05:30
mode-register-fptrunc.gfx11plus.mir
[AMDGPU][True16][CodeGen] true16 codegen pat for fptrunc_round (#124044)
2025-01-30 18:31:52 -05:00
mode-register-fptrunc.mir
[AMDGPU][True16][CodeGen] true16 codegen pat for fptrunc_round (#124044)
2025-01-30 18:31:52 -05:00
mode-register.mir
[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)
2025-03-04 10:51:03 +05:30
module-lds-false-sharing.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
move-addr64-rsrc-dead-subreg-writes.ll
…
move-load-addr-to-valu-flat.mir
[AMDGPU] add tests for Change FLAT SADDR to VADDR form in moveToVALU. NFC. (#149392)
2025-07-17 14:18:52 -07:00
move-load-addr-to-valu.mir
…
move-to-valu-addsubu64.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-atomicrmw-system.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
move-to-valu-atomicrmw.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
move-to-valu-ctlz-cttz.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
move-to-valu-lshlrev.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-pseudo-scalar-trans-f16-fake16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-pseudo-scalar-trans-f16-true16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
move-to-valu-pseudo-scalar-trans.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-vimage-vsample.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-worklist.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
movreld-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
movrels-bug.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
mubuf-legalize-operands-non-ptr-intrinsics.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
mubuf-legalize-operands.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
mubuf-legalize-operands.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
mubuf-offset-private.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
mubuf-shader-vgpr-non-ptr-intrinsics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mubuf-shader-vgpr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mubuf.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mul24-pass-ordering.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
mul_int24.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mul_uint24-amdgcn.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
mul_uint24-r600.ll
…
mul.i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
mul.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
multi-call-resource-usage-mcexpr.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
multi-divergent-exit-region.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
multi-dword-vgpr-spill.ll
…
multilevel-break.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
naked-fn-with-frame-pointer.ll
…
nand.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
narrow_math_for_and.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
need-fp-from-vgpr-spills.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
neg_ashr64_reduce.ll
[AMDGPU] Create hi-half of 64-bit ashr with mov of -1 (#146569)
2025-07-09 12:02:51 -04:00
neighboring-mfma-padding.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
nested-calls.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
nested-loop-conditions.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
no-bundle-asm.ll
…
no-corresponding-integer-type.ll
…
no-dup-inst-prefetch.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
no-fold-accvgpr-mov.ll
AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)
2025-07-18 17:15:38 +09:00
no-fold-accvgpr-mov.mir
AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)
2025-07-18 17:15:38 +09:00
no-fold-accvgpr-read.mir
AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)
2025-07-18 17:15:38 +09:00
no-folding-imm-to-inst-with-fi.ll
[AMDGPU] Do not fold an immediate into instructions with frame indexes (#151263)
2025-08-06 11:47:37 -07:00
no-hsa-graphics-shaders.ll
[AMDGPU] Change handling of unsupported non-compute shaders with HSA (#126798)
2025-02-13 22:23:08 +07:00
no-initializer-constant-addrspace.ll
…
no-remat-indirect-mov.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
no-shrink-extloads.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
no-source-locations-in-prologue.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
noclobber-barrier.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
non-entry-alloca.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
noop-shader-O0.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
nop-data.ll
…
nor-divergent-lanemask.ll
[AMDGPU] (x or y) xor -1 -> x nor y (#130264)
2025-03-28 11:20:17 +01:00
nor.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
not-scalarize-volatile-load.ll
…
nsa-reassign.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
nsa-reassign.mir
…
nsa-vmem-hazard.mir
…
nullptr-long-address-spaces.ll
AMDGPU: Fix broken XFAILed test for fat pointer null initializers (#142015)
2025-05-30 07:55:46 +02:00
nullptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
occupancy-levels.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
offset-split-flat.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
offset-split-global.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
omod-nsz-flag.mir
…
omod.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
opencl-image-metadata.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
opencl-printf-and-hostcall.ll
AMDGPU: Replace ptr undef in tests with poison (#131050)
2025-03-13 13:34:52 +07:00
opencl-printf-pipeline.ll
…
opencl-printf-unsupported.ll
…
opencl-printf.ll
[AMDGPU] Support 'F' and 'A' conversion specifiers with ocl printf (#148784)
2025-07-15 13:24:08 +05:30
operand-folding.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
operand-spacing.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
opt_exec_copy_fold.mir
…
opt-exec-masking-pre-ra-update-liveness-wave32.mir
…
opt-exec-masking-pre-ra-update-liveness.mir
…
opt-sgpr-to-vgpr-copy.mir
Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#135243)
2025-04-10 22:18:21 +02:00
opt-vgpr-live-range-verifier-error.mir
[AMDGPU][NewPM] Port SIOptimizeVGPRLiveRange pass to NPM. (#117686)
2024-11-29 09:11:24 +05:30
optimize-compare.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
optimize-compare.mir
…
optimize-exec-copies-extra-insts-after-copy.mir
[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)
2025-01-20 16:34:01 +05:30
optimize-exec-mask-pre-ra-alloc-failure.mir
…
optimize-exec-mask-pre-ra-def-after-use.mir
…
optimize-exec-mask-pre-ra-loop-phi.mir
…
optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
…
optimize-exec-masking-pre-ra.mir
…
optimize-exec-masking-strip-terminator-bits.mir
…
optimize-if-exec-masking.mir
AMDGPU: Replace undef references with poison in some MIR tests (#131254)
2025-03-14 14:45:49 +07:00
optimize-negated-cond-exec-masking-wave32.mir
…
optimize-negated-cond-exec-masking.mir
…
optimize-negated-cond.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
or3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
or.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
or.r600.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
overlapping-tuple-copy-implicit-op-failure.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
pack.v2f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
pack.v2i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
packed-fp32.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
packed-op-sel.ll
[AMDGPU][SIInsertWaitCnts] skip meta instructions early (#145720)
2025-07-01 22:02:48 +05:30
packetizer.ll
…
pal-metadata-3.0-callable-dvgpr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
pal-metadata-3.0-callable.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
pal-metadata-3.0-dvgpr.ll
[AMDGPU] Enable FWD_PROGRESS bit for GFX10+ on PAL (#139895)
2025-07-21 17:29:06 +01:00
pal-metadata-3.0.gfx1250.ll
[AMDGPU] Remove wave64 functions (#153690)
2025-08-14 15:54:33 -07:00
pal-metadata-3.0.ll
[AMDGPU] Enable FWD_PROGRESS bit for GFX10+ on PAL (#139895)
2025-07-21 17:29:06 +01:00
pal-metadata-3.6.ll
[AMDGPU] Enable FWD_PROGRESS bit for GFX10+ on PAL (#139895)
2025-07-21 17:29:06 +01:00
pal-simple-indirect-call.ll
[AMDGPU][Attributor] Remove final update of waves-per-eu after the attributor run (#155246)
2025-08-27 14:11:03 -04:00
pal-userdata-regs.ll
…
parallelandifcollapse.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
parallelorifcollapse.ll
…
partial-forwarding-hazards.mir
…
partial-regcopy-and-spill-missed-at-regalloc.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
partial-sgpr-to-vgpr-spills.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
partial-shift-shrink.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
partially-dead-super-register-immediate.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
peephole-fold-imm-multi-use.mir
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
peephole-fold-imm.mir
AMDGPU: Simplify foldImmediate with register class based checks (#154682)
2025-08-23 02:13:50 +00:00
peephole-opt-fold-reg-sequence-subreg.mir
PeepholeOpt: Handle subregister compose when looking through reg_sequence (#127051)
2025-02-18 08:07:29 +07:00
peephole-opt-regseq-removal.mir
PeepholeOpt: Do not skip reg_sequence sources with subregs (#125667)
2025-03-13 21:49:16 +07:00
pei-amdgpu-cs-chain-preserve.mir
[AMDGPU] Fix restores in chain functions (#116193)
2024-11-20 10:43:59 +01:00
pei-amdgpu-cs-chain.mir
[AMDGPU] Fix restores in chain functions (#116193)
2024-11-20 10:43:59 +01:00
pei-build-av-spill.mir
[AMDGPU] Remove implicit definition of register group when restoring the last sub-register after a spill (#133986)
2025-05-05 20:17:36 +02:00
pei-build-spill-partial-agpr.mir
…
pei-build-spill.mir
[AMDGPU] Remove implicit definition of register group when restoring the last sub-register after a spill (#133986)
2025-05-05 20:17:36 +02:00
pei-reg-scavenger-position.mir
…
pei-scavenge-sgpr-carry-out.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
pei-scavenge-sgpr-gfx9.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
pei-scavenge-sgpr.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
pei-scavenge-vgpr-spill.mir
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
pei-vgpr-block-spill-csr.mir
[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)
2025-09-03 16:25:18 -07:00
perfhint.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
permlane16_opsel.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
permlane16_var-op-sel.ll
…
permlane-op-sel.ll
…
permute_i8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
permute.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
phi-elimination-assertion.mir
…
phi-elimination-end-cf.mir
AMDGPU: Replace more undef test pointer uses with poison (#131102)
2025-03-14 09:53:45 +07:00
phi-vgpr-input-moveimm.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
phys-partial-liveness.mir
…
pk_max_f16_literal.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
post-ra-sched-kill-bundle-use-inst.mir
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
2025-02-05 12:45:59 +05:30
post-ra-sched-reset.mir
…
post-ra-soft-clause-dbg-info.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
postra-bundle-memops.mir
[AMDGPU] Avoid bundling a SCHED_BARRIER with memops (#153533)
2025-08-27 17:09:27 -05:00
postra-bundle-vimage-vsample-gfx12.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
postra-machine-sink.mir
[CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM (#129690)
2025-07-10 13:10:46 +05:30
postra-norename.mir
…
postra-sched-attribute.ll
[AMDGPU] Support function attribute to override postRA scheduling direction (#147708)
2025-08-01 16:07:09 +08:00
postra-sink-update-dependency.mir
[CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM (#129690)
2025-07-10 13:10:46 +05:30
power-sched-no-instr-sunit.mir
…
pr51516.mir
MachineScheduler: Improve instruction clustering (#137784)
2025-06-05 15:28:04 +08:00
pr155452.ll
[DAG] ComputeNumSignBits - ISD::EXTRACT_ELEMENT needs to return at least 1 (#155455)
2025-08-26 14:28:02 -07:00
predicate-dp4.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
predicates.ll
…
preload-implicit-kernargs-debug-info.ll
[clang] Simplify device kernel attributes (#137882)
2025-06-05 14:15:38 +00:00
preload-implicit-kernargs-IR-lowering.ll
[AMDGPU] Move kernarg preload logic to separate pass (#130434)
2025-05-11 21:18:11 -07:00
preload-implicit-kernargs.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
preload-kernarg-header.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
preload-kernargs-IR-lowering.ll
[AMDGPU] Move kernarg preload logic to separate pass (#130434)
2025-05-11 21:18:11 -07:00
preload-kernargs.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
preserve-hi16.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
preserve-only-inactive-lane.mir
…
preserve-user-waitcnt.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
preserve-wwm-copy-dst-reg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
prevent-fmul-hoist-ir.ll
Revert "[AMDGPU] Implement IR variant of isFMAFasterThanFMulAndFAdd (… (#145580)
2025-06-24 16:10:27 -04:00
print-pipeline-passes.ll
[AMDGPU] Only run AMDGPUPrintfRuntimeBindingPass at non-prelink phase (#125162)
2025-02-10 08:24:50 -05:00
printf_builtin.ll
…
printf_nobuiltin.ll
…
printf-defined.ll
…
printf-existing-format-strings.ll
…
private-access-no-objects.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
private-memory-atomics.ll
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
2025-09-03 20:04:01 +01:00
private-memory-r600.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
prologue-epilogue-markers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
promote-alloca-addrspacecast.ll
…
promote-alloca-array-aggregate.ll
AMDGPU: Use freeze poison instead of undef in alloca promotion (#131285)
2025-03-18 17:27:02 +07:00
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
…
promote-alloca-budget-exhausted.ll
AMDGPU: Use freeze poison instead of undef in alloca promotion (#131285)
2025-03-18 17:27:02 +07:00
promote-alloca-calling-conv.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
promote-alloca-globals.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
promote-alloca-invariant-markers.ll
[NFC][AMDGPU] Improve code introduced in #124607 (#124672)
2025-01-27 22:57:16 -05:00
promote-alloca-lifetime.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
promote-alloca-loadstores.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
promote-alloca-max-regs.ll
[AMDGPU] AMDGPUPromoteAlloca: increase default max-regs to 32 (#155076)
2025-08-26 09:30:16 +09:00
promote-alloca-mem-intrinsics.ll
[AMDGPU] AMDGPUPromoteAlloca: increase default max-regs to 32 (#155076)
2025-08-26 09:30:16 +09:00
promote-alloca-memset.ll
AMDGPU: Use freeze poison instead of undef in alloca promotion (#131285)
2025-03-18 17:27:02 +07:00
promote-alloca-multidim.ll
[AMDGPU] Generate canonical additions in AMDGPUPromoteAlloca (#157810)
2025-09-10 14:46:46 +02:00
promote-alloca-negative-index.ll
[AMDGPU] Generate canonical additions in AMDGPUPromoteAlloca (#157810)
2025-09-10 14:46:46 +02:00
promote-alloca-no-opts.ll
[AMDGPU] Extend promotion of alloca to vectors (#127973)
2025-03-12 15:11:30 +09:00
promote-alloca-non-byte-sizes.ll
[AMDGPU] Avoid crashes for non-byte-sized types in PromoteAlloca (#134042)
2025-04-14 09:13:54 +02:00
promote-alloca-non-constant-index.ll
AMDGPU: Use freeze poison instead of undef in alloca promotion (#131285)
2025-03-18 17:27:02 +07:00
promote-alloca-padding-size-estimate.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
promote-alloca-pointer-array.ll
AMDGPU: Use freeze poison instead of undef in alloca promotion (#131285)
2025-03-18 17:27:02 +07:00
promote-alloca-scoring.ll
…
promote-alloca-shufflevector.ll
[AMDGPU] PromoteAlloca: handle out-of-bounds GEP for shufflevector (#139700)
2025-05-21 15:28:30 +02:00
promote-alloca-stored-pointer-value.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
promote-alloca-strip-abi-opt-attributes.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
promote-alloca-subvecs.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
promote-alloca-to-lds-constantexpr-use.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
promote-alloca-to-lds-icmp.ll
…
promote-alloca-to-lds-phi.ll
…
promote-alloca-to-lds-select.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-vector-gep-of-gep.ll
[AMDGPU] Generate canonical additions in AMDGPUPromoteAlloca (#157810)
2025-09-10 14:46:46 +02:00
promote-alloca-vector-gep.ll
…
promote-alloca-vector-to-vector.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
promote-alloca-vgpr-ratio.ll
AMDGPU: Use freeze poison instead of undef in alloca promotion (#131285)
2025-03-18 17:27:02 +07:00
promote-alloca-volatile.ll
…
promote-constOffset-to-imm-gfx10.mir
…
promote-constOffset-to-imm-gfx90a.mir
…
promote-constOffset-to-imm.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
promote-constOffset-to-imm.mir
…
promote-kernel-arguments.ll
AMDGPU: Replace undef global initializers in tests with poison (#131051)
2025-03-13 13:41:03 +07:00
promote-vect3-load.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
propagate-amdgpu-cluster-dims.ll
[NFC][AMDGPU] Add a missing test case about cluster dims (#159179)
2025-09-16 22:56:24 -04:00
propagate-attributes-bitcast-function.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
propagate-flat-work-group-size.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
propagate-waves-per-eu.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
ps-shader-arg-count.ll
[AMDGPU] AsmPrinter: Unify arg handling (#151672)
2025-08-08 12:00:37 +02:00
pseudo-scalar-transcendental.ll
[AMDGPU] Add another test showing unwanted VALU codegen (#145062)
2025-06-20 17:54:44 +01:00
pseudo-scalar-transcendental.mir
…
ptr-arg-dbg-value.ll
…
ptr-buffer-alias-scheduling.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ptradd-sdag-mubuf.ll
[AMDGPU][SDAG] Handle ISD::PTRADD in various special cases (#145330)
2025-09-19 10:19:38 +02:00
ptradd-sdag-optimizations.ll
[AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR (#146075)
2025-09-19 11:58:41 +02:00
ptradd-sdag-undef-poison.ll
[AMDGPU][SDAG] Add ISD::PTRADD DAG combines (#142739)
2025-06-26 09:40:04 +02:00
ptradd-sdag.ll
[AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns (#143881)
2025-09-18 15:01:07 +02:00
ptrmask.ll
[AMDGPU] Set AS8 address width to 48 bits
2025-05-19 17:26:05 -07:00
pv-packing.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
pv.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
r600-constant-array-fixup.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
r600-encoding.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
r600-export-fix.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
r600-infinite-loop-bug-while-reorganizing-vector.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
r600-legalize-umax-bug.ll
…
r600.add.ll
…
r600.alu-limits.ll
…
r600.amdgpu-alias-analysis.ll
…
r600.bitcast.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
r600.extract-lowbits.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
r600.func-alignment.ll
…
r600.global_atomics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
r600.llvm.is.fpclass.ll
R600: Expand is_fpclass (#135234)
2025-04-12 18:49:12 +02:00
r600.private-memory.ll
…
r600.sub.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
r600.work-item-intrinsics.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
r600cfg.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
ra-inserted-scalar-instructions.mir
…
ran-out-of-registers-error-all-regs-reserved.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ran-out-of-registers-errors.ll
RegAllocFast: Avoid using temporary DiagnosticInfo (#120184)
2024-12-17 16:19:26 +07:00
ran-out-of-sgprs-allocation-failure.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
rcp_iflag.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
rcp-pattern.ll
[AMDGPU] Remove UnsafeFPMath uses (#151079)
2025-07-31 17:36:57 +08:00
read_register.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
read-register-invalid-register.ll
CodeGen: Emit error if getRegisterByName fails (#145194)
2025-06-23 16:33:35 +09:00
read-register-invalid-subtarget.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
read-register-invalid-type-i32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
read-register-invalid-type-i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
read-write-register-illegal-type.ll
DAG: Emit an error if trying to legalize read/write register with illegal types (#145197)
2025-07-26 10:54:59 +09:00
readcyclecounter.ll
[AMDGPU] s_get_shader_cycles_u64 gfx1250 instruction (#152390)
2025-08-06 15:32:28 -07:00
readlane_exec0.mir
[AMDGPU][NPM] Port SILateBranchLowering to NPM (#130063)
2025-03-26 19:28:19 +05:30
README
…
readsteadycounter.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
reassoc-mul-add-1-to-mad.ll
[AMDGPU] Support lowering of cluster related instrinsics (#157978)
2025-09-12 21:11:17 -04:00
reassoc-scalar.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
recursion.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
recursive_global_initializer.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
recursive-resource-usage-mcexpr.ll
[AMDGPU] Flatten recursive register resource info propagation (#142766)
2025-06-12 14:35:28 +01:00
reduce-build-vec-ext-to-ext-build-vec.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
reduce-load-width-alignment.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
reduce-saveexec.mir
…
reduce-store-width-alignment.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
reduction.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
reg-coalescer-sched-crash.ll
AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll test (#131259)
2025-03-14 16:04:55 +07:00
reg-sequence-like-v-pk-mov-b32.mir
AMDGPU: Add baseline test for treating v_pk_mov_b32 like reg_sequence (#125656)
2025-02-13 18:12:09 +07:00
regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
…
regalloc-failure-overlapping-insert-assert.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
regalloc-fast-dont-drop-subreg-index-issue61134.mir
…
regalloc-illegal-eviction-assert.ll
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
regalloc-introduces-copy-sgpr-to-agpr.mir
…
regalloc-undef-copy-fold.mir
AMDGPU: Always use AV spill pseudos on targets with AGPRs (#149099)
2025-07-18 15:31:50 +09:00
regcoal-subrange-join-seg.mir
…
regcoal-subrange-join.mir
…
regcoalesce-64-bit-only-regs.mir
[AMDGPU] Drop high 32 bits of aperture registers (#158725)
2025-09-16 02:11:39 -07:00
regcoalesce-cannot-join-failures.mir
…
regcoalesce-dbg.mir
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
…
regcoalesce-prune.mir
…
regcoalescer-resolve-lane-conflict-by-subranges.mir
…
regcoalescing-remove-partial-redundancy-assert.mir
…
register-coalescer--set-undef-full-reg-use-implicit-def-erase-issue109249.mir
RegisterCoalescer: Set undef on full register uses when coalescing implicit_def (#118321)
2024-12-02 14:43:04 -05:00
register-count-comments.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
register-killed-error-after-alloc-failure0.mir
RegAlloc: Use new approach to handling failed allocations (#128469)
2025-02-26 15:34:47 +07:00
register-killed-error-after-alloc-failure1.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
regpressure_printer.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
reject-agpr-usage-before-gfx908.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
rel32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
release-vgprs-dbg-loc.mir
…
release-vgprs-gfx12-dvgpr.mir
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
release-vgprs-gfx12.mir
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
release-vgprs.mir
…
rem_i128.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
remaining-virtual-register-operands.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
remaining-virtual-register-operands.mir
AMDGPU: Add a mir variant of a regalloc failure test
2025-02-27 20:05:38 +07:00
remat-dead-subreg.mir
…
remat-fp64-constants.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
RegisterCoalescer: Fix assert on remat to copy-to-physreg with subregs (#121734)
2025-01-07 12:22:23 +07:00
remat-smrd.mir
…
remat-sop.mir
AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (#128677)
2025-02-25 18:22:32 +07:00
remat-vop.mir
AMDGPU: Fix not diagnosing unaligned VGPRs for vsrc operands (#155104)
2025-08-25 17:42:58 +09:00
remove-incompatible-extended-image-insts.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
remove-incompatible-functions.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
remove-incompatible-gws.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
remove-incompatible-s-time.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
remove-incompatible-wave32-feature.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
remove-incompatible-wave64-feature.ll
[AMDGPU] Remove wave64 functions (#153690)
2025-08-14 15:54:33 -07:00
remove-no-kernel-id-attribute.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
remove-not-short-exec-branch-on-unconditional-jump.mir
[AMDGPU][SIPreEmitPeephole] Fix mustRetainExeczBranch (#120121)
2024-12-17 11:47:38 +01:00
remove-register-flags.mir
[AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (#130094)
2025-03-20 08:38:04 +01:00
remove-short-exec-branches-gpr-idx-mode.mir
…
remove-short-exec-branches-special-instructions.mir
[AMDGPU][NPM] Port SIPreEmitPeephole to NPM (#130065)
2025-04-08 17:58:48 +05:30
rename-disconnected-bug.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
rename-independent-subregs-mac-operands.mir
[CodeGen][NewPM] Port RenameIndependentSubregs to NPM (#125192)
2025-02-05 17:54:57 +05:30
rename-independent-subregs.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
reorder-stores.ll
…
repeated-divisor.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
replace-store-of-insert-load.ll
…
reqd-work-group-size.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
required-export-priority.ll
[AMDGPU] Fix UB in tests due to mismatched calling conventions (#137957)
2025-05-06 18:31:27 +02:00
required-export-priority.mir
…
reserved-reg-in-clause.mir
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
resource-optimization-remarks.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
resource-usage-crash-unhandled-reg.mir
…
resource-usage-dead-function.ll
…
resource-usage-pal.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ret_jump.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
ret.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
return-with-successors.mir
…
returnaddress.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
rewrite-out-arguments-address-space.ll
…
rewrite-out-arguments.ll
[IR] Convert from nocapture to captures(none) (#123181)
2025-01-29 16:56:47 +01:00
rewrite-partial-reg-uses-dbg.mir
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
2025-02-12 11:21:40 +05:30
rewrite-partial-reg-uses-gen.mir
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
2025-02-12 11:21:40 +05:30
rewrite-partial-reg-uses.mir
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
2025-02-12 11:21:40 +05:30
rewrite-undef-for-phi.ll
AMDGPU: Replace undef phi inputs with poison in tests (#130267)
2025-03-08 07:14:29 +07:00
rewrite-vgpr-mfma-to-agpr-copy-from.mir
[AMDGPU] Add aperture classes to VS_64 (#158823)
2025-09-16 11:15:50 -07:00
rewrite-vgpr-mfma-to-agpr-phi.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
[AMDGPU] Add aperture classes to VS_64 (#158823)
2025-09-16 11:15:50 -07:00
rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
[AMDGPU] Add aperture classes to VS_64 (#158823)
2025-09-16 11:15:50 -07:00
rewrite-vgpr-mfma-to-agpr.gfx90a.ll
AMDGPU: Add tests for every mfma intrinsic v-to-a mapping (#153026)
2025-09-04 11:24:54 +09:00
rewrite-vgpr-mfma-to-agpr.gfx950.ll
AMDGPU: Add tests for every mfma intrinsic v-to-a mapping (#153026)
2025-09-04 11:24:54 +09:00
rewrite-vgpr-mfma-to-agpr.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
rotate-add.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
rotl.i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
rotl.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
rotr.i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
rotr.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
roundeven.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
rsq.f32-safe.ll
[DAGCombiner] Remove UnsafeFPMath usage in visitFSUBForFMACombine etc. (#145637)
2025-06-30 08:41:23 +08:00
rsq.f32.ll
[AMDGPU] Remove UnsafeFPMath uses (#151079)
2025-07-31 17:36:57 +08:00
rsq.f64.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
rv7x0_count3.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
s_add_co_pseudo_lowering.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
s_addk_i32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
s_code_end.ll
…
s_movk_i32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
s_mulk_i32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
s_or_saveexec_xor_combine.mir
…
s-barrier-lowering.ll
[AMDGPU] Upstream the Support for array of named barriers (#154604)
2025-08-20 14:53:03 -07:00
s-barrier.ll
[AMDGPU][SIInsertWaitcnts] Track SCC. Insert KM_CNT waits for SCC writes. (#157843)
2025-09-18 14:41:01 +02:00
s-cluster-barrier.ll
[AMDGPU] Add s-cluster-barrier.ll test. NFC (#160353)
2025-09-23 14:31:04 -07:00
s-getpc-b64-remat.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sad.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
saddo.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
saddsat.ll
[AMDGPU] Recognise bitmask operations as srcmods on select (#152119)
2025-08-07 19:45:09 +01:00
salu-to-valu.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
same-slot-agpr-sgpr.mir
…
sampler-resource-id.ll
…
save-fp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
scalar_to_vector_v2x16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
scalar_to_vector.gfx11plus.ll
[AMDGPU][True16][CodeGen] Fixed two lit tests (#157684)
2025-09-09 11:13:23 -04:00
scalar_to_vector.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
scalar_to_vector.v8i16.ll
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
scalar-branch-missing-and-exec.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
scalar-float-sop1.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
scalar-float-sop2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
scalar-float-sopc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
scalar-store-cache-flush.mir
AMDGPU: Replace undef references with poison in some MIR tests (#131254)
2025-03-14 14:45:49 +07:00
scalarize-insert-subvector.ll
…
scale-offset-flat.ll
[AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns (#143881)
2025-09-18 15:01:07 +02:00
scale-offset-global.ll
[AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns (#143881)
2025-09-18 15:01:07 +02:00
scale-offset-scratch.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
scale-offset-smem.ll
[AMDGPU] Select scale_offset with SMEM instructions (#150078)
2025-07-22 13:26:28 -07:00
scc-clobbered-sgpr-to-vmem-spill.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sched-assert-dead-def-subreg-use-other-subreg.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
sched-assert-onlydbg-value-empty-region.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
sched-barrier-hang-weak-dep.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
sched-barrier-post-RA.mir
…
sched-barrier-pre-RA.mir
[AMDGPU] Add target hook to isGlobalMemoryObject (#112781)
2025-01-11 09:57:57 -08:00
sched-crash-dbg-value.mir
AMDGPU: Replace undef references with poison in some MIR tests (#131254)
2025-03-14 14:45:49 +07:00
sched-group-barrier-pipeline-solver.mir
…
sched-group-barrier-pre-RA.mir
…
sched-handleMoveUp-subreg-def-across-subreg-def.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
sched-image-sample-post-RA.mir
[AMDGPU] Support bottom-up postRA scheduing. (#135295)
2025-06-05 22:07:06 +08:00
sched-no-schedmodel.mir
[ScheduleDAG] Allow disabling the SchedModel / Itineraries during Scheduling (#138057)
2025-05-05 14:07:23 -07:00
sched-prefer-non-mfma.mir
…
sched-setprio.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sched.barrier.inverted.mask.ll
…
schedule-addrspaces.ll
…
schedule-amdgpu-tracker-physreg-crash.ll
Re-apply "[AMDGPU] Fix test failures when expensive checks are enabled (#130644)"
2025-03-14 09:49:20 +01:00
schedule-amdgpu-tracker-physreg.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
schedule-amdgpu-trackers.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
schedule-avoid-spills.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-barrier-fpmode.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
schedule-barrier.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
schedule-fs-loop-nested-if.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-fs-loop-nested.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-fs-loop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-global-loads.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-if-2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-if.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-ilp-liveness-tracking.mir
[AMDGPU] Add MaxMemoryClauseSchedStrategy (#114957)
2024-12-09 10:07:27 +08:00
schedule-ilp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-ilp.mir
…
schedule-kernel-arg-loads.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-physregdeps.mir
…
schedule-regpressure-ilp-metric-spills.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
schedule-regpressure-lds.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-regpressure-limit2.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-regpressure-limit3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-regpressure-limit-clustering.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-regpressure-limit.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-regpressure-misched-max-waves.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
schedule-regpressure.mir
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
schedule-relaxed-occupancy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-vs-if-nested-loop-failure.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
schedule-vs-if-nested-loop.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
schedule-xdl-resource.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
scheduler-handle-move-bundle.mir
…
scheduler-rp-calc-one-successor-two-predecessors-bug.ll
StructurizeCFG: Use poison instead of undef (#130459)
2025-03-10 22:29:15 +07:00
scheduler-subrange-crash.ll
AMDGPU: Switch scheduler-subrange-crash.ll to generated checks (#131316)
2025-03-17 16:07:08 +07:00
scratch-buffer.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
scratch-pointer-sink.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
scratch-simple.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sdag-print-divergence.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sdiv64.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
sdiv.ll
[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDValue with just the frozen node (#150017)
2025-08-05 09:24:09 +01:00
sdivrem24.ll
…
sdivrem64.r600.ll
…
sdwa-commute.ll
…
sdwa-cse.mir
…
sdwa-gfx9.mir
…
sdwa-op64-test.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sdwa-ops.mir
…
sdwa-peephole-cndmask-fail.ll
[AMDGPU] si-peephole-sdwa: Fix cndmask vcc use for wave32 (#139541)
2025-05-14 07:37:01 +02:00
sdwa-peephole-cndmask-sext.ll
[AMDGPU] si-peephole-sdwa: Disable V_CNDMASK_B32 conversion with sext (#140760)
2025-05-26 09:33:09 +02:00
sdwa-peephole-cndmask-wave32.mir
[AMDGPU] si-peephole-sdwa: Fix cndmask vcc use for wave32 (#139541)
2025-05-14 07:37:01 +02:00
sdwa-peephole-cndmask-wave64.mir
[AMDGPU] si-peephole-sdwa: Disable V_CNDMASK_B32 conversion with sext (#140760)
2025-05-26 09:33:09 +02:00
sdwa-peephole-instr-combine-sel-dst.mir
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
sdwa-peephole-instr-combine-sel-src.mir
[AMDGPU] Use different values for SISrcMods::NEG and SISrcMods::SEXT (#147964)
2025-07-11 08:35:19 +02:00
sdwa-peephole-instr-combine-sel.ll
[AMDGPU] Filter candidates of LiveRegOptimizer for profitable cases (#124624)
2025-03-05 18:44:48 -05:00
sdwa-peephole-instr-combine-sel.mir
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
sdwa-peephole-instr-gfx10.mir
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
sdwa-peephole-instr.mir
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
sdwa-peephole.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sdwa-preserve.mir
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
sdwa-scalar-ops.mir
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
sdwa-stack.mir
…
sdwa-vop2-64bit.mir
…
select64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
select-cmp-shared-constant-fp.ll
[AMDGPU] Try to reuse register with the constant from compare in v_cndmask (#148740)
2025-07-16 23:18:44 +02:00
select-cmp-shared-constant-int.ll
[AMDGPU] Try to reuse register with the constant from compare in v_cndmask (#148740)
2025-07-16 23:18:44 +02:00
select-constant-cttz.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
select-constant-xor.ll
…
select-fabs-fneg-extract-legacy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
select-fabs-fneg-extract.f16.ll
[AMDGPU][True16][CodeGen] fix a predicate bug in VGPRImm with f16/bf16 (#144942)
2025-06-23 10:46:59 -04:00
select-fabs-fneg-extract.legal.f16.ll
…
select-fabs-fneg-extract.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
select-fabs-fneg-extract.v2f16.ll
[AMDGPU][True16][CodeGen] fix a predicate bug in VGPRImm with f16/bf16 (#144942)
2025-06-23 10:46:59 -04:00
select-flags-to-fmin-fmax.ll
[AMDGPU] Fix bad removal of s_delay_alu (#145728)
2025-06-27 16:15:10 +02:00
select-i1.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
select-opt.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
select-phi-s16-fp.ll
…
select-undef.ll
[AMDGPU] Add freeze for LowerSELECT (#148796)
2025-07-18 13:29:33 +08:00
select-vectors.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
select.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
select.ll
…
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
…
selectcc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sema-v-unsched-bundle.ll
[AMDGCN] Allow unscheduling of bundled insns
2025-03-18 11:56:51 -05:00
sendmsg-m0-hazard.mir
…
set_kill_i1_for_floation_point_comparison.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
set-dx10.ll
…
set-gpr-idx-peephole.mir
[AMDGPU][NPM] Port SIPreEmitPeephole to NPM (#130065)
2025-04-08 17:58:48 +05:30
set-inactive-wwm-overwrite.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
set-wave-priority.ll
[AMDGPU][NPM] Port AMDGPUSetWavePriority to NPM (#130064)
2025-04-02 16:28:05 +05:30
setcc64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
setcc-equivalent.ll
…
setcc-fneg-constant.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
setcc-limit-load-shrink.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
setcc-multiple-use.ll
…
setcc-opt.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
setcc-sext.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
setcc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
seto.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
setuo.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sext-divergence-driven-isel.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sext-eliminate.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sext-in-reg-failure-r600.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sext-in-reg-vector-shuffle.ll
[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDValue with just the frozen node (#150017)
2025-08-05 09:24:09 +01:00
sext-in-reg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sgpr-control-flow.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sgpr-copy-duplicate-operand.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sgpr-copy-local-cse.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sgpr-copy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sgpr-count-graphics.ll
[AMDGPU] AsmPrinter: Unify arg handling (#151672)
2025-08-08 12:00:37 +02:00
sgpr-phys-copy.mir
[AMDGPU] Drop high 32 bits of aperture registers (#158725)
2025-09-16 02:11:39 -07:00
sgpr-regalloc-flags.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
sgpr-spill-dead-frame-in-dbg-value.mir
…
sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
…
sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
…
sgpr-spill-incorrect-fi-bookkeeping-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sgpr-spill-no-vgprs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sgpr-spill-overlap-wwm-reserve.mir
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
sgpr-spill-partially-undef.mir
AMDGPU: Delete spills of undef values (#119684)
2024-12-17 13:08:38 +07:00
sgpr-spill-to-vmem-scc-clobber-unhandled.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
sgpr-spill-to-vmem-scc-clobber.mir
…
sgpr-spill-update-only-slot-indexes.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sgpr-spill-vmem-large-frame.mir
…
sgpr-spill-wrong-stack-id.mir
AMDGPU: Replace some test i32 undef uses with poison (#131092)
2025-03-13 20:10:17 +07:00
sgpr-spill.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
sgpr-spills-empty-prolog-block.mir
…
sgpr-spills-split-regalloc.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
sgpr-to-vreg1-copy.ll
[AMDGPU] Fix sgpr to vreg_1 copy analysis (#149181)
2025-07-18 14:08:50 +09:00
sgpr-to-vreg1-copy.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
sgprcopies.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shader-addr64-nonuniform.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shared-op-cycle.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
shift-and-i64-ubfe.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
shift-and-i128-ubfe.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shift-i64-opts.ll
…
shift-i128.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shift-select.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shl64_reduce_flags.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
shl64_reduce.ll
AMDGPU: Convert vector 64-bit shl to 32-bit if shift amt >= 32 (#132964)
2025-03-28 23:46:35 +07:00
shl_add_constant.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shl_add_ptr_csub.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shl_add_ptr_global.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
shl_add_ptr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shl_add.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shl_or.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shl-add-to-add-shl.ll
…
shl.ll
[DAG] Always use stack to promote bitcast when the source is vector (#151065)
2025-08-02 15:32:10 -07:00
shl.v2i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
should-not-hoist-set-inactive.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
shrink-add-sub-constant.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
shrink-carry.mir
…
shrink-fma-f64.mir
[AMDGPU] Codegen support for v_fmaak_f64/f_fmamk_f64 (#148734)
2025-07-14 17:57:06 -07:00
shrink-i32-kimm.mir
…
shrink-instructions-flags.mir
…
shrink-instructions-illegal-fold.mir
…
shrink-instructions-implicit-vcclo.mir
…
shrink-insts-scalar-bit-ops.mir
…
shrink-mad-fma-fake16.mir
[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)
2025-02-19 11:37:24 -05:00
shrink-mad-fma-gfx10.mir
[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)
2025-02-19 11:37:24 -05:00
shrink-mad-fma.mir
[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)
2025-02-19 11:37:24 -05:00
shrink-true16.mir
[AMDGPU][True16][MC] VOPC profile fake16 pseudo update (#113175)
2024-11-22 12:12:13 -05:00
shrink-v-cmp-wave32-dead-vcc-lo.mir
…
shrink-vop3-carry-out.mir
…
shufflevector-physreg-copy.ll
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
shufflevector.v2bf16.v2bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2bf16.v3bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2bf16.v4bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2bf16.v8bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f16.v2f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f16.v3f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f16.v4f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f16.v8f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f32.v2f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f32.v3f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f32.v4f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2f32.v8f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i16.v2i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i16.v3i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i16.v4i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i16.v8i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i32.v2i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i32.v3i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i32.v4i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i32.v8i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i64.v2i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i64.v3i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i64.v4i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2i64.v8i64.ll
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
shufflevector.v2p0.v2p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p0.v3p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p0.v4p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p3.v2p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p3.v3p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p3.v4p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v2p3.v8p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3bf16.v2bf16.ll
[SelectionDAG] Fold undemanded operand to UNDEF for VECTOR_SHUFFLE (#145524)
2025-06-25 16:05:54 +02:00
shufflevector.v3bf16.v3bf16.ll
[SelectionDAG] Fold undemanded operand to UNDEF for VECTOR_SHUFFLE (#145524)
2025-06-25 16:05:54 +02:00
shufflevector.v3bf16.v4bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3f16.v2f16.ll
[SelectionDAG] Fold undemanded operand to UNDEF for VECTOR_SHUFFLE (#145524)
2025-06-25 16:05:54 +02:00
shufflevector.v3f16.v3f16.ll
[SelectionDAG] Fold undemanded operand to UNDEF for VECTOR_SHUFFLE (#145524)
2025-06-25 16:05:54 +02:00
shufflevector.v3f16.v4f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3f32.v2f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3f32.v3f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3f32.v4f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i16.v2i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i16.v3i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i16.v4i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i32.v2i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i32.v3i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i32.v4i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i64.v2i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i64.v3i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3i64.v4i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p0.v2p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p0.v3p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p0.v4p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p3.v2p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p3.v3p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v3p3.v4p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4bf16.v2bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4bf16.v3bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4bf16.v4bf16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f16.v2f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f16.v3f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f16.v4f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f32.v2f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f32.v3f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4f32.v4f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i16.v2i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i16.v3i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i16.v4i16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i32.v2i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i32.v3i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i32.v4i32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i64.v2i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i64.v3i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4i64.v4i64.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p0.v2p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p0.v3p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p0.v4p0.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p3.v2p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p3.v3p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
shufflevector.v4p3.v4p3.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
si-annotate-cf-kill.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-annotate-cf-noloop.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-annotate-cf-unreachable.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-annotate-cf.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-annotate-cfg-loop-assert.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-annotate-dbg-info.ll
[StructurizeCFG] Stop setting DebugLocs in flow blocks (#139088)
2025-05-09 14:22:14 -04:00
si-annotate-nested-control-flows.ll
[AMDGPU] Select (xor i1 (divergent trunc:i32 x), -1) -> cmp_neq x, 1 (#133698)
2025-04-11 13:03:01 +02:00
si-annotatecfg-multiple-backedges.ll
…
si-fix-sgpr-copies-copy-to-sgpr.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
si-fix-sgpr-copies.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
si-fold-aligned-agprs.mir
AMDGPU: Stop special casing aligned VGPR targets in operand folding (#155559)
2025-09-02 16:15:25 +00:00
si-fold-aligned-vgprs.mir
AMDGPU: Stop special casing aligned VGPR targets in operand folding (#155559)
2025-09-02 16:15:25 +00:00
si-fold-copy-kills.mir
…
si-fold-kimm.mir
…
si-fold-operands-agpr-copy-reg-sequence.mir
AMDGPU: Avoid using exact class check in reg_sequence AGPR fold (#156135)
2025-09-03 09:05:48 +09:00
si-fold-operands-commute-same-operands-assert.mir
AMDGPU: Do not try to commute instruction with same input register (#127562)
2025-02-27 08:39:03 +07:00
si-fold-operands-requires-ssa.mir
AMDGPU: Add REQUIRES: asserts to machine pass violation test
2025-03-18 07:31:50 +07:00
si-fold-operands-subreg-imm.gfx942.mir
AMDGPU: Fix tracking subreg defs when folding through reg_sequence (#140608)
2025-06-26 07:42:55 +09:00
si-fold-operands-subreg-imm.mir
AMDGPU: Fix tracking subreg defs when folding through reg_sequence (#140608)
2025-06-26 07:42:55 +09:00
si-fold-reg-sequence.mir
[AMDGPU] Fold into uses of splat REG_SEQUENCEs through COPYs. (#145691)
2025-08-04 16:18:33 +01:00
si-fold-scalar-clamp.mir
…
si-i1-copies.mir
…
si-init-whole-wave.mir
[CodeGen][NewPM] Port SIWholeQuadMode to NPM. (#125833)
2025-02-05 18:44:57 +05:30
si-instr-info-correct-implicit-operands.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-instr-info-vopc-exec.mir
[AMDGPU] SIInstrInfo: Fix resultDependsOnExec for VOPC instructions (#134629)
2025-04-22 10:17:35 +02:00
si-lower-control-flow-kill.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-lower-control-flow-unreachable-block.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-lower-control-flow.mir
…
si-lower-i1-copies-order-of-phi-incomings.mir
…
si-lower-i1-copies.mir
…
si-lower-sgpr-spills-vgpr-lanes-usage.mir
…
si-lower-sgpr-spills.mir
…
si-lower-wwm-copies.mir
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)
2025-01-22 14:54:01 +05:30
si-opt-vgpr-liverange-bug-deadlanes.mir
[AMDGPU][NewPM] Port SIOptimizeVGPRLiveRange pass to NPM. (#117686)
2024-11-29 09:11:24 +05:30
si-optimize-vgpr-live-range-dbg-instr.ll
[AMDGPU] Select (xor i1 (divergent trunc:i32 x), -1) -> cmp_neq x, 1 (#133698)
2025-04-11 13:03:01 +02:00
si-optimize-vgpr-live-range-dbg-instr.mir
[AMDGPU][NewPM] Port SIOptimizeVGPRLiveRange pass to NPM. (#117686)
2024-11-29 09:11:24 +05:30
si-pre-allocate-wwm-regs.mir
…
si-pre-allocate-wwwmregs-dbg-noreg.mir
[AMDGPU] Fixed llvm-debuginfo-analyzer for AMDGPU. (#145125)
2025-08-12 22:04:52 +00:00
si-scheduler-exports.ll
…
si-scheduler.ll
…
si-sgpr-spill.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-spill-cf.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-triv-disjoint-mem-access.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-unify-exit-multiple-unreachables.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-unify-exit-return-unreachable.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
si-vector-hang.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sibling-call.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
sign_extend.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
simple-indirect-call-2.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
simple-indirect-call.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
simplify-libcall-nobuiltin-def.ll
…
simplify-libcalls2.ll
AMDGPU: Replace some test i32 undef uses with poison (#131092)
2025-03-13 20:10:17 +07:00
simplify-libcalls.ll
AMDGPU: Replace tests using undef in shufflevector with poison (#130899)
2025-03-12 20:45:02 +07:00
simplifydemandedbits-recursion.ll
AMDGPU: Switch simplifydemandedbits-recursion.ll to generated checks (#131317)
2025-03-17 16:10:01 +07:00
sink-addr-memory-intrinsics.ll
[CodeGenPrepare] Consider target memory intrinics as memory use (#159638)
2025-09-19 14:18:21 -07:00
sink-after-control-flow-postra.mir
[CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM (#129690)
2025-07-10 13:10:46 +05:30
sink-after-control-flow.mir
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sink-image-sample.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sint_to_fp.f64.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
sint_to_fp.i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sint_to_fp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sitofp.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
skip-branch-taildup-ret.mir
…
skip-branch-trap.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
skip-fold-regsequence.mir
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skip-if-dead.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
skip-promote-alloca-vector-users.ll
AMDGPU: Replace ptr undef in tests with poison (#131050)
2025-03-13 13:34:52 +07:00
smed3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
smem-no-clause-coalesced.mir
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
smem-war-hazard.mir
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smfmac_no_agprs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sminmax.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sminmax.v2i16.ll
[AMDGPU] Extend SRA i64 simplification for shift amts in range [33:62] (#138913)
2025-05-30 16:21:38 +02:00
smrd_vmem_war.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
smrd-fold-offset.mir
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smrd-gfx10.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
smrd-vccz-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
smrd.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
snippet-copy-bundle-regression.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
soft-clause-dbg-value.mir
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
soft-clause-exceeds-register-budget.ll
AMDGPU: Migrate more tests away from undef (#131314)
2025-03-17 15:57:47 +07:00
sopk-compares.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sopk-no-literal.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
speculative-execution-freecasts.ll
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spill192.mir
…
spill224.mir
…
spill288.mir
…
spill320.mir
…
spill352.mir
…
spill384.mir
…
spill_kill_v16.mir
[AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (#128060)
2025-02-26 16:17:20 -05:00
spill_more_than_wavesize_csr_sgprs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
spill-agpr-partially-undef.mir
[AMDGPU] Remove implicit definition of register group when restoring the last sub-register after a spill (#133986)
2025-05-05 20:17:36 +02:00
spill-agpr.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
spill-agpr.mir
AMDGPU: Always use AV spill pseudos on targets with AGPRs (#149099)
2025-07-18 15:31:50 +09:00
spill-alloc-sgpr-init-bug.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
spill-before-exec.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
spill-cfg-position.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
spill-csr-frame-ptr-reg-copy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
spill-empty-live-interval.mir
…
spill-m0.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
spill-offset-calculation.ll
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spill-partial-csr-sgpr-live-ins.mir
[AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills (#129848)
2025-03-18 10:51:07 +05:30
spill-reg-tuple-super-reg-use.mir
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spill-regpressure-less.mir
AMDGPU: Replace amdgpu-no-agpr with amdgpu-agpr-alloc (#129893)
2025-03-06 09:17:51 +07:00
spill-scavenge-offset.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
spill-sgpr-csr-live-ins.mir
…
spill-sgpr-stack-no-sgpr.ll
…
spill-sgpr-to-virtual-vgpr.mir
[AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills (#129848)
2025-03-18 10:51:07 +05:30
spill-sgpr-used-for-exec-copy.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
spill-special-sgpr.mir
…
spill-to-agpr-partial.mir
…
spill-vector-superclass.ll
[AMDGPU] Add aperture classes to VS_64 (#158823)
2025-09-16 11:15:50 -07:00
spill-vgpr-block.ll
Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)
2025-04-25 11:29:27 +02:00
spill-vgpr-to-agpr-update-regscavenger.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
spill-vgpr-to-agpr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
spill-vgpr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
spill-wait.mir
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spill-wide-sgpr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
spill-writelane-vgprs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
spillv16.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
spillv16.mir
[AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (#128060)
2025-02-26 16:17:20 -05:00
split-arg-dbg-value.ll
AMDGPU: Replace tests using undef in shufflevector with poison (#130899)
2025-03-12 20:45:02 +07:00
split-liverange-overlapping-copies.mir
…
split-mbb-lis-subrange.mir
…
split-scalar-i64-add.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
split-smrd.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
split-vector-memoperand-offsets.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
splitkit-copy-bundle.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
splitkit-copy-live-lanes.mir
…
splitkit-do-not-undo-subclass-split-with-remat.mir
AMDGPU: Add pseudoinstruction for agpr or vgpr constants (#130042)
2025-03-07 09:18:22 +07:00
splitkit-getsubrangeformask.ll
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
splitkit-nolivesubranges.mir
…
splitkit.mir
…
sra.ll
[DAG] Always use stack to promote bitcast when the source is vector (#151065)
2025-08-02 15:32:10 -07:00
sram-ecc-default.ll
[AMDGPU] gfx1250 sram-ecc feature codegen tests. NFC. (#155293)
2025-08-25 14:32:29 -07:00
sramecc-subtarget-feature-any.ll
[AMDGPU] gfx1250 sram-ecc feature codegen tests. NFC. (#155293)
2025-08-25 14:32:29 -07:00
sramecc-subtarget-feature-disabled.ll
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sramecc-subtarget-feature-enabled.ll
[AMDGPU] gfx1250 sram-ecc feature codegen tests. NFC. (#155293)
2025-08-25 14:32:29 -07:00
sreg-xnull-regclass-bitwidth.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
srem64.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
srem-seteq-illegal-types.ll
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srem.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
srl64_reduce_flags.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
srl64_reduce.ll
[AMDGPU] Convert more 64-bit lshr to 32-bit if shift amt>=32 (#138204)
2025-06-13 17:03:06 +09:00
srl.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
sroa-before-unroll.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
SRSRC-GIT-clobber-check.mir
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ssubo.ll
[AMDGPU] Regenerate add/sub overflow tests
2025-07-28 12:51:21 +01:00
ssubsat.ll
[AMDGPU] Recognise bitmask operations as srcmods on select (#152119)
2025-08-07 19:45:09 +01:00
stack-passed-subdword-arg-crash-issue157997.ll
AMDGPU: Fix returning wrong type for stack passed sub-dword arguments (#158002)
2025-09-12 10:50:03 +09:00
stack-pointer-offset-relative-frameindex.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
stack-realign-kernel.ll
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
stack-realign.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
stack-size-overflow.ll
…
stack-slot-color-sgpr-vgpr-spills.mir
…
stacksave_stackrestore.invalid.ll
GlobalISel: Replace use of report_fatal_error (#145866)
2025-06-27 21:16:23 +09:00
stacksave_stackrestore.ll
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
2025-04-24 17:13:03 +02:00
stale-livevar-in-twoaddr-pass.mir
…
stop-tail-duplicate-cfg-intrinsic.mir
…
store_typed.ll
…
store-barrier.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
store-clobbers-load.ll
[AMDGPU][LIT][NFC] Adding -mtriple for AMDGPUAnnotateUniformValues Pass tests (#156437)
2025-09-03 15:32:28 +05:30
store-global.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
store-hi16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
store-local.96.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
store-local.128.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
store-local.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
store-private.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
store-to-constant.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
store-v3i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
store-vector-ptrs.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
store-weird-sizes.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
stress-calls.ll
…
strict_fadd.f16.ll
[AMDGPU][True16][CodeGen] srl pattern for true16 mode (#132987)
2025-03-26 18:38:20 -04:00
strict_fadd.f32.ll
…
strict_fadd.f64.ll
…
strict_fma.f16.ll
[AMDGPU][True16][CodeGen] srl pattern for true16 mode (#132987)
2025-03-26 18:38:20 -04:00
strict_fma.f32.ll
…
strict_fma.f64.ll
…
strict_fmul.f16.ll
[AMDGPU][True16][CodeGen] srl pattern for true16 mode (#132987)
2025-03-26 18:38:20 -04:00
strict_fmul.f32.ll
…
strict_fmul.f64.ll
…
strict_fpext.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
strict_fptrunc.ll
[AMDGPU][True16][CodeGen] build_vector pattern in true16 (#118904)
2025-02-21 14:02:12 -05:00
strict_fsub.f16.ll
[AMDGPU][True16][GlobalISel] Fix v2*16 build_vector patterns (#151496)
2025-08-04 13:06:06 +02:00
strict_fsub.f32.ll
…
strict_fsub.f64.ll
…
strict_ldexp.f16.ll
[AMDGPU][True16][GlobalISel] Fix v2*16 build_vector patterns (#151496)
2025-08-04 13:06:06 +02:00
strict_ldexp.f32.ll
…
strict_ldexp.f64.ll
…
strictfp_f16_abi_promote.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
structurize1.ll
…
structurize-hoist.ll
[StructurizeCFG] nested-if zerocost hoist bugfix (#155408)
2025-08-28 09:04:14 -05:00
structurize.ll
…
sub64-low-32-bits-known-zero.ll
Reapply "[AMDGPU] Insert readfirstlane in the function returns in sgpr." (#136678)
2025-04-22 17:48:55 +05:30
sub_i1.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sub_u64.ll
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
2025-09-24 12:35:50 +01:00
sub-zext-cc-zext-cc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sub.i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sub.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
sub.v2i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
subreg_interference.mir
…
subreg-coalescer-crash.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
subreg-coalescer-undef-use.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
subreg-eliminate-dead.ll
AMDGPU: Switch test to generated checks (#131315)
2025-03-17 16:03:55 +07:00
subreg-intervals.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
subreg-split-live-in-error.mir
…
subreg-undef-def-with-other-subreg-defs.mir
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
2025-09-16 17:45:29 +00:00
subvector-test.mir
…
swdev282079.ll
[AMDGPU] Move InferAddressSpacesPass to middle end optimization pipeline (#138604)
2025-05-29 17:20:56 -04:00
swdev282079.mir
…
swdev373493.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
swdev380865.ll
LICM: Avoid looking at use list of constant data (#134690)
2025-04-13 17:06:38 +02:00
swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
AMDGPU: Always use AV spill pseudos on targets with AGPRs (#149099)
2025-07-18 15:31:50 +09:00
swdev503538-move-to-valu-stack-srd-physreg.ll
[NFC][FIX] Add -verify-machineinstrs=0 explicitly to some test files
2025-07-23 19:12:46 -04:00
swdev504645-global-fold.ll
[AMDGPU] Handle MachineOperandType global address in SIFoldOperands. (#135424)
2025-05-05 18:12:35 +02:00
switch-default-block-unreachable.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
switch-unreachable.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
swizzle-export.ll
[AMDGPU] swizzle-export.ll - regenerate test checks
2025-07-08 10:47:38 +01:00
swizzle.bit.extract.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
syncscopes.ll
…
tail-call-amdgpu-gfx.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
tail-call-cgp.ll
…
tail-call-inreg-arguments.convergencetokens.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
tail-call-inreg-arguments.error.ll
[NFC][FIX] Add -verify-machineinstrs=0 explicitly to some test files
2025-07-23 19:12:46 -04:00
tail-call-inreg-arguments.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
tail-call-uniform-target-in-vgprs-issue110930.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
tail-dup-bundle.mir
…
tail-duplication-convergent.ll
…
target-cpu.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
target-mem-intrinsic-metadata.ll
…
tex-clause-antidep.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
texture-input-merge.ll
AMDGPU: Replace insertelement poison with insertelement undef (#130896)
2025-03-12 20:33:33 +07:00
tgsplit.ll
…
threeaddr-wmma.mir
…
tid-kd-xnack-any.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
tid-kd-xnack-off.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
tid-kd-xnack-on.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
tid-mul-func-xnack-all-any.ll
…
tid-mul-func-xnack-all-not-supported.ll
…
tid-mul-func-xnack-all-off.ll
…
tid-mul-func-xnack-all-on.ll
…
tid-mul-func-xnack-any-off-1.ll
…
tid-mul-func-xnack-any-off-2.ll
…
tid-mul-func-xnack-any-on-1.ll
…
tid-mul-func-xnack-any-on-2.ll
…
tid-mul-func-xnack-invalid-any-off-on.ll
…
tid-one-func-xnack-any.ll
…
tid-one-func-xnack-not-supported.ll
…
tid-one-func-xnack-off.ll
…
tid-one-func-xnack-on.ll
…
tied-op-for-wwm-scratch-reg-spill-restore.mir
…
token-factor-inline-limit-test.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
track-spilled-vgpr-liveness.mir
…
trans-coexecution-hazard.mir
AMDGPU: Handle the co-execution hazards for TRANS for gfx1250 (#149024)
2025-07-16 10:58:54 -07:00
trans-forwarding-hazards.mir
…
transform-block-with-return-to-epilog.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
trap-abis.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
trap.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
triton_regression_no_waterfall.ll
Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#135243)
2025-04-10 22:18:21 +02:00
triton_regression_no_waterfall.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
triv-disjoint-mem-access-neg-offset.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
true16-fold.mir
[AMDGPU][True16][CodeGen] fold clamp update for true16 (#128919)
2025-04-02 17:10:53 -04:00
true16-ra-pre-gfx11-regression-test.mir
…
true16-saveexec.mir
[AMDGPU][True16][CodeGen] True16 Add OpSel when optimizing exec mask (#128928)
2025-02-28 09:41:05 -05:00
trunc-bitcast-vector.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
trunc-cmp-constant.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
trunc-combine.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
trunc-store-f64-to-f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
trunc-store-i1.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
trunc-store-i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
trunc-store-vec-i16-to-i8.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
trunc-store.ll
…
trunc-vector-store-assertion-failure.ll
…
trunc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
truncate-lshr-cast-build-vector-combine.ll
AMDGPU: Generalize truncate of shift of cast build_vector combine (#125617)
2025-02-04 11:46:30 +07:00
tti-unroll-prefs.ll
…
tuple-allocation-failure.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
twoaddr-constrain.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
twoaddr-fma-f64.mir
[AMDGPU] Codegen support for v_fmaak_f64/f_fmamk_f64 (#148734)
2025-07-14 17:57:06 -07:00
twoaddr-fma.mir
…
twoaddr-mad.mir
…
twoaddr-regsequence.mir
…
twoaddr-wmma.mir
…
uaddo.ll
[AMDGPU] Regenerate add/sub overflow tests
2025-07-28 12:51:21 +01:00
uaddsat.ll
[LLVM][SelectionDAG] Align poison/undef binop folds with IR. (#149334)
2025-07-30 11:20:30 +01:00
udiv64.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
udiv.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
udivrem24.ll
[AMDGPU] udivrem24.ll - regenerate test checks
2025-08-01 12:27:11 +01:00
udivrem64.r600.ll
…
udivrem.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
uint_to_fp.f64.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
uint_to_fp.i64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
uint_to_fp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
uitofp.f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
umed3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
unaligned-buffer.ll
[AMDGPU] Fix edge case of buffer OOB handling (#115479)
2025-03-07 08:56:44 +01:00
unaligned-load-store.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
unallocatable-bundle-regression.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
undef-build-vector.ll
…
undef-copy-propagation.mir
…
undef-handling-crash-in-ra.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
undef-subreg-use-after-coalesce.mir
…
undefined-physreg-sgpr-spill.mir
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
undefined-subreg-liverange.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
unexpected-reg-unit-state.mir
…
unfold-masked-merge-scalar-variablemask.ll
Reland "[SelectionDAG] Make (a & x) | (~a & y) -> (a & (x ^ y)) ^ y available for all targets" (#143651)
2025-06-11 15:56:37 +08:00
unhandled-loop-condition-assertion.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
uniform_branch_with_floating_point_cond.ll
[AMDGPU] Move InferAddressSpacesPass to middle end optimization pipeline (#138604)
2025-05-29 17:20:56 -04:00
uniform-branch-intrinsic-cond.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
uniform-cfg.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
uniform-crash.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
uniform-load-from-tid.ll
[AMDGPU] Mark workitem IDs uniform in more cases (#152581)
2025-08-29 01:21:04 -05:00
uniform-loop-inside-nonuniform.ll
…
uniform-phi-with-undef.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
uniform-select.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
uniform-vgpr-to-sgpr-return.ll
[AMDGPU][True16][CodeGen] update more GFX11Plus codegen test with true16 mode (#138600)
2025-05-12 12:19:46 -04:00
uniform-work-group-attribute-missing.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
uniform-work-group-multistep.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
uniform-work-group-nested-function-calls.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
uniform-work-group-prevent-attribute-propagation.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
uniform-work-group-propagate-attribute.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
uniform-work-group-recursion-test.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
uniform-work-group-test.ll
[AMDGPU][Attributor] Add AAAMDGPUClusterDims (#158076)
2025-09-15 15:04:33 -04:00
unigine-liveness-crash.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
unknown-processor.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
unnamed-function-resource-info.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
unpack-half.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
unpack-non-coissue-insts-post-ra-scheduler.mir
[AMDGPU]: Unpack packed instructions overlapped by MFMAs post-RA scheduling (#157968)
2025-09-19 09:41:02 -07:00
unroll.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
unspill-vgpr-after-rewrite-vgpr-mfma.ll
Greedy: Take copy hints involving subregisters (#159570)
2025-09-19 09:37:36 +09:00
unstructured-cfg-def-use-issue.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
unsupported-atomics.ll
AtomicExpand: Stop using report_fatal_error (#147300)
2025-07-09 15:28:10 +09:00
unsupported-calling-conv-call.ll
AMDGPU: Use reportFatalUsageError for unhandled calling conventions (#145261)
2025-06-23 15:30:13 +09:00
unsupported-calling-conv-func.ll
AMDGPU: Use reportFatalUsageError for unhandled calling conventions (#145261)
2025-06-23 15:30:13 +09:00
unsupported-calls.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
unsupported-cc.ll
…
unsupported-code-object-version.ll
AMDGPU: Use reportFatalUsageError for unsupported code object version (#145133)
2025-06-21 13:01:18 +09:00
unsupported-cs-chain.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
unsupported-image-a16.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
unsupported-image-g16.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
unsupported-image-sample.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
update-lds-alignment.ll
…
update-phi.ll
…
urem64.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
urem-seteq-illegal-types.ll
…
urem.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
use_restore_frame_reg.mir
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
use-after-free-after-cleanup-failed-vreg.ll
[RegAlloc] Fix use-after-free in RegAllocBase::cleanupFailedVReg (#151435)
2025-08-01 00:07:57 -04:00
use-sgpr-multiple-times.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
usubo.ll
[AMDGPU] Regenerate add/sub overflow tests
2025-07-28 12:51:21 +01:00
usubsat.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
v1i64-kernel-arg.ll
…
v1024.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
v_add_u64_pseudo_sdwa.ll
[AMDGPU] Skip debug uses in SIPeepholeSDWA (#160092)
2025-09-22 14:40:00 +01:00
v_ashr_pk.ll
[AMDGPU] Add V_ASHR_PK_I8_I32 and V_ASHR_PK_U8_I32 on gfx1250 (#151389)
2025-07-30 16:30:47 -07:00
v_cmp_gfx11.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
v_cndmask.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
v_cvt_pk_u8_f32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
v_mac_f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
v_mac.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
v_madak_f16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
v_mov_b64_expand_and_shrink.mir
…
v_mov_b64_expansion.mir
[AMDGPU] Use v_mov_b64 in codegen on gfx1250 (#148272)
2025-07-11 22:16:50 -07:00
v_pack.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
v_sat_pk_u8_i16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
v_sub_u64_pseudo_sdwa.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
v_swap_b16.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
v_swap_b32.mir
[AMDGPU] Skip debug instructions in SIShrinkInstructions::matchSwap (#160123)
2025-09-23 09:36:09 +01:00
valu-i1.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
valu-mask-write-hazard-true16.mir
[AMDGPU][True16][CodeGen] add v_cndmask_t16 to hazardmask (#128912)
2025-03-14 12:31:57 -04:00
valu-mask-write-hazard.mir
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
valu-read-sgpr-hazard-attrs.mir
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
valu-read-sgpr-hazard.mir
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
vccz-corrupt-bug-workaround.mir
[AMDGPU][NPM] Port SIInsertWaitcnts to NPM (#130061)
2025-03-24 21:36:45 +05:30
vcmp-saveexec-to-vcmpx-set-kill.mir
…
vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
…
vcmp-saveexec-to-vcmpx.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vcmp-saveexec-to-vcmpx.mir
…
vcmpx-exec-war-hazard.mir
…
vcmpx-permlane16var-hazard.mir
…
vcmpx-permlane-hazard-sdwa.mir
…
vcmpx-permlane-hazard.mir
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
vector_range_metadata.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
vector_rebroadcast.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
vector_shuffle.packed.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
vector-alloca-addrspacecast.ll
[InstCombine] Strip leading zero indices from GEP (#155415)
2025-09-01 09:58:11 +02:00
vector-alloca-atomic.ll
…
vector-alloca-bitcast.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vector-alloca-limits.ll
[AMDGPU] Remove explicit datalayout from tests where not needed
2025-04-30 10:58:17 -07:00
vector-alloca.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vector-extract-insert.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vector-legalizer-divergence.ll
AMDGPU: Use generated checks in unchecked test (#131275)
2025-03-14 18:18:01 +07:00
vector-reduce-add.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
vector-reduce-and.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
vector-reduce-fadd.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
vector-reduce-fmax.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
vector-reduce-fmaximum.ll
[AMDGPU][True16][CodeGen] fix a predicate bug in VGPRImm with f16/bf16 (#144942)
2025-06-23 10:46:59 -04:00
vector-reduce-fmin.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
vector-reduce-fminimum.ll
[AMDGPU][True16][CodeGen] fix a predicate bug in VGPRImm with f16/bf16 (#144942)
2025-06-23 10:46:59 -04:00
vector-reduce-fmul.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
vector-reduce-mul.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
vector-reduce-or.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
vector-reduce-smax.ll
[DAG] Remove Depth=1 hack from isGuaranteedNotToBeUndefOrPoison checks (#152127)
2025-08-05 13:35:04 +01:00
vector-reduce-smin.ll
[DAG] Remove Depth=1 hack from isGuaranteedNotToBeUndefOrPoison checks (#152127)
2025-08-05 13:35:04 +01:00
vector-reduce-umax.ll
[DAG] Remove Depth=1 hack from isGuaranteedNotToBeUndefOrPoison checks (#152127)
2025-08-05 13:35:04 +01:00
vector-reduce-umin.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
vector-reduce-xor.ll
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
2025-04-23 13:06:52 -04:00
vector-spill-restore-to-other-vector-type.mir
…
vectorize-buffer-fat-pointer.ll
[AMDGPU] Fix edge case of buffer OOB handling (#115479)
2025-03-07 08:56:44 +01:00
vectorize-global-local.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vectorize-loads.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vectorize-unroll-metadata.ll
…
verifier-sdwa-cvt.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-constant-bus-violations.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-ds-gws-align.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-duplicate-literal.mir
…
verify-gfx12-gds.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-gfx90a-aligned-vgprs.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-image-vaddr-align.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-image.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-scalar-store.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-sop.mir
…
verify-vimage-vsample.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-vopd-gfx12.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-vopd.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
vertex-fetch-encoding.ll
…
vgpr_constant64_to_sgpr.mir
…
vgpr_constant_to_sgpr.ll
[AMDGPU] Fix UB in tests due to mismatched calling conventions (#137957)
2025-05-06 18:31:27 +02:00
vgpr-agpr-limit-gfx90a.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-blocks-funcinfo.mir
Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)
2025-04-25 11:29:27 +02:00
vgpr-count-compute.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-count-graphics-chain.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-count-graphics.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-descriptor-waterfall-loop-idom-update.ll
AMDGPU: Replace some test i32 undef uses with poison (#131092)
2025-03-13 20:10:17 +07:00
vgpr-large-tuple-alloc-error.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
vgpr-limit-gfx1250.ll
[AMDGPU] Constrain inline asm vgprs to low 256 (#157531)
2025-09-08 16:15:34 -07:00
vgpr-liverange-ir.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vgpr-liverange.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vgpr-lowering-gfx1250-t16.mir
[AMDGPU] Fix high vgpr printing with true16 (#160209)
2025-09-23 09:51:21 -07:00
vgpr-lowering-gfx1250.mir
[AMDGPU] Print high vgpr operand comments from objdump (#156966)
2025-09-04 16:56:49 -07:00
vgpr-mark-last-scratch-load.ll
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
vgpr-mark-last-scratch-load.mir
[AMDGPU][NPM] Port AMDGPUMarkLastScratchLoad to NPM (#131738)
2025-03-19 09:27:05 +05:30
vgpr-remat-v_pk_mov_b32.mir
[AMDGPU] Add isAsCheapAsAMove for v_pk_mov_b32 (#127632)
2025-02-19 00:51:57 -05:00
vgpr-remat.mir
AMDGPU: Add pseudoinstruction for 64-bit agpr or vgpr constants (#154499)
2025-08-20 22:54:37 +09:00
vgpr-spill-dead-frame-in-dbg-value.mir
…
vgpr-spill-emergency-stack-slot-compute.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vgpr-spill-emergency-stack-slot.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
…
vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
…
vgpr-spill-placement-issue61083.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
vgpr-spill-scc-clobber.mir
[AMDGPU] Remove implicit definition of register group when restoring the last sub-register after a spill (#133986)
2025-05-05 20:17:36 +02:00
vgpr-spill.mir
AMDGPU: Delete spills of undef values (#119684)
2024-12-17 13:08:38 +07:00
vgpr-tuple-allocation.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vi-removed-intrinsics.ll
…
virtregrewrite-undef-identity-copy.mir
…
visit-physreg-vgpr-imm-folding-bug.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
vmem-to-salu-hazard.mir
…
vmem-vcc-hazard.mir
…
vni8-across-blocks.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
vni8-live-reg-opt.ll
[AMDGPU] Filter candidates of LiveRegOptimizer for profitable cases (#124624)
2025-03-05 18:44:48 -05:00
vop-shrink-frame-index.mir
…
vop-shrink-non-ssa.mir
…
vop-shrink.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vopc_dpp-true16.mir
[AMDGPU][True16][CodeGen] Skip combineDpp with t16 instructions (#128918)
2025-03-31 10:18:25 -04:00
vopc_dpp.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vopc_dpp.mir
[AMDGPU][True16][CodeGen] clean up a few codegen test for true16 mode (#138542)
2025-05-05 13:17:31 -04:00
vopd-combine-gfx1250.mir
[AMDGPU] Prevent VOPD combining of VGPRs with different MSBs (#157168)
2025-09-05 13:34:53 -07:00
vopd-combine.mir
MachineScheduler: Reset next cluster candidate for each node (#139513)
2025-05-28 14:53:46 +08:00
vopd-src2acc-delay.mir
…
vselect64.ll
…
vselect.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait-before-stores-with-scope_sys.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
wait-before-stores-with-scope_sys.mir
[AMDGPU] gfx1250 waitcnt related codegen tests update. NFC (#155317)
2025-08-25 15:23:59 -07:00
wait-xcnt.mir
[AMDGPU] Tests for unnecessary S_WAIT_XCNT insertion (#145688)
2025-07-23 13:24:03 +01:00
wait.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
waitcnt-agpr.mir
…
waitcnt-back-edge-loop.mir
…
waitcnt-bvh.mir
…
waitcnt-debug-non-first-terminators.mir
…
waitcnt-debug.mir
…
waitcnt-flat.ll
AMDGPU: Replace ptr addrspace(3) undef in tests with poison (#131049)
2025-03-13 13:28:55 +07:00
waitcnt-gfx1250.mir
[AMDGPU] High VGPR waitcnt generation tests. NFC. (#157533)
2025-09-08 16:13:27 -07:00
waitcnt-global-inv-wb.mir
[AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (#135340)
2025-04-22 14:53:55 +02:00
waitcnt-kmcnt-scc-different-block.mir
[AMDGPU][SIInsertWaitcnts] Track SCC. Insert KM_CNT waits for SCC writes. (#157843)
2025-09-18 14:41:01 +02:00
waitcnt-loop-irreducible.mir
…
waitcnt-loop-single-basic-block.mir
…
waitcnt-looptest.ll
…
waitcnt-meta-instructions.mir
[AMDGPU] Remove Dwarf encodings for subregisters (#117891)
2025-01-06 14:51:16 -05:00
waitcnt-multiple-funcs.mir
…
waitcnt-no-redundant.mir
…
waitcnt-overflow.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
waitcnt-permute.mir
…
waitcnt-preexisting-vscnt.mir
[AMDGPU] Reenable BackOffBarrier on GFX11/12 (#155370)
2025-09-02 09:37:43 +02:00
waitcnt-preexisting.mir
…
waitcnt-sample-out-order.mir
[AMDGPU] Treat image_msaa_load as a sampler operation (#141726)
2025-05-28 19:56:05 +09:00
waitcnt-sample-waw.mir
[AMDGPU] Treat image_msaa_load as a sampler operation (#141726)
2025-05-28 19:56:05 +09:00
waitcnt-skip-meta.mir
…
waitcnt-trailing.mir
[AMDGPU][SIInsertWaitCnts] skip meta instructions early (#145720)
2025-07-01 22:02:48 +05:30
waitcnt-unscoped.ll
[AMDGPU] Remove scope check in SIInsertWaitcnts::generateWaitcntInstBefore (#157821)
2025-09-12 14:51:36 -04:00
waitcnt-vinterp.mir
…
waitcnt-vmcnt-loop.mir
…
waitcnt-vmem-waw.mir
…
waitcnt-vscnt.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
waitcnt-vscnt.mir
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
waitcnt.mir
AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)
2025-03-14 09:47:54 +07:00
waterfall_kills_scc.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wave32.ll
[AMDGPU] Implement IR expansion for frem instruction (#130988)
2025-09-03 16:27:15 +02:00
wave_dispatch_regs.ll
[AMDGPU] AsmPrinter: Unify arg handling (#151672)
2025-08-08 12:00:37 +02:00
while-break.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
whole-wave-functions-pei.mir
[AMDGPU] Tail call support for whole wave functions (#145860)
2025-09-04 10:34:43 +02:00
whole-wave-functions.ll
[AMDGPU] Add test to whole-wave-functions.ll. NFC (#160361)
2025-09-23 14:31:34 -07:00
whole-wave-register-copy.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
whole-wave-register-spill.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
widen_extending_scalar_loads.ll
…
widen-smrd-loads.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
widen-vselect-and-mask.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma_modifiers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma_multiple_32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma_multiple_64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-coececution-valu-hazards.mir
[AMDGPU] Hazard handling for gfx1250 wmma instructions (#149865)
2025-07-21 13:24:10 -07:00
wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w32-imm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w32-iu-modifiers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w32-swmmac-index_key.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w32.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w64-imm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w64-iu-modifiers.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w64-swmmac-index_key.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-gfx12-w64.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wmma-hazards-gfx12-w32.mir
…
wmma-hazards-gfx12-w64.mir
…
wmma-hazards-gfx1250-w32.mir
[AMDGPU] gfx1250 v_wmma_scale[16]_f32_16x16x128_f8f6f4 codegen (#152036)
2025-08-04 19:16:34 -07:00
wmma-hazards.mir
…
workgroup-id-in-arch-sgprs.ll
[AMDGPU][NFC] Add back -new-reg-bank-select flag. (#159181)
2025-09-17 11:29:16 +02:00
workitem-intrinsic-opts.ll
[DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences (#146054)
2025-07-30 10:27:19 +02:00
wqm-gfx11.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wqm-terminators.mir
[CodeGen][NewPM] Port SIWholeQuadMode to NPM. (#125833)
2025-02-05 18:44:57 +05:30
wqm.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wqm.mir
[AMDGPU] Generate some WQM/WWM tests (NFC) (#152635)
2025-08-08 14:10:13 +09:00
write_register.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
write-register-invalid-register.ll
CodeGen: Emit error if getRegisterByName fails (#145194)
2025-06-23 16:33:35 +09:00
write-register-vgpr-into-sgpr.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
wrong-transalu-pos-fix.ll
…
wwm-reg-shift-down-gfx11plus.mir
[AMDGPU][True16][CodeGen] update wwm reg sorting check condition (#135053)
2025-04-27 14:30:34 -04:00
wwm-regalloc-error.ll
AMDGPU: Avoid contraction in wwm allocation failure message (#150888)
2025-07-28 17:11:28 +09:00
wwm-reserved-spill.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
wwm-reserved.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
wwm-spill-superclass-pseudo.mir
…
xfail.r600.bitcast.ll
…
xnack-subtarget-feature-any.ll
…
xnack-subtarget-feature-disabled.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
xnack-subtarget-feature-enabled.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
xnor.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
xor3-i1-const.ll
[InstCombine] Optimize redundant floating point comparisons in or/and inst's (#158097)
2025-09-16 20:52:11 +05:30
xor3.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
xor_add.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
xor-r600.ll
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
2025-03-13 08:25:02 +07:00
xor.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
zero_extend.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
zext-divergence-driven-isel.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
zext-i64-bit-operand.ll
[RFC][NFC][AMDGPU] Remove -verify-machineinstrs from llvm/test/CodeGen/AMDGPU/*.ll (#150024)
2025-07-23 13:42:46 -04:00
zext-lid.ll
…

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.