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llvm-project/llvm/test/CodeGen/AMDGPU
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Ryan Mitchell 13b20e7aea
[AMDGPU][SILoadStoreOptimizer] Fix lds address operand offset (#176816) 
The offset operand in GLOBAL_LOAD_ASYNC_TO_LDS_B128, for instance, is
added to both the lds and global address, but SILoadStoreOptimizer is
currently unaware of that. This PR inserts an add to counteract the
offset meant for the global address. This one add is better than not
doing the optimization at all, and having to insert 2 adds for each
global address calculation (with no offset).

```
; ENABLE-LABEL: name: promote_async_load_offset
; ENABLE: liveins: $ttmp7, $vgpr0, $sgpr0_sgpr1
; ENABLE-NEXT: {{  $}}
; ENABLE-NEXT: renamable $vgpr1 = V_LSHLREV_B32_e32 8, $vgpr0, implicit $exec
; ENABLE-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 $vgpr0, 512, 0, implicit $exec
; ENABLE-NEXT: renamable $vgpr3, dead $sgpr_null = V_ADDC_U32_e64 0, killed $vgpr0, killed $vcc_lo, 0, implicit $exec
; ENABLE-NEXT: renamable $vgpr1 = disjoint V_OR_B32_e32 0, killed $vgpr1, implicit $exec
; ENABLE-NEXT: renamable $vgpr0 = V_ADD_U32_e32 256, $vgpr1, implicit $exec
; ENABLE-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr0, $vgpr2_vgpr3, -256, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
; ENABLE-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr1, killed $vgpr2_vgpr3, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)

; DISABLE-LABEL: name: promote_async_load_offset
; DISABLE: liveins: $ttmp7, $vgpr0, $sgpr0_sgpr1
; DISABLE-NEXT: {{  $}}
; DISABLE-NEXT: renamable $vgpr1 = V_LSHLREV_B32_e32 8, $vgpr0, implicit $exec
; DISABLE-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 256, $vgpr0, 0, implicit $exec
; DISABLE-NEXT: renamable $vgpr3, $sgpr_null = V_ADDC_U32_e64 0, $vgpr0, killed $vcc_lo, 0, implicit $exec
; DISABLE-NEXT: renamable $vgpr1 = disjoint V_OR_B32_e32 0, killed $vgpr1, implicit $exec
; DISABLE-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 $vgpr1, killed $vgpr2_vgpr3, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
; DISABLE-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 512, $vgpr0, 0, implicit $exec
; DISABLE-NEXT: renamable $vgpr3, $sgpr_null = V_ADDC_U32_e64 0, killed $vgpr0, killed $vcc_lo, 0, implicit $exec
; DISABLE-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr1, killed $vgpr2_vgpr3, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
```

This PR also promotes the global address to an offset when the offset is
calculated with V_ADD_U64 on applicable gfx versions, (and inversely
adds the LDS offset), whereas previously the optimization opportunity
was missed entirely.
2026-01-26 09:23:17 +01:00
..
GlobalISel
AMDGPU: Ignore type legality in isFAbsFree (#177630)
2026-01-23 19:43:23 +01:00
32-bit-local-address-space.ll
…
a-v-ds-atomic-cmpxchg.ll
AMDGPU: Add agpr variants of multi-data DS instructions (#156420)
2025-09-04 09:13:36 +09:00
a-v-ds-atomicrmw.ll
AMDGPU: Add tests for atomics with AGPR operands (#155820)
2025-08-28 22:21:07 +09:00
a-v-flat-atomic-cmpxchg.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
a-v-flat-atomicrmw.ll
[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)
2025-11-21 15:17:55 +00:00
a-v-global-atomic-cmpxchg.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
a-v-global-atomicrmw.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
aa-as-infer.ll
…
aa-points-to-constant-memory.ll
…
abi-attribute-hints-undefined-behavior.ll
…
abs_i16.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
abs_i32.ll
[AMDGPU] 32-bit abs is not legal on R600 (#164103)
2025-10-18 20:47:40 -05:00
absdiff.ll
[AMDGPU] Lower S_ABSDIFF_I32 to VALU instructions (#167691)
2025-11-13 14:35:44 +01:00
acc-ldst.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
accvgpr-copy.mir
…
accvgpr-spill-scc-clobber.mir
…
add3.ll
…
add64-low-32-bits-known-zero.ll
…
add_i1.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
add_i64.ll
[AMDGPU] Update codegen tests for PR #154069 (#154862)
2025-08-22 07:58:21 -06:00
add_i128.ll
…
add_shl.ll
…
add_sub_u64_pseudos.mir
…
add_u64.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
add-debug.ll
…
add-max.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
add.i16.ll
…
add.ll
…
add.v2i16.ll
[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)
2025-10-17 14:29:37 -04:00
addrspacecast-captured.ll
…
addrspacecast-constantexpr.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
addrspacecast-gas.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
addrspacecast-initializer-unsupported.ll
…
addrspacecast-initializer.ll
…
addrspacecast-known-non-null.ll
…
addrspacecast.gfx6.ll
…
addrspacecast.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
addrspacecast.r600.ll
…
addsub64_carry.ll
[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)
2025-10-22 08:42:29 -05:00
adjust-writemask-cse.ll
…
adjust-writemask-invalid-copy.ll
…
adjust-writemask-vectorized.ll
…
agpr-copy-no-free-registers-assertion-after-ra-failure.ll
…
agpr-copy-no-free-registers.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
agpr-copy-no-vgprs.mir
…
agpr-copy-propagation.mir
AMDGPU: Stop handling AGPR case in getCrossCopyRegClass (#161800)
2025-10-06 23:34:39 +09:00
agpr-copy-reuse-writes.mir
…
agpr-copy-sgpr-no-vgprs.mir
…
agpr-csr.ll
…
agpr-register-count.ll
…
agpr-remat.ll
…
agpr-spill-copy.mir
…
agpr-to-agpr-copy.mir
…
alignbit-pat.ll
[AMDGPU] Ensure divergence for v_alignbit (#129159)
2025-09-26 10:55:56 -07:00
alloc-aligned-tuples-gfx90a.mir
…
alloc-aligned-tuples-gfx908.mir
…
alloc-aligned-tuples-gfx1250.mir
…
alloc-all-regs-reserved-in-class.mir
…
alloca.ll
…
allow-check.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
always-uniform.ll
…
amd.endpgm.ll
…
amdgcn-call-whole-wave.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
[AMDGPU] Fixup 30219f0f4300 (#170266)
2025-12-02 10:16:53 +01:00
amdgcn-ieee.ll
[NFC][AMDGPU] Precommit test amdgcn-ieee.ll (#163118)
2025-10-13 07:00:57 -04:00
amdgcn-load-offset-from-reg.ll
…
amdgcn.bitcast.16bit.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
amdgcn.bitcast.32bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.48bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.64bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.96bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.128bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.160bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.192bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.224bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.256bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.288bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.320bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.352bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.384bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.448bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.512bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.576bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.640bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.704bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.768bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.832bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.896bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.960bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.1024bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
amdgcn.bitcast.ptr.ll
…
amdgcn.private-memory.ll
…
amdgpu-alias-analysis.ll
…
amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
…
amdgpu-attributor-flat-scratch-init-asan.ll
[AMDGPU][Attributor] Stop inferring amdgpu-no-flat-scratch-init in sanitized functions. (#161319)
2025-10-03 21:16:57 +05:30
amdgpu-attributor-intrinsic-missing-nocallback.ll
Reapply "AMDGPU: Do not infer implicit inputs for !nocallback intrinsics" (#176081)
2026-01-15 09:08:27 -06:00
amdgpu-attributor-min-agpr-alloc.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-attributor-nocallback-intrinsics.ll
Reapply "AMDGPU: Do not infer implicit inputs for !nocallback intrinsics" (#176081)
2026-01-15 09:08:27 -06:00
amdgpu-branch-weight-metadata.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
amdgpu-codegenprepare-break-large-phis-heuristics.ll
[AMDGPU] Use reverse iteration in CodeGenPrepare (#145484)
2025-10-10 13:00:40 +02:00
amdgpu-codegenprepare-break-large-phis.ll
…
amdgpu-codegenprepare-fdiv.f64.ll
AMDGPU: Introduce f64 rsq pattern in AMDGPUCodeGenPrepare (#172053)
2025-12-22 15:49:59 +01:00
amdgpu-codegenprepare-fdiv.ll
AMDGPU: Stop requiring afn for f32 rsq formation (#172082)
2025-12-23 18:16:15 +01:00
amdgpu-codegenprepare-fold-binop-select.ll
[AMDGPU] 32-bit ABS is a legal DAG node (#163907)
2025-10-17 16:11:59 -05:00
amdgpu-codegenprepare-idiv.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
amdgpu-codegenprepare-mul24.ll
…
amdgpu-codegenprepare-sqrt.ll
…
amdgpu-cs-chain-cc.ll
…
amdgpu-cs-chain-fp-nosave.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
amdgpu-cs-chain-preserve-cc.ll
…
amdgpu-export-kernel-runtime-handles.ll
…
amdgpu-function-calls-option.ll
…
amdgpu-inline.ll
…
amdgpu-late-codegenprepare-crash-splat.ll
…
amdgpu-late-codegenprepare.ll
…
amdgpu-libcall-sincos-pass-ordering.ll
…
amdgpu-llvm-debuginfo-analyzer.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
amdgpu-lower-exec-sync-and-module-lds.ll
[AMDGPU] Add s_wakeup_barrier instruction for gfx1250 (#170501)
2025-12-10 09:45:13 +01:00
amdgpu-lower-exec-sync-and-sw-lds.ll
[AMDGPU] Add amdgpu-lower-exec-sync pass to lower named-barrier globals (#165692)
2025-11-17 10:08:40 +05:30
amdgpu-lower-exec-sync.ll
[AMDGPU] Add s_wakeup_barrier instruction for gfx1250 (#170501)
2025-12-10 09:45:13 +01:00
amdgpu-max-num-workgroups-load-annotate.ll
…
amdgpu-miscellaneous-uniform-intrinsic.ll
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
amdgpu-mul24-knownbits.ll
…
amdgpu-no-agprs-violations.ll
…
amdgpu-nsa-threshold.ll
…
amdgpu-num-agpr.ll
…
amdgpu-prepare-agpr-alloc.mir
AMDGPU: Start using AV_MOV_B64_IMM_PSEUDO (#154500)
2025-08-22 13:59:36 +09:00
amdgpu-reloc-const.ll
…
amdgpu-shader-calling-convention.ll
…
amdgpu-simplify-libcall-ceil.ll
…
amdgpu-simplify-libcall-copysign.ll
…
amdgpu-simplify-libcall-exp2.ll
…
amdgpu-simplify-libcall-exp.ll
…
amdgpu-simplify-libcall-fabs.ll
…
amdgpu-simplify-libcall-floor.ll
…
amdgpu-simplify-libcall-fma.ll
…
amdgpu-simplify-libcall-fmax-splat.ll
…
amdgpu-simplify-libcall-fmax.ll
…
amdgpu-simplify-libcall-fmin-splat.ll
…
amdgpu-simplify-libcall-fmin.ll
…
amdgpu-simplify-libcall-image-function-signatures.ll
…
amdgpu-simplify-libcall-ldexp-splat.ll
…
amdgpu-simplify-libcall-ldexp.ll
…
amdgpu-simplify-libcall-log2.ll
…
amdgpu-simplify-libcall-log10.ll
…
amdgpu-simplify-libcall-log.ll
…
amdgpu-simplify-libcall-mad.ll
…
amdgpu-simplify-libcall-pow-codegen.ll
…
amdgpu-simplify-libcall-pow.ll
…
amdgpu-simplify-libcall-pown.ll
…
amdgpu-simplify-libcall-powr.ll
…
amdgpu-simplify-libcall-rint.ll
…
amdgpu-simplify-libcall-rootn.ll
[IR] Add new function attribute nocreateundeforpoison (#164809)
2025-11-04 12:00:44 +00:00
amdgpu-simplify-libcall-round.ll
…
amdgpu-simplify-libcall-sincos.defined.ll
…
amdgpu-simplify-libcall-sincos.defined.nobuiltin.ll
…
amdgpu-simplify-libcall-sincos.defined.sin.cos.ll
…
amdgpu-simplify-libcall-sincos.ll
Use AllocaInst::getAllocationSize instead of manual size calculations (#176486)
2026-01-19 09:55:52 -05:00
amdgpu-simplify-libcall-sincos.nobuiltins.ll
…
amdgpu-simplify-libcall-sincos.weak.ll
…
amdgpu-simplify-libcall-sqrt.ll
…
amdgpu-simplify-libcall-trunc.ll
…
amdgpu-simplify-libcall-unexpected-types.ll
…
amdgpu-simplify-uniform-waterfall.ll
[AMDGPU] Stop optimising readfirstlane in pass AMDGPUUniformIntrinsicCombine (#166955)
2025-11-08 01:17:39 +05:30
amdgpu-snop-padding.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-dynamic-indirect-access.ll
…
amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-dynamic-lds-test.ll
…
amdgpu-sw-lower-lds-lower-all.ll
…
amdgpu-sw-lower-lds-lower-none.ll
…
amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
…
amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access.ll
…
amdgpu-sw-lower-lds-multiple-blocks-return-asan.ll
…
amdgpu-sw-lower-lds-multiple-blocks-return.ll
…
amdgpu-sw-lower-lds-non-kernel-declaration.ll
…
amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
…
amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-dynamic-lds-test.ll
…
amdgpu-sw-lower-lds-static-indirect-access-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-indirect-access-function-param.ll
…
amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
…
amdgpu-sw-lower-lds-static-indirect-access-lower-none.ll
…
amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
…
amdgpu-sw-lower-lds-static-indirect-access-nested.ll
…
amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
…
amdgpu-sw-lower-lds-static-indirect-access.ll
…
amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-lds-O0.ll
…
amdgpu-sw-lower-lds-static-lds-test-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-lds-test.ll
…
amdgpu-sw-lower-lds-static-lds-vector-ptrs.ll
…
amdgpu-uniform-intrinsic-combine.ll
[AMDGPU] Add optimization for llvm.amdgcn.wave.shuffle in uniform cases (#174795)
2026-01-14 17:49:42 +00:00
amdgpu-uniform-temporal-divergence.ll
[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)
2025-10-30 12:32:32 +05:30
amdgpu-unroll-threshold.ll
…
amdgpu.private-memory.ll
…
amdgpu.work-item-intrinsics.deprecated.ll
…
amdhsa-kernarg-preload-num-sgprs.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
amdhsa-trap-num-sgprs.ll
…
amdpal_scratch_mergedshader.ll
…
amdpal-callable.ll
…
amdpal-chain-metadata.ll
…
amdpal-cs.ll
…
amdpal-elf.ll
…
amdpal-es.ll
…
amdpal-gs.ll
…
amdpal-hs.ll
…
amdpal-ls.ll
…
amdpal-metadata-agpr-register-count.ll
…
amdpal-msgpack-cs.ll
…
amdpal-msgpack-default.ll
…
amdpal-msgpack-denormal.ll
…
amdpal-msgpack-dx10-clamp.ll
…
amdpal-msgpack-es.ll
…
amdpal-msgpack-gs.ll
…
amdpal-msgpack-hs.ll
…
amdpal-msgpack-ieee.ll
…
amdpal-msgpack-ls.ll
…
amdpal-msgpack-ps.ll
…
amdpal-msgpack-psenable.ll
…
amdpal-msgpack-vs.ll
…
amdpal-ps.ll
…
amdpal-psenable.ll
…
amdpal-usersgpr-init.ll
…
amdpal-vs.ll
…
amdpal.ll
…
and_or.ll
…
and-gcn.ll
…
and.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
and.r600.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
andorbitset.ll
…
andorn2.ll
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
2025-09-03 20:04:01 +01:00
andorxorinvimm.ll
…
annotate-existing-abi-attributes.ll
[AMDGPU][Attributor] Remove final update of waves-per-eu after the attributor run (#155246)
2025-08-27 14:11:03 -04:00
annotate-kernel-features-hsa-call.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
annotate-kernel-features-hsa.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
annotate-kernel-features.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
annotate-noclobber.ll
…
anonymous-gv.ll
…
any_extend_vector_inreg.ll
[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (#165295)
2025-11-11 13:14:48 -06:00
anyext.ll
[AMDGPU] Use "v_bfi_b32 x, 0, z" to implement (z & ~x) (#156636)
2025-09-03 11:00:03 +00:00
are-loads-from-same-base-ptr.ll
…
array-ptr-calc-i32.ll
…
array-ptr-calc-i64.ll
…
artificial-terminators.mir
…
ashr64_reduce_flags.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
ashr64_reduce.ll
…
ashr.v2i16.ll
…
asm-printer-check-vcc.mir
…
at-least-one-def-value-assert.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
atomic_cmp_swap_local.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
atomic_load_add.ll
…
atomic_load_local.ll
[AMDGPU] Use true16 loads with +real-true16 and sram-ecc (#161256)
2025-10-07 09:31:07 -07:00
atomic_load_sub.ll
…
atomic_optimization_split_dt_update.ll
…
atomic_optimizations_buffer.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
atomic_optimizations_global_pointer.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
atomic_optimizations_local_pointer.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
atomic_optimizations_pixelshader.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
atomic_optimizations_raw_buffer.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
atomic_optimizations_struct_buffer.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
atomic_store_local.ll
[AMDGPU] Use true16 loads with +real-true16 and sram-ecc (#161256)
2025-10-07 09:31:07 -07:00
atomic-optimizer-promote-i8.ll
…
atomic-optimizer-strict-wqm.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
atomicrmw_usub_cond.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
atomicrmw_usub_sat.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
atomicrmw-bf16-gfx11plus.ll
…
atomicrmw-expand.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
atomicrmw-nand.ll
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
2025-09-03 20:04:01 +01:00
atomics_cond_sub.ll
AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)
2025-12-09 23:13:33 +00:00
atomics-cas-remarks-gfx90a.ll
…
atomics-hw-remarks-gfx90a.ll
…
atomics-system-scope.ll
AMDGPU: Fix constrain register logic for physregs (#161794)
2025-10-03 21:20:36 +09:00
attr-amdgpu-align.ll
[AMDGPU] Apply alignment attr for make.buffer.rsrc (#166914)
2025-12-08 12:48:54 +08:00
attr-amdgpu-flat-work-group-size-vgpr-limit.ll
…
attr-amdgpu-flat-work-group-size.ll
…
attr-amdgpu-max-num-workgroups-propagate.ll
[AMDGPU][Attributor] Remove final update of waves-per-eu after the attributor run (#155246)
2025-08-27 14:11:03 -04:00
attr-amdgpu-max-num-workgroups.ll
…
attr-amdgpu-num-sgpr.ll
…
attr-amdgpu-num-vgpr.ll
…
attr-amdgpu-num-workgroups_error_check.ll
…
attr-amdgpu-waves-per-eu.ll
Revert "[AMDGPU] Allow amdgpu-waves-per-eu to lower target occupancy range" (#177544)
2026-01-23 08:55:14 +00:00
attr-unparseable.ll
…
attributor-flatscratchinit-globalisel.ll
…
attributor-flatscratchinit-undefined-behavior2.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
attributor-flatscratchinit-undefined-behavior.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
attributor-flatscratchinit.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
attributor-loop-issue-58639.ll
[AMDGPU][Attributor] Remove final update of waves-per-eu after the attributor run (#155246)
2025-08-27 14:11:03 -04:00
attributor-noalias-addrspace.ll
Revert "[AMDGPU][Attributor] Infer inreg attribute in AMDGPUAttributor (#146720)"
2025-08-18 22:59:52 -04:00
attributor-noopt.ll
…
av_movimm_pseudo_expansion.mir
AMDGPU: Special case align requirement for AV_MOV_B64_IMM_PSEUDO
2025-09-04 09:55:39 +09:00
av_spill_cross_bb_usage.mir
[MachineSink] Remove subrange of live-ins from super register as well. (#159145)
2025-09-26 14:45:26 +09:00
av-spill-expansion-with-machine-cp.mir
…
av-split-dead-valno-crash.ll
[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)
2025-11-21 15:17:55 +00:00
back-off-barrier-subtarget-feature.ll
[AMDGPU] Reenable BackOffBarrier on GFX11/12 (#155370)
2025-09-02 09:37:43 +02:00
bad-agpr-vgpr-regalloc-priority.mir
…
barrier-elimination-gfx12.ll
…
barrier-elimination.ll
…
barrier-signal-wait-latency.ll
[AMDGPU] Schedule independent instructions between s_barrier_signal and s_barrier_wait (#172057)
2025-12-16 11:48:50 +05:30
basic-branch.ll
…
basic-call-return.ll
…
basic-loop.ll
…
bb-prolog-spill-during-regalloc.ll
…
bf16-conversions.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
bf16-math.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
bf16-ops.ll
…
bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
bfe_uint.ll
…
bfe-combine.ll
…
bfe-patterns.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
bfi_int.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
bfi_int.r600.ll
…
bfi_nested.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
bfm.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
big_alu.ll
…
bit-op-reduce-width-known-bits.ll
…
bitcast_vector_bigint.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
bitcast-constant-to-vector.ll
…
bitcast-v4f16-v4i16.ll
…
bitcast-vector-extract.ll
…
bitop3.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
bitreverse-inline-immediates.ll
…
bitreverse.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BITREVERSE (#172101)
2025-12-15 17:45:33 -08:00
blender-coalescer-verifier-error-empty-subrange.mir
…
blender-no-live-segment-at-def-implicit-def.ll
…
block-should-not-be-in-alive-blocks.mir
…
br_cc.f16.ll
[AMDGPU] Allow 16-bit imm folding in real true16 (#173318)
2026-01-15 11:15:12 -08:00
branch-condition-and.ll
…
branch-folder-requires-no-phis.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
branch-folding-implicit-def-subreg.ll
[AMDGPU] Invert scc uses to delete s_cmp_eq* (#167382)
2026-01-14 10:24:24 -06:00
branch-relax-bundle.ll
…
branch-relax-indirect-branch.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
branch-relax-no-terminators.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
branch-relax-spill.ll
…
branch-relaxation-debug-info.mir
…
branch-relaxation-gfx10-branch-offset-bug.ll
…
branch-relaxation-gfx1250.ll
[AMDGPU] Disable s_add_pc_i64 instruction (#175644)
2026-01-14 23:01:43 +01:00
branch-relaxation-inst-size-gfx10.ll
…
branch-relaxation-inst-size-gfx11.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
branch-relaxation.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
branch-uniformity.ll
…
break-smem-soft-clauses.mir
…
break-vmem-soft-clauses.mir
…
bswap.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
buffer-atomic-fadd.f32-no-rtn.ll
…
buffer-atomic-fadd.f32-rtn.ll
AMDGPU: Start to use AV classes for unknown vector class (#166482)
2025-11-13 09:28:33 -08:00
buffer-atomic-fadd.f64.ll
AMDGPU: Start to use AV classes for unknown vector class (#166482)
2025-11-13 09:28:33 -08:00
buffer-atomic-fadd.v2f16-no-rtn.ll
…
buffer-atomic-fadd.v2f16-rtn.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
buffer-fat-pointer-atomicrmw-fadd.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
buffer-fat-pointer-atomicrmw-fmax.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
buffer-fat-pointer-atomicrmw-fmin.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
buffer-fat-pointer-atomicrmw-usub_cond.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
buffer-fat-pointer-atomicrmw-usub_sat.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
buffer-fat-pointer-unsupported-errors.ll
…
buffer-fat-pointers-contents-legalization.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
buffer-fat-pointers-memcpy.ll
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
2025-12-03 11:13:52 +01:00
buffer-intrinsic-mmo-type.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
buffer-intrinsics-mmo-offsets.ll
…
buffer-rsrc-ptr-ops.ll
…
buffer-schedule.ll
…
bug-cselect-b64.ll
…
bug-deadlanes.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
bug-multi-operands-to-update-after-fold.mir
…
bug-pk-f32-imm-fold.mir
[AMDGPU] Don't fold an i64 immediate value if it can't be replicated from its lower 32-bit (#168458)
2025-11-18 17:11:10 -05:00
bug-sdag-emitcopyfromreg.ll
…
bug-sdag-scheduler-cycle.ll
…
bug-undef-spilled-agpr.mir
…
bug-v4f64-subvector.ll
…
bug-vopc-commute.ll
…
build_vector-r600.ll
…
build_vector.gfx11plus.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
build_vector.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
build-vector-insert-elt-infloop.ll
…
build-vector-packed-partial-undef.ll
[AMDGPU][True16] extractEltcheap check 16bit in true16 mode (#171762)
2026-01-20 09:45:05 -05:00
bundle-breaks-phy-liveness.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
bundle-latency.mir
…
bypass-div.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
byval-frame-setup.ll
…
call_fs.ll
…
call-alias-register-usage0.ll
…
call-alias-register-usage1.ll
…
call-alias-register-usage2.ll
…
call-alias-register-usage3.ll
…
call-alias-register-usage-agpr.ll
…
call-args-inreg-bfloat.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-args-inreg-no-sgpr-for-csrspill-xfail.ll
…
call-args-inreg.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-argument-types.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
call-c-function.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-constant.ll
…
call-constexpr.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-defs-mode-register.ll
[DAG] Add strictfp implicit def reg after metadata. (#168282)
2025-11-17 10:57:21 +00:00
call-encoding.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-graph-register-usage.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-preserved-registers.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-reqd-group-size.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
call-return-types.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-skip.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-waitcnt.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-waw-waitcnt.mir
…
callbr-intrinsics.ll
[AMDGPU][GlobalISel] Fix / workaround amdgcn.kill/.unreachable lowering (#170639)
2025-12-04 13:42:53 +01:00
callbr.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
callee-frame-setup.ll
…
callee-special-input-sgprs-fixed-abi.ll
…
callee-special-input-vgprs-packed.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
callee-special-input-vgprs.ll
[AMDGPU] callee-special-input-vgprs.ll / callee-special-input-vgprs-packed.ll - regenerate test coverage (#159587)
2025-09-18 15:19:48 +00:00
calling-conventions.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
captured-frame-index.ll
…
carryout-selection.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
cayman-loop-bug.ll
…
cc-entry.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
cc-sgpr-limit.ll
…
cc-sgpr-over-limit.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
cc-update.ll
…
cf_end.ll
…
cf-loop-on-constant.ll
…
cf-stack-bug.ll
…
cgp-addressing-modes-flat.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
cgp-addressing-modes-gfx908.ll
…
cgp-addressing-modes-gfx1030.ll
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
2025-12-05 12:37:33 +00:00
cgp-addressing-modes-smem.ll
…
cgp-addressing-modes.ll
…
cgp-bitfield-extract.ll
[AMDGPU] Ensure divergence for v_alignbit (#129159)
2025-09-26 10:55:56 -07:00
chain-hi-to-lo.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
chain-node-divergence-update-crash-issue-173885.ll
[SelectionDAG] Skip chain node when updating divergence (#173885)
2025-12-29 14:54:40 -05:00
change-scc-to-vcc.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
check-subtarget-features.ll
…
clamp-modifier.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
clamp-omod-special-case.mir
…
clamp.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
cluster_stores.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
cluster-dims.ll
[AMDGPU] Add the support for .cluster_dims code object metadata (#158721)
2025-09-15 16:13:07 -04:00
cluster-flat-loads-postra.mir
…
cluster-flat-loads.mir
…
cmp_shrink.mir
…
cndmask-no-def-vcc.ll
…
coalesce-copy-to-agpr-to-av-registers.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
coalesce-identity-copies-undef-subregs.mir
…
coalesce-into-dead-subreg-copies.mir
…
coalesce-liveout-undef-copy.mir
…
coalesce-vgpr-alignment.ll
…
coalescer_distribute.ll
…
coalescer_remat.ll
…
coalescer-avoid-coalesce-class-with-no-registers.ll
RegisterCoalescer: Do not introduce uses of empty register classes (#161809)
2025-10-10 04:01:04 +00:00
coalescer-avoid-coalesce-class-with-no-registers.mir
RegisterCoalescer: Do not introduce uses of empty register classes (#161809)
2025-10-10 04:01:04 +00:00
coalescer-early-clobber-subreg.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
coalescer-extend-pruned-subrange.mir
…
coalescer-identical-values-undef.mir
…
coalescer-remat-dead-use.mir
…
coalescer-removepartial-extend-undef-subrange.mir
…
coalescer-subranges-another-copymi-not-live.mir
…
coalescer-subranges-another-prune-error.mir
…
coalescer-subranges-prune-kill-copy.mir
…
coalescer-subreg-join.mir
…
coalescer-subregjoin-fullcopy.mir
…
coalescer-undef-subreg-use-invalid-lanemask.mir
…
coalescer-with-subregs-bad-identical.mir
…
coalescing_makes_lanes_undef.mir
Fix typos and spelling errors across codebase (#156270)
2026-01-13 11:52:46 -05:00
coalescing-subreg-was-undef-but-became-def.mir
…
coalescing-with-subregs-in-loop-bug.mir
…
code-object-v3.ll
…
code-size-estimate-gfx1250.ll
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
code-size-estimate.ll
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
code-size-estimate.mir
…
codegen-internal-only-func.ll
…
codegen-prepare-addrmode-sext.ll
…
codegen-prepare-addrspacecast-non-null-vector.ll
…
codegen-prepare-addrspacecast-non-null.ll
AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)
2025-12-01 18:40:26 -05:00
collapse-endcf2.mir
…
collapse-endcf-broken.mir
…
collapse-endcf.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
collapse-endcf.mir
…
combine_andor_with_cmps.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
combine_vloads.ll
…
combine-add-zext-xor.ll
…
combine-and-sext-bool.ll
…
combine-cond-add-sub.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
combine-ftrunc.ll
…
combine-reg-or-const.ll
…
combine-sreg64-inits.mir
…
combine-vload-extract.ll
…
comdat.ll
…
commute_modifiers.ll
…
commute-compares-scalar-float.ll
…
commute-compares.ll
…
commute-frame-index-operand.mir
…
commute-op-sel.mir
…
commute-shifts.ll
…
commute-vop3.mir
…
complex-folding.ll
…
compute-known-bits-nofpclass.ll
DAG: Handle AssertNoFPClass in computeKnownBits (#167289)
2025-11-10 08:56:08 -08:00
computeKnownBits-scalar-to-vector-crash.ll
…
computeNumSignBits-mul.ll
…
concat_vectors.ll
…
constant-address-space-32bit.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
constant-fold-imm-immreg.mir
…
constant-fold-mi-operands.ll
…
constrained-shift.ll
…
control-flow-fastregalloc.ll
…
control-flow-optnone.ll
…
convergence-laneops.ll
…
convergence-tokens.ll
…
convergent-inlineasm.ll
…
copy_phys_vgpr64.mir
…
copy_to_scc.ll
…
copy-hoist-no-spills.ll
…
copy-illegal-type.ll
…
copy-overlap-sgpr-kill.mir
…
copy-overlap-vgpr-kill.mir
…
copy-phys-reg-implicit-operand-kills-subregs.mir
…
copy-to-reg-frameindex.ll
AMDGPU: Fix verifier error when waterfall call target is in AV register (#168017)
2025-11-14 09:49:40 -08:00
copy-to-reg-scc-clobber.ll
…
copy-to-reg.ll
…
copy-vgpr-clobber-spill-vgpr.mir
…
copyprop_regsequence_with_undef.mir
…
copysign-simplify-demanded-bits.ll
DAG: Fold copysign with a known signmask to a disjoint or (#167266)
2025-11-10 08:55:45 -08:00
copysign-to-disjoint-or-combine.ll
DAG: Fix arith_fence handling in SignBitIsZeroFP (#172537)
2025-12-16 20:10:38 +00:00
couldnt-join-subrange-3.mir
…
cross-block-use-is-not-abi-copy.ll
…
cse-convergent.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
cse-phi-incoming-val.ll
…
csr-gfx10.ll
…
csr-sgpr-spill-live-ins.mir
…
ctlz_zero_undef.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
ctlz.ll
AMDGPU: Use generic legality checks instead of checking subtarget feature (#177656)
2026-01-23 20:43:44 +01:00
ctpop16.ll
[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)
2025-10-22 08:42:29 -05:00
ctpop64.ll
…
ctpop.ll
…
cttz_zero_undef.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
cttz.ll
…
cube.ll
…
cvt_f32_ubyte.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
cvt_flr_i32_f32.ll
…
cvt_rpi_i32_f32.ll
…
dag-divergence-atomic.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
dag-divergence.ll
Revert "SelectionDAG: Do not propagate divergence through glue (#174766)"
2026-01-07 14:23:15 +00:00
dag-preserve-disjoint-flag.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
dagcomb-extract-vec-elt-different-sizes.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
dagcomb-mullohi.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
dagcomb-shuffle-vecextend-non2.ll
…
dagcombine-fma-crash.ll
…
dagcombine-fma-fmad.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
dagcombine-fmul-sel.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
dagcombine-lshr-and-cmp.ll
…
dagcombine-reassociate-bug.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
dagcombine-select.ll
[AMDGPU] Use APInt in performSetCCCombine (#176564)
2026-01-20 09:14:25 +08:00
dagcombine-setcc-select.ll
…
dagcombine-v1i8-extractvecelt-crash.ll
…
dagcombiner-bug-illegal-vec4-int-to-fp.ll
…
dbg-info-inline-at.ll
…
dbg-value-ends-sched-region.mir
…
dbg-value-starts-sched-region.mir
…
dce-disjoint-intervals.mir
…
dead_bundle.mir
…
dead_copy.mir
…
dead-lane.mir
…
dead-machine-elim-after-dead-lane.ll
…
debug_frame.ll
…
debug-independence-adjustSchedDependency.ll
[AMDGPU] Latency calculation must be independent of meta insts (#177052)
2026-01-21 12:19:55 -06:00
debug-value2.ll
…
debug-value-scheduler-crash.mir
…
debug-value-scheduler-liveins.mir
…
debug-value-scheduler.mir
…
debug-value.ll
…
debug.ll
…
default_amdhsa_code_object_version.ll
…
default-flat-work-group-size-overrides-waves-per-eu.ll
Revert "[AMDGPU] Allow amdgpu-waves-per-eu to lower target occupancy range" (#177544)
2026-01-23 08:55:14 +00:00
default-fp-mode.ll
…
detect-dead-lanes.mir
…
direct-indirect-call.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
directive-amdgcn-target.ll
[AMDGPU] Define gfx1310 target with ELF number 0x50 (#177355)
2026-01-22 17:08:38 +01:00
disable_form_clauses.ll
…
disable-preload-kernargs.ll
[AMDGPU] Add an option to completely disable kernel argument preload (#153975)
2025-08-18 09:44:20 -04:00
disconnected-predset-break-bug.ll
…
div_i128.ll
Revert "SelectionDAG: Do not propagate divergence through glue (#174766)"
2026-01-07 14:23:15 +00:00
div_v2i128.ll
Revert "SelectionDAG: Do not propagate divergence through glue (#174766)"
2026-01-07 14:23:15 +00:00
div-rem-by-constant-64.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
diverge-extra-formal-args.ll
…
diverge-interp-mov-lower.ll
…
diverge-switch-default.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
divergence-at-use.ll
…
divergence-driven-abs.ll
…
divergence-driven-bfe-isel.ll
…
divergence-driven-bitreverse.ll
…
divergence-driven-buildvector.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
divergence-driven-ctlz-cttz.ll
…
divergence-driven-ctpop.ll
…
divergence-driven-min-max.ll
…
divergence-driven-negsubinlineconst.ll
…
divergence-driven-not-isel.ll
…
divergence-driven-sext-inreg.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
divergence-driven-trunc-to-i1.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
divergence-driven-xnor.ll
…
divergent-branch-uniform-condition.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
divrem24-assume.ll
…
do-not-fold-copy.mir
…
do-not-unify-divergent-exit-nodes-with-musttail.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
dpp64_combine.ll
[AMDGPU] gfx1251 VOP3 dpp support (#159654)
2025-09-18 16:18:09 -07:00
dpp64_combine.mir
[AMDGPU] gfx1251 VOP1 dpp support (#159637)
2025-09-18 13:42:06 -07:00
dpp_combine_gfx11.mir
AMDGPU: Fix DPP combiner using isOperandLegal on incomplete inst (#155595)
2025-09-03 01:19:01 +09:00
dpp_combine_gfx1250.mir
…
dpp_combine-true16.mir
…
dpp_combine.ll
[AMDGPU] gfx1251 VOP2 dpp support (#159641)
2025-09-18 15:38:29 -07:00
dpp_combine.mir
…
drop-mem-operand-move-smrd.ll
…
ds_gws_align.ll
…
ds_permute_a_v.ll
AMDGPU: Define agpr versions of ds permute instructions (#156695)
2025-09-04 15:13:59 +09:00
ds_read2_offset_order.ll
…
ds_read2_superreg.ll
…
ds_read2-gfx1250.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
ds_read2.ll
…
ds_read2st64.ll
…
ds_write2_a_v.ll
Revert "CodeGen: Record MMOs in finalizeBundle" (#166520)
2025-11-05 11:11:08 +01:00
ds_write2.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
ds_write2st64.ll
…
ds-alignment.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
ds-combine-large-stride.ll
…
ds-combine-with-dependence.ll
…
ds-negative-offset-addressing-mode-loop.ll
…
ds-read2-write2-debug-info.ll
AMDGPU: Use getMergedLocation in SILoadStoreOptimizer (#156396)
2025-11-10 15:04:24 -08:00
ds-sub-offset.ll
…
ds-vectorization-alignment.ll
…
dst-sel-hazard.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
dual-source-blend-export.ll
…
dummy-regalloc-priority-advisor.mir
…
dumpcode.ll
…
duplicate-attribute-indirect.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
dvgpr_sym_fail_too_many_block_size_16_anon.ll
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
dvgpr_sym_fail_too_many_block_size_16.ll
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
dvgpr_sym.ll
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
dwarf-multi-register-use-crash.ll
…
dynamic_stackalloc.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
dynamic-vgpr-reserve-stack-for-cwsr.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
early-if-convert-cost.ll
…
early-if-convert.ll
…
early-inline-alias.ll
…
early-inline.ll
…
early-lis-two-address-partial-def.mir
…
early-tailduplicator-nophis.mir
…
early-tailduplicator-terminator.mir
…
early-term.mir
…
eh_frame.ll
…
elf-header-flags-mach.ll
[AMDGPU] Define gfx1310 target with ELF number 0x50 (#177355)
2026-01-22 17:08:38 +01:00
elf-header-flags-sramecc.ll
AMDGPU: Add gfx1250 to sram-ecc elf header flags test (#162107)
2025-10-06 16:22:46 +00:00
elf-header-flags-xnack.ll
…
elf-header-osabi.ll
…
elf-notes.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
elf.ll
…
elf.metadata.ll
…
elf.r600.ll
…
eliminate-frame-index-s-add-i32.mir
…
eliminate-frame-index-s-add-u32.mir
…
eliminate-frame-index-s-mov-b32.mir
…
eliminate-frame-index-scalar-bit-ops.mir
…
eliminate-frame-index-v-add-co-u32-wave32.mir
…
eliminate-frame-index-v-add-co-u32.mir
…
eliminate-frame-index-v-add-u32.mir
…
else.ll
…
emit-high-vgprs.mir
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
empty-function.ll
…
empty-text.ll
…
enable-no-signed-zeros-fp-math.ll
…
enable-scratch-only-dynamic-stack.ll
…
endcf-loop-header.ll
…
endpgm-dce.mir
…
exceed-max-sgprs.ll
…
exec-mask-opt-cannot-create-empty-or-backward-segment.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
expand-atomicrmw-syncscope.ll
…
expand-scalar-carry-out-select-user.ll
[AMDGPU] Delete redundant s_or_b32 (#165261)
2025-11-07 09:27:20 -06:00
expand-si-indirect.mir
…
expand-variadic-call.ll
…
expand-waitcnt-profiling.ll
[AMDGPU][SIInsertWaitcnt] Implement Waitcnt Expansion for Profiling (#169345)
2026-01-12 17:35:06 +05:30
expert_scheduling_gfx12.mir
[AMDGPU] Add support for GFX12 expert scheduling mode 2 (#170319)
2026-01-09 15:49:10 +00:00
export-cluster-postra.mir
…
extend-bit-ops-i16.ll
…
extend-phi-subrange-not-in-parent.mir
…
extend-wwm-virt-reg-liveness.mir
…
extload-align.ll
…
extload-private.ll
…
extload.ll
…
extra-lds-size.ll
[AMDGPU] update LDS block size for gfx1250 (#167614)
2025-11-17 16:03:47 -08:00
extra-sroa-after-unroll.ll
…
extract_subvector_vec4_vec3.ll
…
extract_vector_dynelt.ll
Reapply "[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#170323) (#171838)
2025-12-15 09:05:00 +01:00
extract_vector_elt-f16.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
extract_vector_elt-f64.ll
…
extract_vector_elt-i8.ll
…
extract_vector_elt-i16.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
extract_vector_elt-i64.ll
…
extract-load-i1.ll
…
extract-lowbits.ll
…
extract-subvector-16bit.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
extract-subvector-equal-length.ll
…
extract-subvector.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
extract-vector-elt-build-vector-combine.ll
…
extractelt-to-trunc.ll
…
fabs-known-signbit-combine-fast-fdiv-lowering.ll
AMDGPU: Avoid introducing unnecessary fabs in fast fdiv lowering (#172553)
2025-12-17 00:22:12 +01:00
fabs-r600.ll
…
fabs.bf16.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
fabs.f16.ll
AMDGPU: Ignore type legality in isFAbsFree (#177630)
2026-01-23 19:43:23 +01:00
fabs.f64.ll
…
fabs.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
fadd64.ll
…
fadd-fma-fmul-combine.ll
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
fadd.f16.ll
…
fadd.ll
…
fast-ra-kills-vcc.mir
…
fast-regalloc-bundles.mir
…
fast-unaligned-load-store.global.ll
…
fast-unaligned-load-store.private.ll
…
fastregalloc-illegal-subreg-physreg.mir
…
fastregalloc-self-loop-heuristic.mir
…
fastregalloc-sgpr-only.mir
…
fcanonicalize-elimination.bf16.ll
…
fcanonicalize-elimination.ll
[DAGCombiner] Relax nsz constraint for FP optimizations (#165011)
2025-12-09 12:07:46 +02:00
fcanonicalize.bf16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
fcanonicalize.f16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fcanonicalize.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FCANONICALIZE (#174662)
2026-01-09 08:51:16 -08:00
fceil64.ll
…
fceil.ll
…
fcmp64.ll
…
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.f16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
fcmp.ll
…
fconst64.ll
…
fcopysign.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fcopysign.f16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fcopysign.f32.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fcopysign.f32.r600.ll
…
fcopysign.f64.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fcopysign.gfx11plus.ll
[AMDGPU][True16][CodeGen] Fixed two lit tests (#157684)
2025-09-09 11:13:23 -04:00
fdiv32-to-rcp-folding.ll
…
fdiv_flags.f32.ll
[AMDGPU] Use reverse iteration in CodeGenPrepare (#145484)
2025-10-10 13:00:40 +02:00
fdiv-nofpexcept.ll
…
fdiv.bf16.ll
[AMDGPU] Add support for safe bfloat16 fdiv on targets with bf16 trans instructions (#154373)
2025-08-19 16:03:45 -04:00
fdiv.f16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fdiv.f64.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
fdiv.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
fdot2.ll
…
fence-barrier.ll
…
fence-lds-read2-write2.ll
…
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
ffloor.f64.ll
…
ffloor.ll
…
finalize-isel-kill-scc-vcc.mir
…
finalizebundle.mir
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
fix-crash-valu-hazard.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-frame-ptr-reg-copy-livein.ll
…
fix-frame-reg-in-custom-csr-spills.ll
…
fix-sgpr-copies-f16-fake16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-f16-gfx12-fake16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-f16-gfx12-true16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-f16-true16.mir
[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)
2025-10-17 14:29:37 -04:00
fix-sgpr-copies-f16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-nondeterminism.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
fix-sgpr-copies-phi-block-end-iterator-debugloc.ll
…
fix-sgpr-copies-phi-regression-av-classes.ll
[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)
2025-11-21 15:17:55 +00:00
fix-sgpr-copies-phi-regression-issue130646-issue130119.ll
…
fix-sgpr-copies-phi-regression-issue130646.mir
…
fix-sgpr-copies-readfirstlane-av-register-regression.ll
AMDGPU: Constrain readfirstlane operand when writing to m0 (#168004)
2025-11-14 17:18:43 +00:00
fix-sgpr-copies-vgpr16-to-spgr32.ll
…
fix-sgpr-copies-wwm.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
fix-sgpr-copies-wwm.mir
…
fix-sgpr-copies.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-vgpr-copies.mir
…
fix-wwm-vgpr-copy.ll
…
flat_atomics_i32_system.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
flat_atomics_i64_noprivate.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
flat_atomics_i64_system_noprivate.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
flat_atomics_i64_system.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
flat_atomics_i64.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
flat_atomics.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
flat-address-space.ll
…
flat-atomic-fadd.f32.ll
…
flat-atomic-fadd.f64.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
flat-atomicrmw-fadd.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
flat-atomicrmw-fmax.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
flat-atomicrmw-fmin.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
flat-atomicrmw-fsub.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
flat-error-unsupported-gpu-hsa.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
flat-for-global-subtarget-feature.ll
…
flat-load-clustering.mir
…
flat-load-saddr-to-vaddr.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
flat-offset-bug.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
flat-saddr-atomics.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
flat-saddr-load.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
flat-saddr-store.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
flat-scratch-alloca-issue-155902.ll
[CodeGen] Consider imm offsets when sorting framerefs (#171012)
2026-01-08 17:48:30 -05:00
flat-scratch-fold-fi-gfx1250.mir
…
flat-scratch-fold-fi.mir
…
flat-scratch-i8-i16.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
flat-scratch-init.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
flat-scratch-reg.ll
…
flat-scratch-svs.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
flat-scratch.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
floor.ll
[SDAG] Remove most non-canonical libcall handing (#171288)
2025-12-10 11:45:26 +01:00
fma-combine.ll
[SelectionDAG] Remove NoInfsFPMath uses (#162788)
2025-10-12 09:34:24 +08:00
fma-mix.gfx11plus.ll
[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)
2025-09-24 11:27:26 -04:00
fma.f16.gfx11plus.ll
[AMDGPU][True16][CodeGen] insert proper register for 16bit data type in vop3p insts (#153143)
2025-08-14 12:02:15 -04:00
fma.f16.ll
[AMDGPU] Extend RA hints to handle VGPR_16_Lo128 (#176819)
2026-01-19 13:41:14 -08:00
fma.f64.ll
…
fma.ll
…
fmac.sdwa.ll
…
fmad-formation-fmul-distribute-denormal-mode.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
fmad.ll
…
fmamk_fmaak-t16.mir
[AMDGPU] Make VGPR_16_Lo128 allocatable (#173309)
2026-01-14 10:40:05 -08:00
fmax3-maximumnum.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fmax3.f64.ll
…
fmax3.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
fmax_legacy.f16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fmax_legacy.f64.ll
…
fmax_legacy.ll
[DAGCombiner] Remove most NoSignedZerosFPMath uses (#161180)
2025-09-30 11:44:34 +08:00
fmax.ll
…
fmaximum3.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
fmaximum3.v2f16.ll
…
fmaximum.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
fmaxnum.f64.ll
…
fmaxnum.ll
AMDGPU: Remove some unnecessary callsite attributes from tests (#174270)
2026-01-03 10:53:33 +00:00
fmaxnum.r600.ll
…
fmed3-cast-combine.ll
AMDGPU: Ignore type legality in isFAbsFree (#177630)
2026-01-23 19:43:23 +01:00
fmed3.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fmed3.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fmin3-minimumnum.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fmin3.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
fmin_fmax_legacy.amdgcn.ll
[DAGCombiner] Remove most NoSignedZerosFPMath uses (#161180)
2025-09-30 11:44:34 +08:00
fmin_legacy.f16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fmin_legacy.f64.ll
…
fmin_legacy.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
fmin.ll
…
fminimum3.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
fminimum3.v2f16.ll
…
fminimum.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
fminnum.f64.ll
…
fminnum.ll
AMDGPU: Remove some unnecessary callsite attributes from tests (#174270)
2026-01-03 10:53:33 +00:00
fminnum.r600.ll
…
fmul64.ll
…
fmul-2-combine-multi-use.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
fmul-to-ldexp.ll
[AMDGPU] Extend RA hints to handle VGPR_16_Lo128 (#176819)
2026-01-19 13:41:14 -08:00
fmul.f16.ll
…
fmul.ll
…
fmuladd.f16.ll
…
fmuladd.f32.ll
…
fmuladd.f64.ll
…
fmuladd.v2f16.ll
…
fncall-implicitdef.ll
[LiveVariables] Mark use without implicit if defined at instr (#119446)
2025-08-18 08:34:59 -04:00
fnearbyint.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
fneg-combines-gfx1200.ll
[AMDGPU] Remove odd syntax in some RUN lines. NFC. (#169831)
2025-11-27 17:00:54 +00:00
fneg-combines.f16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fneg-combines.legal.f16.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
fneg-combines.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fneg-combines.new.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fneg-combines.si.ll
…
fneg-fabs-divergence-driven-isel.ll
…
fneg-fabs-r600.ll
…
fneg-fabs.bf16.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
fneg-fabs.f16.ll
AMDGPU: Ignore type legality in isFAbsFree (#177630)
2026-01-23 19:43:23 +01:00
fneg-fabs.f64.ll
…
fneg-fabs.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
fneg-fold-legalize-dag-increase-insts.ll
…
fneg-modifier-casting.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fneg.bf16.ll
[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (#165295)
2025-11-11 13:14:48 -06:00
fneg.f16.ll
…
fneg.f64.ll
…
fneg.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fold_acc_copy_into_valu.mir
…
fold-agpr-phis.mir
…
fold-cndmask-wave32.mir
…
fold-cndmask.mir
…
fold-commute-sgpr.mir
…
fold-fabs.ll
ValueTracking: Improve computeKnownFPClass fmul handling (#173247)
2025-12-24 22:17:58 +00:00
fold-fi-mubuf.mir
…
fold-fi-operand-shrink.mir
…
fold-fmaak-bug.ll
…
fold-fmul-to-neg-abs.ll
…
fold-freeze-fmul-to-fma.ll
…
fold-gep-offset.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
fold-imm-copy-agpr.mir
AMDGPU: Check if immediate is legal for av_mov_b32_imm_pseudo (#160819)
2025-09-27 08:24:20 +09:00
fold-imm-copy.mir
AMDGPU: Check if immediate is legal for av_mov_b32_imm_pseudo (#160819)
2025-09-27 08:24:20 +09:00
fold-imm-f16-f32.mir
…
fold-immediate-operand-shrink-with-carry.mir
…
fold-immediate-operand-shrink.mir
…
fold-immediate-output-mods.mir
…
fold-implicit-operand.mir
…
fold-int-pow2-with-fmul-or-fdiv.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
fold-literal-multiple-gfx10.mir
…
fold-multiple-commute.mir
…
fold-multiple.mir
…
fold-omod-crash.mir
…
fold-operands-frame-index-agpr.mir
AMDGPU: Check if immediate is legal for av_mov_b32_imm_pseudo (#160819)
2025-09-27 08:24:20 +09:00
fold-operands-frame-index.gfx10.mir
…
fold-operands-frame-index.mir
…
fold-operands-order.mir
…
fold-operands-remove-m0-redef.mir
…
fold-operands-s-add-copy-to-vgpr.mir
…
fold-operands-scalar-fmac.mir
…
fold-over-exec.mir
…
fold-readlane.mir
…
fold-reload-into-exec.mir
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
fold-reload-into-m0.mir
…
fold-restore-undef-use.mir
…
fold-sgpr-copy.mir
AMDGPU: Relax legal register operand constraint (#157989)
2025-09-12 08:57:47 +09:00
fold-sgpr-multi-imm.mir
…
fold-short-64-bit-literals.mir
…
fold-vgpr-copy.mir
…
fold-vgpr-phyreg.mir
…
fold-zero-high-bits-clear-kill-flags.mir
…
fold-zero-high-bits-skips-non-reg.mir
…
folding-of-i32-as-i64.mir
…
force-alwaysinline-lds-global-address-codegen.ll
…
force-alwaysinline-lds-global-address.ll
…
force-wait-after-always-gds.mir
…
fp32_to_fp16.ll
…
fp64-atomics-gfx90a.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
fp64-min-max-buffer-atomics.ll
…
fp64-min-max-buffer-ptr-atomics.ll
…
fp_to_sint.f64.ll
…
fp_to_sint.ll
[AMDGPU] Implement codegen for GFX11+ V_CVT_PK_[IU]16_F32 (#168719)
2025-12-10 22:26:59 +00:00
fp_to_uint.f64.ll
…
fp_to_uint.ll
[AMDGPU] Implement codegen for GFX11+ V_CVT_PK_[IU]16_F32 (#168719)
2025-12-10 22:26:59 +00:00
fp_trunc_store_fp32_to_bf16.ll
AMDGPU: Fix truncstore from v6f32 to v6f16 (#171212)
2025-12-08 22:46:36 +00:00
fp_trunc_store_fp64_to_bf16.ll
…
fp-atomic-to-s_denormmode.mir
…
fp-atomics-gfx942.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
fp-atomics-gfx950.ll
…
fp-atomics-gfx1200.ll
…
fp-classify.ll
AMDGPU: Ignore type legality in isFAbsFree (#177630)
2026-01-23 19:43:23 +01:00
fp-min-max-buffer-atomics.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
fp-min-max-buffer-ptr-atomics.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
fp-min-max-image-atomics.ll
…
fp-min-max-num-flat-atomics.ll
…
fp-min-max-num-global-atomics.ll
…
fp-to-int-to-fp.ll
[DAGCombiner] Extend fp->int->fp optimizations to include clamping (#164502)
2025-12-23 20:26:40 +02:00
fpenv.ll
…
fpext-free.ll
…
fpext.f16.ll
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
fpext.ll
…
fpow.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fptoi.i128.ll
Revert "SelectionDAG: Do not propagate divergence through glue (#174766)"
2026-01-07 14:23:15 +00:00
fptosi.f16.ll
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
fptoui_uitofp.ll
[DAGCombiner] Extend FP-to-Int cast without requiring nsz (#161093)
2025-10-11 00:34:33 +09:00
fptoui.f16.ll
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
fptrunc.f16.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
fptrunc.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPTRUNC (#171723)
2025-12-18 13:16:46 -08:00
fptrunc.v2f16.no.fast.math.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPTRUNC (#171723)
2025-12-18 13:16:46 -08:00
fract-match.ll
AMDGPU: Ignore type legality in isFAbsFree (#177630)
2026-01-23 19:43:23 +01:00
fract.f64.ll
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
fract.ll
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
frame-index-elimination-tied-operand.mir
…
frame-index-elimination.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
frame-index.mir
…
frame-lowering-entry-all-sgpr-used.mir
…
frame-lowering-fp-adjusted.mir
…
frame-setup-without-sgpr-to-vgpr-spills.ll
…
freeze-binary.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
freeze.ll
AMDGPU/GlobalISel: Regbanklegalize for G_CONCAT_VECTORS (#171471)
2025-12-15 10:37:40 +01:00
frem.ll
AMDGPU: Ignore type legality in isFAbsFree (#177630)
2026-01-23 19:43:23 +01:00
frexp-constant-fold.ll
…
fshl.ll
[AMDGPU] Invert scc uses to delete s_cmp_eq* (#167382)
2026-01-14 10:24:24 -06:00
fshr.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
fsqrt.f32.ll
AMDGPU: Teach lowering that sqrt never returns subnormal (#174838)
2026-01-08 12:05:29 +01:00
fsqrt.f64.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
fsqrt.r600.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
fsub64.ll
…
fsub-as-fneg-src-modifier.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FSUB (#171244)
2025-12-11 11:55:28 -08:00
fsub.f16.ll
…
fsub.ll
[DAGCombiner] Remove NoSignedZerosFPMath in visitFNEG (#162052)
2025-10-08 17:01:47 +08:00
ftrunc.f64.ll
…
ftrunc.ll
…
function-args-inreg.ll
…
function-args.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
function-call-relocs.ll
…
function-esm2-prologue-epilogue.ll
[AMDGPU] Add support for GFX12 expert scheduling mode 2 (#170319)
2026-01-09 15:49:10 +00:00
function-resource-usage.ll
[AMDGPU] Emit amdgpu.max_num_named_barrier resource symbol (#169851)
2025-12-04 12:48:23 -08:00
function-returns.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fused-bitlogic.ll
…
gcn-reg-pressure-true16-integer-overflow.mir
…
gds-allocation.ll
…
gds-atomic.ll
…
gds-unsupported.ll
…
generic-targets-require-v6.ll
…
gep-address-space.ll
…
gep-const-address-space.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
gep-flags-stack-offsets.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
gfx10-twoaddr-fma.mir
…
gfx10-vop-literal.ll
…
gfx10plus-wavefront-sgpr-count.ll
[AMDGPU] Set GRANULATED_WAVEFRONT_SGPR_COUNT of compute_pgm_rsrc1 to 0 for gfx10+ (#154666)
2025-08-27 09:48:42 +08:00
gfx11-twoaddr-fma.mir
…
gfx11-user-sgpr-init16-bug.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
gfx12_scalar_subword_loads.ll
…
gfx90a-enc.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
gfx902-without-xnack.ll
…
gfx942-hazards.mir
…
gfx-call-non-gfx-func.ll
…
gfx-callable-argument-types.ll
[AMDGPU] Latency calculation must be independent of meta insts (#177052)
2026-01-21 12:19:55 -06:00
gfx-callable-preserved-registers.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
gfx-callable-return-types.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
global_atomic_optimizer_fp_rtn.ll
…
global_atomics_i32_system.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
global_atomics_i64_system.ll
PeepholeOpt: Fix losing subregister indexes on full copies (#161310)
2025-10-02 13:36:47 +09:00
global_atomics_i64.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
global_atomics_iterative_scan_fp.ll
…
global_atomics_iterative_scan.ll
…
global_atomics_optimizer_fp_no_rtn.ll
…
global_atomics_scan_fadd.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
global_atomics_scan_fmax.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
global_atomics_scan_fmin.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
global_atomics_scan_fsub.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
global_atomics.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
global_smrd_cfg.ll
…
global_smrd.ll
…
global-address.ll
[AMDGPU] Remove odd syntax in some RUN lines. NFC. (#169831)
2025-11-27 17:00:54 +00:00
global-alias.ll
…
global-atomic-fadd.f32-no-rtn.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
global-atomic-fadd.f32-rtn.ll
AMDGPU: Start to use AV classes for unknown vector class (#166482)
2025-11-13 09:28:33 -08:00
global-atomic-fadd.f64.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
global-atomic-fadd.v2f16-no-rtn.ll
…
global-atomic-fadd.v2f16-rtn.ll
…
global-atomic-scan.ll
…
global-atomicrmw-fadd-wrong-subtarget.ll
…
global-atomicrmw-fadd.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
global-atomicrmw-fmax.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
global-atomicrmw-fmin.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
global-atomicrmw-fsub.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
global-atomics-fp-wrong-subtarget.ll
…
global-constant.ll
AMDGPU: Use ELF mangling in data layout (#163011)
2025-10-13 03:01:45 +00:00
global-directive.ll
…
global-extload-gfx11plus.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
global-extload-i16.ll
…
global-i16-load-store.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
global-load-saddr-to-vaddr.ll
…
global-load-xcnt.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
global-saddr-atomics-min-max-system.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
global-saddr-atomics.gfx908.ll
…
global-saddr-atomics.gfx1030.ll
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
2025-12-05 12:37:33 +00:00
global-saddr-atomics.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
global-saddr-load.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
global-saddr-store.ll
…
global-smrd-unknown.ll
…
global-variable-relocs.ll
AMDGPU: Use ELF mangling in data layout (#163011)
2025-10-13 03:01:45 +00:00
greedy-alloc-fail-sgpr1024-spill.mir
…
greedy-broken-ssa-verifier-error.mir
…
greedy-global-heuristic.mir
…
greedy-instruction-split-subrange.mir
…
greedy-liverange-priority.mir
…
greedy-remark-crash-unassigned-reg.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
greedy-reverse-local-assignment.ll
…
group-image-instructions.ll
…
gv-const-addrspace.ll
…
gv-offset-folding.ll
…
gws_agpr.ll
AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)
2025-11-25 18:55:34 +00:00
gws-hazards.mir
…
half-alloca-promotion.ll
…
half.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
hard-clause-limit-attr.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clause-limit.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clauses-gfx1250.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clauses-img-gfx10.mir
…
hard-clauses-img-gfx11.mir
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
hard-clauses-img-gfx12.mir
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
hard-clauses-load-monitor.mir
[AMDGPU] Update hard-clauses-load-monitor.mir. NFC (#157546)
2025-09-08 16:19:10 -07:00
hard-clauses.mir
[MachineStripDebug] Remove debug instructions from inside bundles (#160297)
2025-09-25 09:40:54 +01:00
hazard-buffer-store-v-interp.mir
…
hazard-flat-instruction-valu-check.mir
…
hazard-getreg-waitalu.mir
[AMDGPU] Handle S_GETREG_B32 hazard on gfx1250 (#153848)
2025-08-15 11:38:22 -07:00
hazard-gfx1250-flat-scr-hi.mir
[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC (#170396)
2025-12-03 00:14:32 -08:00
hazard-hidden-bundle.mir
…
hazard-in-bundle.mir
…
hazard-inlineasm.mir
…
hazard-kill.mir
…
hazard-lds-addtid.mir
…
hazard-pass-ordering.mir
…
hazard-pseudo-machineinstrs.mir
…
hazard-recognizer-meta-insts.mir
…
hazard-recognizer-src-shared-base.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
hazard-shift64.mir
[AMDGPU] Generate more efficient code to avoid shift64 hazard (#171871)
2026-01-05 09:19:15 -06:00
hazard.mir
…
hazards-gfx950.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
hazards-gfx1250.mir
[AMDGPU][GCNHazardRecognizer] Remove instances of hardcoded S_WAITCNT_DEPCTR operand values (#171811)
2025-12-11 13:26:54 +00:00
high-bits-zeroed-16-bit-ops.mir
…
high-RP-reschedule.mir
…
hip.extern.shared.array.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
hoist-cond.ll
…
hsa-default-device.ll
…
hsa-fp-mode.ll
…
hsa-func-align.ll
…
hsa-func.ll
…
hsa-generic-target-features.ll
…
hsa-globals.ll
…
hsa-group-segment.ll
…
hsa-metadata-agpr-register-count.ll
…
hsa-metadata-agpr-small.ll
…
hsa-metadata-deduced-arg-attr.ll
…
hsa-metadata-dynlds-func-hidden-args-v5.ll
…
hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
…
hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
…
hsa-metadata-enqueue-kernel-.ll
…
hsa-metadata-from-llvm-ctor-dtor-list.ll
…
hsa-metadata-from-llvm-ir-full.ll
…
hsa-metadata-heap-v5.ll
…
hsa-metadata-hidden-args-v4.ll
…
hsa-metadata-hidden-args-v5.ll
…
hsa-metadata-hostcall-present-asan.ll
…
hsa-metadata-hostcall-v4.ll
…
hsa-metadata-hostcall-v5.ll
…
hsa-metadata-images.ll
…
hsa-metadata-invalid-ocl-version-1.ll
…
hsa-metadata-invalid-ocl-version-3.ll
…
hsa-metadata-kernel-code-props.ll
…
hsa-metadata-multigrid-sync-arg-v5.ll
…
hsa-metadata-queue-ptr-v4.ll
…
hsa-metadata-queue-ptr-v5.ll
…
hsa-metadata-queueptr-v5.ll
…
hsa-metadata-resource-usage-function-ordering.ll
…
hsa-metadata-uniform-workgroup-size-v5.ll
…
hsa-metadata-wavefrontsize.ll
…
hsa-metadata-workgroup-processor-mode-v5.ll
…
hsa-note-no-func.ll
…
hsa.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
huge-number-operand-folds.mir
…
huge-private-buffer.ll
…
i1_copy_phi_with_phi_incoming_value.mir
…
i1-copies-rpo.mir
…
i1-copy-from-loop.ll
…
i1-copy-implicit-def.ll
…
i1-copy-phi-uniform-branch.ll
…
i1-copy-phi.ll
…
i1-divergent-phi-fix-sgpr-copies-assert.mir
…
i1-to-bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
i8-to-double-to-float.ll
…
icmp64.ll
…
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
…
idemponent-atomics.ll
AtomicExpand: Use LibcallLoweringInfo analysis (#176384)
2026-01-18 07:12:41 +01:00
identical-subrange-spill-infloop.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
idiv-licm.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
idot2.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
idot4s.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
idot4u.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
idot8s.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
idot8u.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
iglp-no-clobber.ll
[AMDGPU] Add the support for 45-bit buffer resource (#159702)
2025-09-24 11:12:02 -04:00
iglp.opt.reentry.ll
…
illegal-eviction-assert.mir
…
illegal-sgpr-to-vgpr-copy.ll
…
image-attributes.ll
…
image-load-d16-tfe.ll
…
image-resource-id.ll
…
image-sample-waterfall.ll
…
image-schedule.ll
…
img-nouse-adjust.ll
…
imm16.ll
[AMDGPU] Allow 16-bit imm folding in real true16 (#173318)
2026-01-15 11:15:12 -08:00
imm.ll
Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)
2025-09-23 17:36:02 +01:00
immv216.ll
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
implicit-arg-block-count.ll
[AMDGPU] Optimize block count calculations to the new ABI (#174112)
2026-01-08 16:03:00 -06:00
implicit-arg-v5-opt.ll
…
implicit-def-muse.ll
…
implicit-kernarg-backend-usage.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
implicit-kernel-argument-alignment.ll
…
implicitarg-attributes.ll
…
implicitarg-offset-attributes.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
indirect-addressing-si-gfx9.ll
…
indirect-addressing-si.ll
AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 (#168166)
2025-11-14 20:19:24 -08:00
indirect-addressing-term.ll
…
indirect-call-known-callees.ll
…
indirect-call-set-from-other-function.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
indirect-call.ll
…
indirect-private-64.ll
…
infer-addrpace-pipeline.ll
…
infer-addrspace-flat-atomic.ll
[AMDGPU][SDAG] Only fold flat offsets if they are inbounds PTRADDs (#165427)
2025-11-19 11:48:12 +01:00
infer-uniform-load-shader.ll
…
infinite-loop-evergreen.ll
…
infinite-loop.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
inflate-av-remat-imm.mir
AMDGPU: Add pseudoinstruction for 64-bit agpr or vgpr constants (#154499)
2025-08-20 22:54:37 +09:00
inflate-reg-class-vgpr-mfma-to-agpr-negative-tests.mir
AMDGPU: Handle rewriting VGPR MFMA to AGPR with subregister copies (#153019)
2025-08-21 01:17:03 +00:00
inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
inflate-reg-class-vgpr-mfma-to-av.mir
…
inflated-reg-class-snippet-copy-use-after-free.mir
…
infloop-subrange-spill-inspect-subrange.mir
…
infloop-subrange-spill.mir
…
init-whole-wave-vgpr-count-large.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
init-whole-wave-vgpr-count-leaf.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
init-whole-wave-vgpr-count-use-inactive.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
init-whole-wave-vgpr-count.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
inline-asm-av-constraint-err.ll
AMDGPU: Add new VA inline asm constraint for AV registers (#152665)
2025-08-12 10:17:28 +09:00
inline-asm-av-constraint.ll
AMDGPU: Add new VA inline asm constraint for AV registers (#152665)
2025-08-12 10:17:28 +09:00
inline-asm-out-of-bounds-register.ll
[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)
2025-09-03 16:25:18 -07:00
inline-asm-reserved-regs.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inline-asm.i128.ll
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
inline-asm.ll
…
inline-attr.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
inline-calls.ll
…
inline-constraints.ll
…
inline-maxbb.ll
…
inlineasm-16-fake16.ll
…
inlineasm-16-true16.ll
…
inlineasm-16.ll
…
inlineasm-illegal-type.ll
[AMDGPU] Fix crash for inline-asm inputs of type MVT::Other (#153425)
2025-08-13 17:27:31 +02:00
inlineasm-mismatched-size-error.ll
[AMDGPU] Fix a crash when a bool variable is used in inline asm (#171004)
2025-12-08 14:44:21 -05:00
inlineasm-mismatched-size.ll
…
inlineasm-packed.ll
…
inlineasm-sgmask.ll
Try To Guess SGMasks for Inline Asm Instructions (#155491)
2026-01-23 12:43:53 -06:00
inlineasm-v16.ll
…
InlineAsmCrash.ll
…
input-mods.r600.ll
…
insert_subreg.ll
…
insert_vector_dynelt.ll
Reapply "[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#170323) (#171838)
2025-12-15 09:05:00 +01:00
insert_vector_elt.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
insert_vector_elt.v2bf16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
insert_vector_elt.v2i16.ll
[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (#165295)
2025-11-11 13:14:48 -06:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
…
insert_vector_elt.v2i16.subtest-saddr.ll
…
insert_waitcnt_for_precise_memory.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
insert-branch-w32.mir
…
insert-delay-alu-bug.ll
[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)
2025-10-22 08:42:29 -05:00
insert-delay-alu-literal.mir
…
insert-delay-alu-parse.mir
…
insert-delay-alu-wmma-xdl.mir
…
insert-delay-alu.mir
…
insert-handle-flat-vmem-ds.mir
…
insert-skip-from-vcc.mir
AMDGPU: Fix assert when looking for s_and_b64 + vcc branch pattern (#177031)
2026-01-20 22:23:52 +00:00
insert-skips-gfx10.mir
…
insert-skips-gfx12.mir
[AMDGPU] Add s_barrier_init|join|leave instructions (#153296)
2025-08-12 15:07:07 -07:00
insert-skips-gws.mir
…
insert-skips-ignored-insts.mir
…
insert-subvector-unused-scratch.ll
…
insert-waitcnts-callee.mir
…
insert-waitcnts-crash.ll
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
insert-waitcnts-exp.mir
…
insert-waitcnts-fence-soft.mir
…
insert-waitcnts-gfx12-wbinv.mir
…
insert-waitcnts-hang.mir
…
insert-waitcnts-merge.ll
(reland) [AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077) (#171779)
2025-12-12 09:41:04 +01:00
inserted-wait-states.mir
…
inst-prefetch-hint.ll
…
integer-canonicalizing-src-modifiers.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
integer-mad-patterns.ll
Reland "[AMDGPU][GlobalISel] Add RegBankLegalize support for G_MUL (#… (#177481)
2026-01-22 14:59:52 -08:00
integer-select-src-modifiers.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
internalize.ll
…
invalid-addrspacecast.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
invalid-cast-load-i1.ll
…
invalid-hidden-kernarg-in-kernel-signature.ll
…
invalid-inline-asm-constraint-crash.ll
…
invariant-image-load.ll
…
invariant-load-no-alias-store.ll
AMDGPU: Handle invariant loads when considering if a load can be scalar (#168787)
2025-11-20 13:07:23 -05:00
invert-br-undef-vcc.mir
…
ipra-regmask.ll
[CodeGen][NPM] Add support for -print-regusage in New Pass Manager (#169761)
2026-01-14 11:00:02 +05:30
ipra-return-address-save-restore.ll
…
ipra.ll
…
irtranslator-whole-wave-functions.ll
Reapply "[AMDGPU] Intrinsic for launching whole wave functions" (#153584)
2025-08-15 10:12:47 +02:00
isel-amdgcn-cs-chain-intrinsic-w32.ll
[AMDGPU] Relax restrictions on amdgcn.cs.chain intrinsic (#169785)
2025-12-10 11:12:46 +01:00
isel-amdgcn-cs-chain-intrinsic-w64.ll
[AMDGPU] Allow any SGPRs for chain callees (#168345)
2025-12-02 09:44:35 +01:00
isel-amdgpu-cs-chain-cc.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
[AMDGPU] Allow any SGPRs for chain callees (#168345)
2025-12-02 09:44:35 +01:00
isel-amdgpu-cs-chain-preserve-cc.ll
AMDGPU/GlobalISel: Regbanklegalize for G_CONCAT_VECTORS (#171471)
2025-12-15 10:37:40 +01:00
isel-whole-wave-functions.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
issue48473.mir
…
issue92561-restore-undef-scc-verifier-error.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
issue98474-assigned-physreg-interference.mir
…
issue98474-need-live-out-undef-subregister-def.ll
…
issue98474-virtregrewriter-live-out-undef-subregisters.mir
…
issue120256-annotate-constexpr-addrspacecast.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
issue121601-combine-concat-vectors-assumes-f16.ll
…
issue130120-eliminate-frame-index.ll
…
issue139317-bad-opsel-reg-sequence-fold.ll
…
issue153808-extract-subvector-legalize.ll
DAG: Handle half spanning extract_subvector in type legalization (#154101)
2025-08-21 00:05:12 +00:00
issue176578.ll
AMDGPU: Fix assert when looking for s_and_b64 + vcc branch pattern (#177031)
2026-01-20 22:23:52 +00:00
issue176966-extend-vector-inreg.ll
Fix EXTEND_VECTOR_INREG widening when input > result size (#177095)
2026-01-22 09:33:46 +01:00
itofp.i128.bf.ll
[CodeGen] Rename expand-fp to expand-ir-insts (#172681)
2025-12-18 11:15:04 +00:00
itofp.i128.ll
[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)
2025-10-24 17:25:00 +02:00
jump-address.ll
…
kcache-fold.ll
…
kernarg-size.ll
…
kernarg-stack-alignment.ll
…
kernel_code_t_recurse.ll
…
kernel-args.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
kernel-argument-dag-lowering.ll
[AMDGPU] kernel-argument-dag-lowering.ll - regenerate test coverage (#159526)
2025-09-18 09:34:38 +00:00
kernel-mubuf-with-voffset.mir
…
kernel-vgpr-spill-mubuf-with-voffset.ll
…
kill-infinite-loop.ll
…
kill-true-in-return-block.ll
…
known-never-nan.ll
…
known-never-snan.ll
…
knownbits-recursion.ll
…
large-alloca-compute.ll
…
large-alloca-graphics.ll
…
large-avgpr-assign-last.mir
…
large-constant-initializer.ll
…
large-work-group-promote-alloca.ll
…
lcssa-optnone.ll
…
lds-alignment.ll
…
lds-bounds.ll
…
lds-branch-vmem-hazard.mir
[AMDGPU] Consider FLAT instructions for VMEM hazard detection (#137170)
2025-11-18 18:41:04 +01:00
lds-direct-hazards-gfx11.mir
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
lds-direct-hazards-gfx12.mir
…
lds-dma-hazards.mir
…
lds-dma-waitcnt.mir
…
lds-dma-waits.ll
(reland) [AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077) (#171779)
2025-12-12 09:41:04 +01:00
lds-dma-workgroup-release.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
lds-frame-extern.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
lds-global-non-entry-func.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for amd_gcn_end_cf (#175118)
2026-01-13 18:18:39 +05:30
lds-initializer.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
lds-limit-diagnostics-gfx1250.ll
[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)
2025-08-14 12:52:00 -07:00
lds-limit-diagnostics.ll
…
lds-m0-init-in-loop.ll
…
lds-misaligned-bug.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
lds-mixed-absolute-addresses-unused.ll
…
lds-mixed-absolute-dynlds.ll
…
lds-no-realign-allocated-variables.ll
…
lds-oqap-crash.ll
…
lds-output-queue.ll
…
lds-reject-anonymous-kernels.ll
…
lds-reject-mixed-absolute-addresses.ll
…
lds-relocs.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
lds-run-twice-absolute-md.ll
[AIX] Fix AIX failures due to switch to internal shell (#160566)
2025-09-24 14:11:44 -04:00
lds-run-twice.ll
[AIX] Fix AIX failures due to switch to internal shell (#160566)
2025-09-24 14:11:44 -04:00
lds-size-hsa-gfx950.ll
…
lds-size-hsa-gfx1250.ll
[AMDGPU] update LDS block size for gfx1250 (#167614)
2025-11-17 16:03:47 -08:00
lds-size-pal-gfx950.ll
…
lds-size-pal-gfx1250.ll
[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)
2025-08-14 12:52:00 -07:00
lds-size-pal-metadata.ll
[AMDGPU] Fix hw stage metadata setting for unsigned values (#154502)
2025-09-02 10:42:11 +02:00
lds-size.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
lds-zero-initializer.ll
…
legalize-amdgcn.dead.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.load.format.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.load.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.store.format.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.buffer.store.format.f32.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.buffer.store.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.load.format.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.load.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.store.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.tbuffer.load.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.tbuffer.store.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.tbuffer.load.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.tbuffer.store.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.tbuffer.store.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-fp-load-invariant.ll
…
legalize-soffset-mbuf.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalizedag-bug-expand-setcc.ll
…
licm-regpressure.mir
…
licm-valu.mir
…
licm-wwm.mir
…
limit-soft-clause-reg-pressure.mir
…
lit.local.cfg
…
literal64.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
literal-constant-like-operand-instruction-size.ll
…
literals.ll
…
live-interval-bug-in-rename-independent-subregs.mir
RenameIndependentSubregs: try to only implicit def used subregs (#167486)
2025-11-20 09:28:34 +09:00
liveness.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
liveout-implicit-def-subreg-redef-blender-verifier-error.mir
…
livevars-implicitdef.mir
[LiveVariables] Mark use without implicit if defined at instr (#119446)
2025-08-18 08:34:59 -04:00
llc-pipeline-npm.ll
[CodeGen][NPM] Specify Loop pass adaptor to not use MSSA (#176690)
2026-01-24 09:08:44 +05:30
llc-pipeline.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
llvm.amdgcn.add.min.max.ll
[AMDGPU] Add intrinsics for v_[pk]_add_{min|max}_* instructions (#164731)
2025-10-22 17:46:33 -07:00
llvm.amdgcn.addrspacecast.nonnull.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
llvm.amdgcn.alignbyte.ll
…
llvm.amdgcn.atomic.dec.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
llvm.amdgcn.atomic.inc.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU] Support bfloat comparison for ballot intrinsic (#165495)
2025-10-30 09:44:25 -07:00
llvm.amdgcn.ballot.i64.ll
[AMDGPU] Support bfloat comparison for ballot intrinsic (#165495)
2025-10-30 09:44:25 -07:00
llvm.amdgcn.ballot.i64.wave32.ll
…
llvm.amdgcn.bitop3.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.bitreplicate.ll
…
llvm.amdgcn.buffer.load-last-use.ll
…
llvm.amdgcn.buffer.load.dwordx3.ll
…
llvm.amdgcn.buffer.load.lds.err.ll
…
llvm.amdgcn.buffer.store.dwordx3.ll
…
llvm.amdgcn.bvh8_intersect_ray.ll
…
llvm.amdgcn.class.f16.ll
…
llvm.amdgcn.class.ll
…
llvm.amdgcn.cluster.id.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cluster.load.async.to.lds.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cluster.load.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cluster.workgroup.id.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cluster.workgroup.max.flat.id.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cluster.workgroup.max.id.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cooperative.atomic-agent.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
llvm.amdgcn.cooperative.atomic-basic.ll
[AMDGPU] Add gfx1251 runlines to cooperative atomcis tests. NFC (#159437)
2025-09-17 14:08:05 -07:00
llvm.amdgcn.cooperative.atomic-singlethread.ll
[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)
2025-09-04 09:19:25 +00:00
llvm.amdgcn.cooperative.atomic-system.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
llvm.amdgcn.cooperative.atomic-wavefront.ll
[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)
2025-09-04 09:19:25 +00:00
llvm.amdgcn.cooperative.atomic-workgroup.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
llvm.amdgcn.cos.bf16.ll
…
llvm.amdgcn.cos.f16.ll
…
llvm.amdgcn.cos.ll
…
llvm.amdgcn.cubeid.ll
…
llvm.amdgcn.cubema.ll
…
llvm.amdgcn.cubesc.ll
…
llvm.amdgcn.cubetc.ll
…
llvm.amdgcn.cvt.f16.fp8.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.f32.fp8.err.ll
…
llvm.amdgcn.cvt.fp8.dpp.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.fp8.dpp.mir
…
llvm.amdgcn.cvt.fp8.e5m3.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.fp8.f16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.fp8.ll
…
llvm.amdgcn.cvt.off.f32.i4.ll
…
llvm.amdgcn.cvt.pk.f16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.pk.i16.ll
…
llvm.amdgcn.cvt.pk.u16.ll
…
llvm.amdgcn.cvt.pknorm.i16.ll
…
llvm.amdgcn.cvt.pknorm.u16.ll
…
llvm.amdgcn.cvt.pkrtz.ll
…
llvm.amdgcn.cvt.sat.pk.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.scale.pk.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.scalef32.pk8.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
…
llvm.amdgcn.cvt.scalef32.pk.ll
…
llvm.amdgcn.cvt.scalef32.sr.ll
…
llvm.amdgcn.cvt.scalef32.sr.pk16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
…
llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cvt.scalef32.sr.pk.ll
…
llvm.amdgcn.cvt.sr.ll
…
llvm.amdgcn.cvt.sr.pk.bf16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.dead.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.dispatch.id.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
llvm.amdgcn.dispatch.ptr.ll
…
llvm.amdgcn.div.fixup.f16.ll
…
llvm.amdgcn.div.fixup.ll
…
llvm.amdgcn.div.fmas.ll
[AMDGPU] Update codegen tests for PR #154069 (#154862)
2025-08-22 07:58:21 -06:00
llvm.amdgcn.div.scale.ll
…
llvm.amdgcn.dot4.f32.ll
…
llvm.amdgcn.ds.add.gs.reg.rtn.ll
…
llvm.amdgcn.ds.append.ll
…
llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
…
llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
…
llvm.amdgcn.ds.bpermute.fi.b32.ll
…
llvm.amdgcn.ds.bpermute.ll
…
llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
…
llvm.amdgcn.ds.bvh.stack.rtn.ll
…
llvm.amdgcn.ds.consume.ll
…
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
llvm.amdgcn.ds.gws.barrier.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
llvm.amdgcn.ds.gws.init.ll
…
llvm.amdgcn.ds.gws.sema.br.ll
…
llvm.amdgcn.ds.gws.sema.p.ll
…
llvm.amdgcn.ds.gws.sema.release.all.ll
…
llvm.amdgcn.ds.gws.sema.v.ll
…
llvm.amdgcn.ds.ordered.add-errors.ll
…
llvm.amdgcn.ds.ordered.add-unsupported.ll
…
llvm.amdgcn.ds.ordered.add.gfx10.ll
…
llvm.amdgcn.ds.ordered.add.gfx11.ll
[AMDGPU] TableGen-erate SDNode descriptions (#168248)
2025-11-17 00:10:07 +00:00
llvm.amdgcn.ds.ordered.add.ll
…
llvm.amdgcn.ds.ordered.swap.ll
…
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.read.tr.gfx950.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
llvm.amdgcn.ds.sub.gs.reg.rtn.ll
…
llvm.amdgcn.ds.swizzle.ll
…
llvm.amdgcn.dual_intersect_ray.ll
…
llvm.amdgcn.exp2.ll
…
llvm.amdgcn.exp.bf16.ll
…
llvm.amdgcn.exp.compr.ll
…
llvm.amdgcn.exp.ll
…
llvm.amdgcn.exp.prim.ll
…
llvm.amdgcn.exp.row.ll
…
llvm.amdgcn.fcmp.w32.ll
…
llvm.amdgcn.fcmp.w64.ll
…
llvm.amdgcn.fdiv.fast.ll
…
llvm.amdgcn.fdot2.bf16.bf16.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
llvm.amdgcn.fdot2.f16.f16.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
llvm.amdgcn.fdot2.f32.bf16.ll
…
llvm.amdgcn.fdot2.ll
…
llvm.amdgcn.flat.prefetch.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.fma.legacy.ll
[AMDGPU] Do not generate V_FMAC_DX9_ZERO_F32 on GFX12 (#171116)
2025-12-08 13:20:02 +00:00
llvm.amdgcn.fmad.ftz.f16.ll
…
llvm.amdgcn.fmad.ftz.ll
…
llvm.amdgcn.fmed3.f16.ll
…
llvm.amdgcn.fmed3.ll
…
llvm.amdgcn.fmul.legacy.ll
…
llvm.amdgcn.fract.f16.ll
…
llvm.amdgcn.fract.ll
…
llvm.amdgcn.frexp.exp.f16.ll
…
llvm.amdgcn.frexp.exp.ll
…
llvm.amdgcn.frexp.mant.f16.ll
…
llvm.amdgcn.frexp.mant.ll
…
llvm.amdgcn.global.atomic.csub.ll
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
2025-12-05 12:37:33 +00:00
llvm.amdgcn.global.atomic.ordered.add.b64.ll
…
llvm.amdgcn.global.load.async.to.lds.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.global.load.lds.err.ll
…
llvm.amdgcn.global.load.lds.gfx950.ll
…
llvm.amdgcn.global.load.lds.ll
…
llvm.amdgcn.global.load.tr-w32.ll
…
llvm.amdgcn.global.load.tr-w64.ll
…
llvm.amdgcn.global.prefetch.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.global.store.async.from.lds.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.groupstaticsize.ll
…
llvm.amdgcn.icmp.w32.ll
…
llvm.amdgcn.icmp.w64.ll
…
llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
llvm.amdgcn.iglp.opt.exp.large.mir
[AMDGPU] Examine instructions in pending queues during scheduling (#147653)
2025-10-16 08:46:29 -07:00
llvm.amdgcn.iglp.opt.exp.simple.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.iglp.opt.exp.small.mir
…
llvm.amdgcn.iglp.opt.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.iglp.opt.single.2b.mir
…
llvm.amdgcn.iglp.opt.single.2c.mir
…
llvm.amdgcn.image.a16.dim.ll
…
llvm.amdgcn.image.a16.encode.ll
…
llvm.amdgcn.image.atomic.dim.gfx90a.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
llvm.amdgcn.image.atomic.dim.ll
…
llvm.amdgcn.image.atomic.flt.ll
…
llvm.amdgcn.image.atomic.noret.ll
[AMDGPU] Support image atomic no return instructions (#150742)
2025-10-29 10:42:15 +08:00
llvm.amdgcn.image.atomic.pk.add.ll
[AMDGPU] Support image atomic no return instructions (#150742)
2025-10-29 10:42:15 +08:00
llvm.amdgcn.image.d16.dim.ll
…
llvm.amdgcn.image.dim.gfx90a.ll
Greedy: Make eviction broken hint cost use CopyCost units (#160084)
2025-09-23 08:03:01 +09:00
llvm.amdgcn.image.dim.ll
…
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Regenerate test case to cover gfx10 check lines. (#154909)
2025-08-22 15:00:28 +05:30
llvm.amdgcn.image.gather4.d16.dim.ll
…
llvm.amdgcn.image.gather4.dim.ll
…
llvm.amdgcn.image.gather4.o.dim.ll
…
llvm.amdgcn.image.getlod.dim.ll
…
llvm.amdgcn.image.load.2dmsaa.ll
…
llvm.amdgcn.image.load.a16.d16.ll
…
llvm.amdgcn.image.load.a16.ll
…
llvm.amdgcn.image.msaa.load.ll
…
llvm.amdgcn.image.msaa.load.x.ll
…
llvm.amdgcn.image.nsa.ll
…
llvm.amdgcn.image.sample.a16.dim.ll
…
llvm.amdgcn.image.sample.cd.a16.dim.ll
…
llvm.amdgcn.image.sample.cd.dim.ll
…
llvm.amdgcn.image.sample.cd.g16.encode.ll
…
llvm.amdgcn.image.sample.cd.g16.ll
…
llvm.amdgcn.image.sample.d16.dim.ll
…
llvm.amdgcn.image.sample.dim.gfx90a.ll
…
llvm.amdgcn.image.sample.dim.ll
…
llvm.amdgcn.image.sample.g16.a16.dim.ll
…
llvm.amdgcn.image.sample.g16.encode.ll
…
llvm.amdgcn.image.sample.g16.ll
…
llvm.amdgcn.image.sample.noret.ll
…
llvm.amdgcn.image.sample.o.dim.ll
…
llvm.amdgcn.image.store.a16.d16.ll
…
llvm.amdgcn.image.store.a16.ll
…
llvm.amdgcn.implicit.ptr.buffer.hsa.ll
…
llvm.amdgcn.implicit.ptr.buffer.ll
…
llvm.amdgcn.implicitarg.ptr.ll
…
llvm.amdgcn.init.exec.ll
…
llvm.amdgcn.init.exec.wave32.ll
…
llvm.amdgcn.init.whole.wave-w32.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.init.whole.wave-w64.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.interp.f16.ll
…
llvm.amdgcn.interp.inreg.ll
AMDGPU: Replace copy-to-mov-imm folding logic with class compat checks (#154501)
2025-08-26 23:41:35 +09:00
llvm.amdgcn.interp.ll
…
llvm.amdgcn.intersect_ray.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.inverse.ballot.i32.ll
AMDGPU: llvm.amdgcn.inverse.ballot needs to be convergent (#155725)
2025-08-27 19:40:27 -07:00
llvm.amdgcn.inverse.ballot.i64.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.is.private.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.is.shared.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.kernarg.segment.ptr.ll
…
llvm.amdgcn.kill.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.lds.direct.load.ll
…
llvm.amdgcn.lds.kernel.id.ll
…
llvm.amdgcn.lds.param.load.ll
…
llvm.amdgcn.lerp.ll
[AMDGPU] Adding instruction specific features (#167809)
2025-11-19 11:06:00 +08:00
llvm.amdgcn.load.monitor.gfx1250.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.load.to.lds.gfx950.ll
…
llvm.amdgcn.load.to.lds.ll
[AMDGPU] Enable volatile and non-temporal for loads to LDS (#153244)
2025-10-20 12:42:22 -05:00
llvm.amdgcn.load.tr.gfx1250.w32.ll
[AMDGPU] Remove intrinsic declarations in a couple tests, NFC (#177218)
2026-01-21 12:16:26 -08:00
llvm.amdgcn.log.bf16.ll
…
llvm.amdgcn.log.clamp.ll
…
llvm.amdgcn.log.ll
…
llvm.amdgcn.make.buffer.rsrc.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
llvm.amdgcn.mbcnt.ll
…
llvm.amdgcn.mfma.bf16.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.form.ll
AMDGPU: Track minNumAGPRs in MFI instead of mayUseAGPRs (#161996)
2025-10-07 08:48:45 +09:00
llvm.amdgcn.mfma.gfx90a.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.gfx942.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.gfx950.bf16.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.gfx950.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.i8.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.xf32.gfx942.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mov.dpp8.ll
…
llvm.amdgcn.mov.dpp.gfx1251.ll
[AMDGPU] gfx1251 VOP1 dpp support (#159637)
2025-09-18 13:42:06 -07:00
llvm.amdgcn.mov.dpp.ll
…
llvm.amdgcn.mqsad.pk.u16.u8.ll
…
llvm.amdgcn.mqsad.u32.u8.ll
…
llvm.amdgcn.msad.u8.ll
…
llvm.amdgcn.mul.i24.ll
…
llvm.amdgcn.mul.u24.ll
…
llvm.amdgcn.mulhi.i24.ll
[AMDGPU][GlobalISel] Add RegBankLegalize mul24 and fmul.legacy (#173123)
2025-12-23 12:35:28 -08:00
llvm.amdgcn.mulhi.u24.ll
[AMDGPU][GlobalISel] Add RegBankLegalize mul24 and fmul.legacy (#173123)
2025-12-23 12:35:28 -08:00
llvm.amdgcn.perm.ll
…
llvm.amdgcn.perm.pk.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
llvm.amdgcn.permlane16.swap.ll
…
llvm.amdgcn.permlane16.var.ll
…
llvm.amdgcn.permlane32.swap.ll
…
llvm.amdgcn.permlane64.ll
[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)
2025-10-30 12:32:32 +05:30
llvm.amdgcn.permlane64.ptr.ll
[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)
2025-10-30 12:32:32 +05:30
llvm.amdgcn.permlane.gfx1250.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.permlane.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.permlane.ptr.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.pops.exiting.wave.id.ll
…
llvm.amdgcn.prng.ll
[AMDGPU] Combine prng(undef) -> undef (#154160)
2025-08-18 12:13:16 -07:00
llvm.amdgcn.ps.live.ll
…
llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
[AMDGPU] TableGen-erate SDNode descriptions (#168248)
2025-11-17 00:10:07 +00:00
llvm.amdgcn.qsad.pk.u16.u8.ll
…
llvm.amdgcn.quadmask.ll
[AMDGPU] s_quadmask* implicitly defines SCC (#161582)
2025-10-02 10:29:09 -05:00
llvm.amdgcn.queue.ptr.ll
…
llvm.amdgcn.raw.atomic.buffer.load.ll
[AMDGPU] Add regbankselect rules for G_ICMP/G_FCMP (#172048)
2026-01-14 12:37:16 -05:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
…
llvm.amdgcn.raw.buffer.atomic.ll
…
llvm.amdgcn.raw.buffer.load.format.d16.ll
…
llvm.amdgcn.raw.buffer.load.format.ll
…
llvm.amdgcn.raw.buffer.load.lds.ll
…
llvm.amdgcn.raw.buffer.load.ll
…
llvm.amdgcn.raw.buffer.load.tfe.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.raw.buffer.store.format.d16.ll
…
llvm.amdgcn.raw.buffer.store.format.ll
…
llvm.amdgcn.raw.buffer.store.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
[AMDGPU] Add regbankselect rules for G_ICMP/G_FCMP (#172048)
2026-01-14 12:37:16 -05:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
…
llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
…
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.raw.ptr.buffer.atomic.ll
…
llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.amdgcn.raw.ptr.buffer.load.bf16.xfail.ll
…
llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
…
llvm.amdgcn.raw.ptr.buffer.load.format.ll
…
llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
…
llvm.amdgcn.raw.ptr.buffer.load.lds.ll
[AMDGPU] Enable volatile and non-temporal for loads to LDS (#153244)
2025-10-20 12:42:22 -05:00
llvm.amdgcn.raw.ptr.buffer.load.ll
[AMDGPU] Enable volatile and non-temporal for loads to LDS (#153244)
2025-10-20 12:42:22 -05:00
llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.amdgcn.raw.ptr.buffer.store.bf16.xfail.ll
…
llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
…
llvm.amdgcn.raw.ptr.buffer.store.format.ll
…
llvm.amdgcn.raw.ptr.buffer.store.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
Reapply [IR] Remove options to make scalable TypeSize access a warning (#156336)
2025-09-03 11:12:11 +02:00
llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
…
llvm.amdgcn.raw.ptr.tbuffer.load.ll
…
llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
…
llvm.amdgcn.raw.ptr.tbuffer.store.ll
…
llvm.amdgcn.raw.tbuffer.load.d16.ll
…
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)
2025-09-30 07:56:23 -07:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
…
llvm.amdgcn.raw.tbuffer.store.ll
…
llvm.amdgcn.rcp.bf16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.rcp.f16.ll
…
llvm.amdgcn.rcp.legacy.ll
…
llvm.amdgcn.rcp.ll
…
llvm.amdgcn.readfirstlane.ll
[AMDGPU] Stop optimising readfirstlane in pass AMDGPUUniformIntrinsicCombine (#166955)
2025-11-08 01:17:39 +05:30
llvm.amdgcn.readfirstlane.m0.ll
…
llvm.amdgcn.readfirstlane.ptr.ll
…
llvm.amdgcn.readlane.ll
[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)
2025-10-30 12:32:32 +05:30
llvm.amdgcn.readlane.ptr.ll
…
llvm.amdgcn.reduce.add.ll
[NFC][AMDGPU] Refactor wave reduce test files (#170440)
2025-12-03 14:36:25 +05:30
llvm.amdgcn.reduce.and.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.fadd.ll
[NFC][AMDGPU] Refactor wave reduce test files (#170440)
2025-12-03 14:36:25 +05:30
llvm.amdgcn.reduce.fmax.ll
[NFC][AMDGPU] Refactor wave reduce test files (#170440)
2025-12-03 14:36:25 +05:30
llvm.amdgcn.reduce.fmin.ll
[NFC][AMDGPU] Refactor wave reduce test files (#170440)
2025-12-03 14:36:25 +05:30
llvm.amdgcn.reduce.fsub.ll
[NFC][AMDGPU] Refactor wave reduce test files (#170440)
2025-12-03 14:36:25 +05:30
llvm.amdgcn.reduce.max.ll
[NFC][AMDGPU] Refactor wave reduce test files (#170440)
2025-12-03 14:36:25 +05:30
llvm.amdgcn.reduce.min.ll
[NFC][AMDGPU] Refactor wave reduce test files (#170440)
2025-12-03 14:36:25 +05:30
llvm.amdgcn.reduce.or.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.sub.ll
[NFC][AMDGPU] Refactor wave reduce test files (#170440)
2025-12-03 14:36:25 +05:30
llvm.amdgcn.reduce.umax.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.umin.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.reduce.xor.ll
[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)
2025-09-10 20:13:30 +05:30
llvm.amdgcn.rsq.bf16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.rsq.f16.ll
…
llvm.amdgcn.rsq.legacy.ll
…
llvm.amdgcn.rsq.ll
…
llvm.amdgcn.s.barrier.ll
[AMDGPU] Schedule independent instructions between s_barrier_signal and s_barrier_wait (#172057)
2025-12-16 11:48:50 +05:30
llvm.amdgcn.s.barrier.signal.isfirst.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.s.barrier.signal.isfirst.mir
[AMDGPU][SIInsertWaitcnts] Track SCC. Insert KM_CNT waits for SCC writes. (#157843)
2025-09-18 14:41:01 +02:00
llvm.amdgcn.s.buffer.load.ll
…
llvm.amdgcn.s.buffer.prefetch.data.ll
…
llvm.amdgcn.s.dcache.inv.ll
…
llvm.amdgcn.s.dcache.inv.vol.ll
…
llvm.amdgcn.s.dcache.wb.ll
…
llvm.amdgcn.s.dcache.wb.vol.ll
…
llvm.amdgcn.s.decperflevel.ll
…
llvm.amdgcn.s.get.waveid.in.workgroup.ll
…
llvm.amdgcn.s.getpc.ll
…
llvm.amdgcn.s.getreg.ll
…
llvm.amdgcn.s.incperflevel.ll
…
llvm.amdgcn.s.memrealtime.ll
…
llvm.amdgcn.s.memtime.ll
…
llvm.amdgcn.s.monitor.sleep.ll
…
llvm.amdgcn.s.nop.ll
…
llvm.amdgcn.s.prefetch.data.ll
…
llvm.amdgcn.s.sethalt.ll
…
llvm.amdgcn.s.setprio.inc.wg.ll
…
llvm.amdgcn.s.setprio.ll
…
llvm.amdgcn.s.setreg.ll
…
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.s.sleep.var.ll
…
llvm.amdgcn.s.ttracedata.ll
…
llvm.amdgcn.s.wait.event.ll
…
llvm.amdgcn.s.wait.gfx12.ll
…
llvm.amdgcn.s.wait.gfx1250.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.s.waitcnt_gfx1250.ll
[AMDGPU] gfx1250 waitcnt related codegen tests update. NFC (#155317)
2025-08-25 15:23:59 -07:00
llvm.amdgcn.s.waitcnt.ll
…
llvm.amdgcn.sad.hi.u8.ll
…
llvm.amdgcn.sad.u8.ll
…
llvm.amdgcn.sad.u16.ll
…
llvm.amdgcn.sbfe.ll
…
llvm.amdgcn.sched.barrier.ll
…
llvm.amdgcn.sched.group.barrier.gfx11.ll
…
llvm.amdgcn.sched.group.barrier.gfx12.ll
…
llvm.amdgcn.sched.group.barrier.iterative.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.sched.group.barrier.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.sdot2.ll
…
llvm.amdgcn.sdot4.ll
…
llvm.amdgcn.sdot8.ll
…
llvm.amdgcn.sendmsg.ll
…
llvm.amdgcn.sendmsg.rtn.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.set.inactive.chain.arg.ll
…
llvm.amdgcn.set.inactive.ll
…
llvm.amdgcn.sffbh.ll
…
llvm.amdgcn.sin.bf16.ll
…
llvm.amdgcn.sin.f16.ll
…
llvm.amdgcn.sin.ll
…
llvm.amdgcn.smfmac.gfx950.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.softwqm.ll
…
llvm.amdgcn.sqrt.bf16.ll
…
llvm.amdgcn.sqrt.f16.ll
…
llvm.amdgcn.sqrt.ll
…
llvm.amdgcn.struct.atomic.buffer.load.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for amd_gcn_end_cf (#175118)
2026-01-13 18:18:39 +05:30
llvm.amdgcn.struct.buffer.atomic.fadd.ll
…
llvm.amdgcn.struct.buffer.atomic.ll
…
llvm.amdgcn.struct.buffer.load.format.d16.ll
…
llvm.amdgcn.struct.buffer.load.format.ll
…
llvm.amdgcn.struct.buffer.load.format.v3f16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.buffer.load.lds.ll
…
llvm.amdgcn.struct.buffer.load.ll
…
llvm.amdgcn.struct.buffer.load.tfe.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.struct.buffer.store.format.d16.ll
…
llvm.amdgcn.struct.buffer.store.format.ll
…
llvm.amdgcn.struct.buffer.store.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for amd_gcn_end_cf (#175118)
2026-01-13 18:18:39 +05:30
llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
…
llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
…
llvm.amdgcn.struct.ptr.buffer.atomic.ll
…
llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
…
llvm.amdgcn.struct.ptr.buffer.load.format.ll
…
llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
…
llvm.amdgcn.struct.ptr.buffer.load.lds.ll
…
llvm.amdgcn.struct.ptr.buffer.load.ll
…
llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
…
llvm.amdgcn.struct.ptr.buffer.store.format.ll
…
llvm.amdgcn.struct.ptr.buffer.store.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
…
llvm.amdgcn.struct.ptr.tbuffer.load.ll
…
llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
…
llvm.amdgcn.struct.ptr.tbuffer.store.ll
…
llvm.amdgcn.struct.tbuffer.load.d16.ll
…
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)
2025-09-30 07:56:23 -07:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
…
llvm.amdgcn.struct.tbuffer.store.ll
…
llvm.amdgcn.sudot4.ll
…
llvm.amdgcn.sudot8.ll
…
llvm.amdgcn.tanh.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.tbuffer.load.dwordx3.ll
…
llvm.amdgcn.tbuffer.store.dwordx3.ll
…
llvm.amdgcn.tensor.load.store.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.trig.preop.ll
…
llvm.amdgcn.ubfe.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
llvm.amdgcn.udot2.ll
…
llvm.amdgcn.udot4.ll
…
llvm.amdgcn.udot8.ll
…
llvm.amdgcn.unreachable.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
llvm.amdgcn.update.dpp.gfx90a.ll
…
llvm.amdgcn.update.dpp.ll
AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 (#168166)
2025-11-14 20:19:24 -08:00
llvm.amdgcn.waitcnt.out.order.ll
…
llvm.amdgcn.wave.barrier.ll
…
llvm.amdgcn.wave.id.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.wave.shuffle.ll
[AMDGPU] Improve llvm.amdgcn.wave.shuffle handling for pre-GFX8 (#174845)
2026-01-07 21:48:11 +01:00
llvm.amdgcn.wavefrontsize.ll
…
llvm.amdgcn.wmma_32.ll
…
llvm.amdgcn.wmma_64.ll
…
llvm.amdgcn.wmma.gfx1250.w32.ll
Revert "[AMDGPU] add clamp immediate operand to WMMA iu8 intrinsic (#171069)" (#174303)
2026-01-04 02:13:21 +00:00
llvm.amdgcn.wmma.imm.gfx1250.w32.ll
Revert "[AMDGPU] add clamp immediate operand to WMMA iu8 intrinsic (#171069)" (#174303)
2026-01-04 02:13:21 +00:00
llvm.amdgcn.wmma.imod.gfx1250.w32.ll
Revert "[AMDGPU] add clamp immediate operand to WMMA iu8 intrinsic (#171069)" (#174303)
2026-01-04 02:13:21 +00:00
llvm.amdgcn.wmma.index.gfx1250.w32.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.workgroup.id.ll
…
llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
…
llvm.amdgcn.workitem.id.ll
…
llvm.amdgcn.wqm.demote.ll
AMDGPU: Consider isVGPRImm when forming constant from build_vector (#168168)
2025-11-14 21:42:26 -08:00
llvm.amdgcn.wqm.ll
…
llvm.amdgcn.wqm.vote.ll
…
llvm.amdgcn.writelane.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.writelane.ptr.ll
…
llvm.ceil.f16.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
llvm.cos.bf16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.cos.f16.ll
[AMDGPU] Enable ISD::{FSIN,FCOS} custom lowering to work on v2f16 (#176382)
2026-01-20 07:35:54 +01:00
llvm.cos.ll
…
llvm.dbg.value.ll
…
llvm.deoptimize.ll
DAG: Check if deoptimize call is available before emitting it (#170940)
2025-12-29 21:48:28 +00:00
llvm.exp2.bf16.ll
AMDGPU: Directly use v2bf16 as register type for bf16 vectors. (#175761)
2026-01-13 17:48:38 +01:00
llvm.exp2.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.exp10.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.exp.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.floor.f16.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
llvm.fma.f16.ll
…
llvm.fmuladd.f16.ll
[AMDGPU] Extend RA hints to handle VGPR_16_Lo128 (#176819)
2026-01-19 13:41:14 -08:00
llvm.fptrunc.round.err.ll
…
llvm.fptrunc.round.ll
…
llvm.frexp.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.get.fpmode.ll
…
llvm.get.rounding.ll
…
llvm.is.fpclass.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.is.fpclass.f16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.is.fpclass.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_IS_FPCLASS (#167575)
2025-11-18 09:00:57 -08:00
llvm.ldexp.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.log2.bf16.ll
AMDGPU: Directly use v2bf16 as register type for bf16 vectors. (#175761)
2026-01-13 17:48:38 +01:00
llvm.log2.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.log10.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.log.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.maximum.f16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.maximum.f32.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.maximum.f64.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
llvm.maxnum.f16.ll
…
llvm.memcpy.ll
AMDGPU: Use ELF mangling in data layout (#163011)
2025-10-13 03:01:45 +00:00
llvm.minimum.f16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.minimum.f32.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.minimum.f64.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
llvm.minnum.f16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.mulo.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.pow-gfx9.ll
…
llvm.pow.ll
…
llvm.powi.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.prefetch.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.r600.cube.ll
…
llvm.r600.dot4.ll
…
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll
…
llvm.r600.recipsqrt.clamped.ll
…
llvm.r600.recipsqrt.ieee.ll
…
llvm.r600.tex.ll
…
llvm.rint.f16.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
llvm.rint.f64.ll
…
llvm.rint.ll
…
llvm.round.f64.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
llvm.round.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
llvm.set.rounding.ll
…
llvm.sin.bf16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.sin.f16.ll
[AMDGPU] Enable ISD::{FSIN,FCOS} custom lowering to work on v2f16 (#176382)
2026-01-20 07:35:54 +01:00
llvm.sin.ll
[DAGCombiner] Remove most UnsafeFPMath references (#146295)
2025-08-22 15:27:25 +08:00
llvm.sqrt.bf16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.sqrt.f16.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
llvm.trunc.f16.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
lo16-hi16-illegal-copy.mir
…
lo16-hi16-physreg-copy.mir
…
lo16-lo16-physreg-copy-agpr.mir
…
lo16-lo16-physreg-copy-sgpr.mir
…
load-constant-always-uniform.ll
…
load-constant-f32.ll
…
load-constant-f64.ll
…
load-constant-i1.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
load-constant-i8.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
load-constant-i16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
load-constant-i32.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
load-constant-i64.ll
…
load-global-f32.ll
…
load-global-f64.ll
…
load-global-i1.ll
…
load-global-i8.ll
[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (#165295)
2025-11-11 13:14:48 -06:00
load-global-i16.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
load-global-i32.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
load-global-i64.ll
…
load-global-invariant.ll
AMDGPU: Add baseline test for split/widen invariant loads (#168913)
2025-11-21 13:53:14 -05:00
load-hi16.ll
…
load-input-fold.ll
…
load-lo16.ll
…
load-local-f32-no-ds128.ll
…
load-local-f32.ll
…
load-local-f64.ll
…
load-local-i1.ll
…
load-local-i8.ll
…
load-local-i16.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
load-local-i32.ll
…
load-local-i64.ll
…
load-local-redundant-copies.ll
…
load-local.96.ll
…
load-local.128.ll
…
load-range-metadata-assert.ll
…
load-range-metadata-sign-bits.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
load-select-ptr.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
load-store-cnt.ll
…
load-store-opt-addc0.mir
…
load-store-opt-dlc.mir
…
load-store-opt-ds-regclass-constrain.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
load-store-opt-scale-offset.mir
[AMDGPU] Enable XNACK on gfx1250 (#161457)
2025-10-03 11:04:55 -04:00
load-store-opt-scc.mir
…
load-weird-sizes.ll
…
local-64.ll
…
local-atomicrmw-fadd.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
local-atomicrmw-fmax.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
local-atomicrmw-fmin.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
local-atomicrmw-fsub.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
local-atomics64.ll
…
local-atomics.ll
…
local-memory.amdgcn.ll
…
local-memory.ll
…
local-memory.r600.ll
…
local-stack-alloc-add-references.gfx8.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
local-stack-alloc-add-references.gfx9.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
local-stack-alloc-add-references.gfx10.mir
[CodeGen] Consider imm offsets when sorting framerefs (#171012)
2026-01-08 17:48:30 -05:00
local-stack-alloc-block-sp-reference.ll
[CodeGen] Consider imm offsets when sorting framerefs (#171012)
2026-01-08 17:48:30 -05:00
local-stack-alloc-sort-framerefs.mir
[CodeGen] Consider imm offsets when sorting framerefs (#171012)
2026-01-08 17:48:30 -05:00
local-stack-slot-offset.ll
…
long-branch-reserve-register.ll
…
loop_break.ll
…
loop_exit_with_xor.ll
…
loop_header_nopred.mir
…
loop-address.ll
…
loop-idiom.ll
…
loop-live-out-copy-undef-subrange.ll
…
loop-on-function-argument.ll
…
loop-prefetch-data.ll
[AMDGPU] Add support for GFX12 expert scheduling mode 2 (#170319)
2026-01-09 15:49:10 +00:00
loop-prefetch.ll
…
loop-vector-sink.ll
[AMDGPU] Precommit test for sinking vector ops PR 162580 (#165050)
2025-10-27 13:44:44 -04:00
lower-brcond-with-xor.ll
[AMDGPU] Support xor cond, -1 when lowering BRCOND (#160341)
2025-09-23 17:16:21 -04:00
lower-buffer-fat-pointers-calls.ll
…
lower-buffer-fat-pointers-constants.ll
[AMDGPU][LowerBufferFatPointers] Fix lack of rewrite when loading/storing null (#154128)
2025-08-18 12:32:54 -05:00
lower-buffer-fat-pointers-contents-legalization.ll
…
lower-buffer-fat-pointers-control-flow.ll
[AMDGPU][LowerBufferFatPointers] Fix crash with select false (#166471)
2025-11-05 19:21:52 +00:00
lower-buffer-fat-pointers-dead-intrinsics.ll
[AMDGPU][LowerBufferFatPointers] Erase dead ptr(7) intrinsics (#160798)
2025-09-29 10:46:45 -05:00
lower-buffer-fat-pointers-lastuse-metadata.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
lower-buffer-fat-pointers-mem-transfer.ll
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
2025-12-03 11:13:52 +01:00
lower-buffer-fat-pointers-memops.ll
…
lower-buffer-fat-pointers-nontemporal-metadata.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
lower-buffer-fat-pointers-p7-in-memory.ll
…
lower-buffer-fat-pointers-pointer-ops.ll
[LangRef] Specify icmp on pointers to only compare address (#163936)
2025-12-04 15:24:23 +00:00
lower-buffer-fat-pointers-unoptimized-debug-data.ll
[RemoveDIs][AMDGPU] Replace defunct getAssignmentMarkers call (#153212)
2025-08-12 17:20:38 +01:00
lower-control-flow-live-intervals.mir
…
lower-control-flow-live-variables-update.mir
…
lower-control-flow-live-variables-update.xfail.mir
…
lower-control-flow-other-terminators.mir
…
lower-ctor-dtor-constexpr-alias.ll
…
lower-ctor-dtor-declaration.ll
…
lower-ctor-dtor-existing.ll
…
lower-ctor-dtor.ll
…
lower-empty-ctor-dtor.ll
…
lower-i1-copies-clear-kills.mir
…
lower-i1-copies-implicit-def-unstructured-loop.mir
…
lower-indirect-lds-references.ll
…
lower-intrinsics-barriers.ll
AMDGPU: Refactor lowering of s_barrier to split barriers (#154648)
2025-08-28 07:01:20 -07:00
lower-intrinsics-cluster-barrier.ll
[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)
2025-09-16 14:49:48 -07:00
lower-intrinsics-split-barriers.ll
AMDGPU: Refactor lowering of s_barrier to split barriers (#154648)
2025-08-28 07:01:20 -07:00
lower-kernargs.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
lower-kernel-and-module-lds.ll
…
lower-kernel-lds-constexpr.ll
[ReplaceConstant] Don't create instructions for the same constant multiple times in the same basic block (#169141)
2025-11-26 22:44:40 -05:00
lower-kernel-lds-super-align.ll
…
lower-kernel-lds.ll
…
lower-lds-struct-aa-memcpy.ll
Revert "CodeGen: Record MMOs in finalizeBundle" (#166520)
2025-11-05 11:11:08 +01:00
lower-lds-struct-aa-merge.ll
…
lower-lds-struct-aa.ll
Revert "CodeGen: Record MMOs in finalizeBundle" (#166520)
2025-11-05 11:11:08 +01:00
lower-lds-with-alias-scope.ll
…
lower-lds-with-noalias.ll
…
lower-mem-intrinsics-threshold.ll
…
lower-mem-intrinsics.ll
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
2025-12-03 11:13:52 +01:00
lower-module-lds-all-indirect-accesses.ll
…
lower-module-lds-check-metadata.ll
…
lower-module-lds-constantexpr-phi.ll
…
lower-module-lds-constantexpr.ll
[ReplaceConstant] Don't create instructions for the same constant multiple times in the same basic block (#169141)
2025-11-26 22:44:40 -05:00
lower-module-lds-inactive.ll
…
lower-module-lds-indirect-extern-uses-max-reachable-alignment.ll
…
lower-module-lds-offsets.ll
…
lower-module-lds-precise-allocate-to-module-struct.ll
[AMDGPU] Be less optimistic when allocating module scope lds (#161464)
2025-10-02 16:15:48 -04:00
lower-module-lds-single-var-ambiguous.ll
…
lower-module-lds-single-var-unambiguous.ll
…
lower-module-lds-used-list.ll
…
lower-module-lds-via-hybrid.ll
[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)
2025-10-02 10:06:25 +02:00
lower-module-lds-via-table.ll
[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)
2025-10-02 10:06:25 +02:00
lower-module-lds-zero-size-arr.ll
…
lower-module-lds.ll
…
lower-multiple-ctor-dtor.ll
…
lower-noalias-kernargs.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
lower-range-metadata-intrinsic-call.ll
…
lower-term-opcodes.mir
…
lower-work-group-id-intrinsics-hsa.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
lower-work-group-id-intrinsics-opt.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
lower-work-group-id-intrinsics-pal.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
lower-work-group-id-intrinsics.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
lrint.ll
…
lro-coerce-v4i8-phi-loop.ll
[AMDGPU] LiveRegOptimizer: consider i8/i16 binops on SDWA (#155800)
2025-12-15 12:04:33 -05:00
lro-phi-samebb-nonlookthrough-store.ll
[AMDGPU] LRO: allow same-BB non-lookthrough users for PHI (#160909)
2025-09-30 00:57:07 +09:00
lround.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
lshl64-to-32.ll
…
lshl-add-u64.ll
[AMDGPU] Add few missing gfx1250 codegen tests. NFC (#155314)
2025-08-25 15:22:33 -07:00
lshr.v2i16.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
lto-lower-module-lds.ll
…
machine-cse-commute-target-flags.mir
…
machine-cse-ssa.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
machine-function-info-cwsr.ll
[AMDGPU] AMDGPUPromoteAlloca: increase default max-regs to 32 (#155076)
2025-08-26 09:30:16 +09:00
machine-scheduler-sink-trivial-remats-attr.mir
Revert "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#175813)
2026-01-13 19:29:50 +00:00
machine-scheduler-sink-trivial-remats-debug.mir
Revert "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#175813)
2026-01-13 19:29:50 +00:00
machine-scheduler-sink-trivial-remats.mir
Revert "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#175813)
2026-01-13 19:29:50 +00:00
machine-sink-cycle.mir
…
machine-sink-ignorable-exec-use.mir
…
machine-sink-lane-mask.mir
…
machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
…
machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
…
machine-sink-temporal-divergence-swdev407790.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
machine-sink-temporal-divergence-swdev407790.mir
…
machinelicm-convergent.mir
…
machinelicm-copy-like-instrs.mir
…
machinelicm-undef-use.mir
…
macro-fusion-cluster-vcc-uses.mir
…
mad24-get-global-id.ll
…
mad_64_32.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
mad_int24.ll
[AMDGPU] Regenerate test checks for mad24 tests (#162455)
2025-10-08 13:36:50 +01:00
mad_u64_u32.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
mad_uint24.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
mad-combine.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
mad-mix-bf16.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
mad-mix-hi-bf16.ll
…
mad-mix-hi.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
mad-mix-lo-bf16.ll
…
mad-mix-lo.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
mad-mix.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
mad.u16.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
madak-inline-constant.mir
[AMDGPU] Skip debug uses in SIInstrInfo::foldImmediate (#160102)
2025-09-22 15:22:09 +01:00
madak.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
madmk.ll
…
mai-hazards-gfx90a.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mai-hazards-gfx942.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mai-hazards-mfma-scale.gfx950.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mai-hazards.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
mai-inline.ll
…
make-buffer-rsrc-lds-fails.ll
[AMDGPU] Add the support for 45-bit buffer resource (#159702)
2025-09-24 11:12:02 -04:00
masked-load-vectortypes.ll
[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)
2025-11-21 15:17:55 +00:00
match-perm-extract-vector-elt-bug.ll
[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)
2025-10-02 10:06:25 +02:00
materialize-frame-index-sgpr.gfx10.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
materialize-frame-index-sgpr.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
max3.ll
…
max-hard-clause-length.ll
…
max-literals.ll
…
max-sgprs.ll
…
max.i16.ll
…
max.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
maximumnum.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
maximumnum.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
mcexpr-knownbits-assign-crash-gh-issue-110930.ll
…
mcp-aligned-vgprs.mir
…
mcp-implicit-clobber.mir
…
mcp-overlap-after-propagation.mir
…
mcp-use-before-def.mir
…
mdt-preserving-crash.ll
…
med3-knownbits.ll
…
med3-no-simplify.ll
…
mem-builtins.ll
…
memcpy-crash-issue63986.ll
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
2025-12-03 11:13:52 +01:00
memcpy-fixed-align.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memcpy-inline-fails.ll
…
memcpy-libcall.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memcpy-param-combinations.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memcpy-scalar-load.ll
…
memcpy-scoped-aa.ll
…
memintrinsic-unroll.ll
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
2025-12-03 11:13:52 +01:00
memmove-param-combinations.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memmove-scalar-load.ll
…
memmove-var-size.ll
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
2025-12-03 11:13:52 +01:00
memory_clause.ll
…
memory_clause.mir
…
memory-legalizer-atomic-insert-end.mir
…
memory-legalizer-barriers-mmra.ll
[AMDGPU] Insert waitcnt for non-global fence release in GFX12 (#159282)
2025-09-23 11:52:38 +02:00
memory-legalizer-barriers.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
memory-legalizer-buffer-atomics.ll
[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#168852)
2025-11-25 10:11:04 +01:00
memory-legalizer-fence-mmra-global.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
memory-legalizer-fence-mmra-local.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-fence.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
memory-legalizer-flat-agent.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
memory-legalizer-flat-cluster.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-flat-lastuse.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-flat-nontemporal.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-flat-singlethread.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-flat-system.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
memory-legalizer-flat-volatile.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-flat-wavefront.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-flat-workgroup.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-global-agent.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
memory-legalizer-global-cluster.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-global-lastuse.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-global-nontemporal.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-global-singlethread.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-global-system.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
memory-legalizer-global-volatile.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-global-wavefront.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-global-workgroup.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-invalid-addrspace.mir
…
memory-legalizer-invalid-syncscope.ll
…
memory-legalizer-lds-dma-volatile-and-nontemporal.ll
[AMDGPU] Enable volatile and non-temporal for loads to LDS (#153244)
2025-10-20 12:42:22 -05:00
memory-legalizer-local-agent.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-local-cluster.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-local-nontemporal.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-local-singlethread.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-local-system.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-local-volatile.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-local-wavefront.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-local-workgroup.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
memory-legalizer-local.mir
…
memory-legalizer-multiple-mem-operands-atomics.mir
…
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
memory-legalizer-private-agent.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
memory-legalizer-private-cluster.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-private-lastuse.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-private-nontemporal.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-private-singlethread.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-private-system.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
memory-legalizer-private-volatile.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-private-wavefront.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-private-workgroup.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
memory-legalizer-region.mir
…
memory-legalizer-store-infinite-loop.ll
…
merge-buffer-gfx12.mir
…
merge-buffer.mir
…
merge-consecutive-wait-alus.mir
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
merge-flat-load-store.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
merge-flat-saddr-load-store.mir
[AMDGPU] Support merging of flat GVS ops (#154200)
2025-08-18 14:31:41 -07:00
merge-flat-with-global-load-store.mir
…
merge-global-load-store.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
merge-image-load-gfx10.mir
…
merge-image-load-gfx11.mir
…
merge-image-load-gfx12.mir
…
merge-image-load.mir
…
merge-image-sample-gfx10.mir
…
merge-image-sample-gfx11.mir
…
merge-image-sample-gfx12.mir
…
merge-image-sample.mir
…
merge-load-store-agpr.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
merge-load-store-physreg.mir
…
merge-load-store-vreg.mir
…
merge-load-store.mir
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
merge-m0.mir
…
merge-out-of-order-ldst.ll
…
merge-out-of-order-ldst.mir
…
merge-s-load.mir
…
merge-sbuffer-load.mir
…
merge-store-crash.ll
…
merge-store-usedef.ll
…
merge-stores.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
merge-tbuffer-gfx9.mir
…
merge-tbuffer-gfx10.mir
…
merge-tbuffer-gfx11.mir
[AMDGPU] Support merging 16-bit and 8-bit TBUFFER load/store instruction (#145078)
2025-08-20 21:16:25 +08:00
merge-tbuffer-gfx12.mir
…
merged-bfx-opt.ll
…
mesa3d.ll
…
mesa_regression.ll
…
mfma-bf16-vgpr-cd-select.ll
…
mfma-cd-select.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mfma-loop.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
mfma-no-register-aliasing.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
mfma-vgpr-cd-select-gfx942.ll
…
mfma-vgpr-cd-select.ll
…
min3.ll
…
min-waves-per-eu-not-respected.ll
…
min.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
minimummaximum.ll
…
minimumnum.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
minimumnum.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
minmax.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
mir-print-dead-csr-fi.mir
…
misched-into-wmma-hazard-shadow.mir
[AMDGPU] Allow hazard checks for WMMA co-exec (#168805)
2025-12-01 11:46:30 -08:00
misched-killflags.mir
…
missing-store.ll
…
mixed_wave32_wave64.ll
…
mixed-vmem-types.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
mixed-wave32-wave64.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
mmo-target-flags-folding.ll
…
mmra.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
mode-register-fpconstrain.ll
…
mode-register-fptrunc.gfx11plus-fake16.mir
…
mode-register-fptrunc.gfx11plus.mir
…
mode-register-fptrunc.mir
…
mode-register.mir
…
module-lds-false-sharing.ll
…
move-addr64-rsrc-dead-subreg-writes.ll
…
move-load-addr-to-valu-flat.mir
…
move-load-addr-to-valu.mir
…
move-to-valu-absdiff.mir
[AMDGPU] Lower S_ABSDIFF_I32 to VALU instructions (#167691)
2025-11-13 14:35:44 +01:00
move-to-valu-addsubu64.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-atomicrmw-system.ll
…
move-to-valu-atomicrmw.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
move-to-valu-ctlz-cttz.ll
…
move-to-valu-lshl_add.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
move-to-valu-lshlrev.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-pseudo-scalar-trans-f16-fake16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-pseudo-scalar-trans-f16-true16.ll
…
move-to-valu-pseudo-scalar-trans.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-vimage-vsample.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-worklist.ll
…
movreld-bug.ll
…
movrels-bug.mir
…
mubuf-legalize-operands-non-ptr-intrinsics.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
mubuf-legalize-operands.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
mubuf-legalize-operands.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
mubuf-offset-private.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
mubuf-shader-vgpr-non-ptr-intrinsics.ll
…
mubuf-shader-vgpr.ll
…
mubuf.ll
…
mul24-pass-ordering.ll
AMDGPU: Remove some unnecessary callsite attributes from tests (#174270)
2026-01-03 10:53:33 +00:00
mul_int24.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
mul_uint24-amdgcn.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
mul_uint24-r600.ll
…
mul.i16.ll
…
mul.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
multi-call-resource-usage-mcexpr.ll
…
multi-divergent-exit-region.ll
…
multi-dword-vgpr-spill.ll
…
multilevel-break.ll
…
naked-fn-with-frame-pointer.ll
AMDGPU: Use ELF mangling in data layout (#163011)
2025-10-13 03:01:45 +00:00
nand.ll
…
narrow_math_for_and.ll
…
need-fp-from-vgpr-spills.ll
…
neg_ashr64_reduce.ll
[AMDGPU][SDAG] Only fold flat offsets if they are inbounds PTRADDs (#165427)
2025-11-19 11:48:12 +01:00
neighboring-mfma-padding.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
nested-calls.ll
…
nested-loop-conditions.ll
…
no-bundle-asm.ll
…
no-corresponding-integer-type.ll
…
no-dup-inst-prefetch.ll
…
no-fold-accvgpr-mov.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
no-fold-accvgpr-mov.mir
…
no-fold-accvgpr-read.mir
…
no-folding-imm-to-inst-with-fi.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
no-hsa-graphics-shaders.ll
…
no-initializer-constant-addrspace.ll
…
no-limit-coalesce.mir
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
no-remat-indirect-mov.mir
…
no-shrink-extloads.ll
…
no-source-locations-in-prologue.ll
…
noclobber-barrier.ll
…
nofpclass-call.ll
DAG: Fix assert on nofpclass call with aggregate return (#167725)
2025-11-12 18:12:20 +00:00
non-entry-alloca.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
noop-shader-O0.ll
…
nop-data.ll
…
nor-divergent-lanemask.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
nor.ll
…
not-scalarize-volatile-load.ll
…
nsa-reassign.ll
…
nsa-reassign.mir
…
nsa-vmem-hazard.mir
…
nullptr-long-address-spaces.ll
…
nullptr.ll
…
occupancy-levels.ll
[AMDGPU] Define gfx1310 target with ELF number 0x50 (#177355)
2026-01-22 17:08:38 +01:00
offset-split-flat.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
offset-split-global.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
omod-nsz-flag.mir
…
omod.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
opencl-image-metadata.ll
…
opencl-printf-and-hostcall.ll
…
opencl-printf-pipeline.ll
…
opencl-printf-unsupported.ll
…
opencl-printf.ll
[AMDGPU] Fix use-after-erase in OpenCL printf runtime binding (#177356)
2026-01-23 09:02:56 +01:00
operand-folding.ll
…
operand-spacing.ll
…
opt_exec_copy_fold.mir
…
opt-exec-masking-pre-ra-update-liveness-wave32.mir
…
opt-exec-masking-pre-ra-update-liveness.mir
…
opt-sgpr-to-vgpr-copy.mir
…
opt-vgpr-live-range-verifier-error.mir
…
optimize-compare.ll
…
optimize-compare.mir
[AMDGPU] Remove redundant s_cmp_* after add X, 1 (#176962)
2026-01-23 07:51:36 -06:00
optimize-exec-copies-extra-insts-after-copy.mir
…
optimize-exec-mask-pre-ra-alloc-failure.mir
…
optimize-exec-mask-pre-ra-def-after-use.mir
…
optimize-exec-mask-pre-ra-loop-phi.mir
…
optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
[AMDGPU] SIOptimizeExecMaskingPreRA: Fix crash on exec copy fold into INLINEASM (#172481)
2025-12-16 17:55:05 +01:00
optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
…
optimize-exec-masking-pre-ra.mir
…
optimize-exec-masking-strip-terminator-bits.mir
…
optimize-if-exec-masking.mir
…
optimize-negated-cond-exec-masking-wave32.mir
…
optimize-negated-cond-exec-masking.mir
…
optimize-negated-cond.ll
…
or3.ll
…
or.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
or.r600.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
overlapping-tuple-copy-implicit-op-failure.ll
…
pack.v2f16.ll
…
pack.v2i16.ll
…
packed-fp32.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
packed-op-sel.ll
…
packetizer.ll
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
pal-metadata-3.0-callable-dvgpr.ll
…
pal-metadata-3.0-callable.ll
[AMDGPU] Remove subtarget features for dynamic VGPRs (#160822)
2025-10-06 09:50:11 +02:00
pal-metadata-3.0-dvgpr.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
pal-metadata-3.0.gfx950.ll
[AMDGPU] update LDS block size for gfx1250 (#167614)
2025-11-17 16:03:47 -08:00
pal-metadata-3.0.gfx1250.ll
[AMDGPU] update LDS block size for gfx1250 (#167614)
2025-11-17 16:03:47 -08:00
pal-metadata-3.0.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
pal-metadata-3.6-dvgpr.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
pal-metadata-3.6.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
pal-simple-indirect-call.ll
[AMDGPU][Attributor] Remove final update of waves-per-eu after the attributor run (#155246)
2025-08-27 14:11:03 -04:00
pal-userdata-regs.ll
…
parallelandifcollapse.ll
…
parallelorifcollapse.ll
…
partial-forwarding-hazards.mir
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
partial-regcopy-and-spill-missed-at-regalloc.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
partial-sgpr-to-vgpr-spills.ll
…
partial-shift-shrink.ll
…
partially-dead-super-register-immediate.ll
…
peephole-fold-imm-multi-use.mir
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
peephole-fold-imm.mir
AMDGPU: Simplify foldImmediate with register class based checks (#154682)
2025-08-23 02:13:50 +00:00
peephole-opt-fold-reg-sequence-subreg.mir
…
peephole-opt-regseq-removal.mir
PeepholeOpt: Fix losing subregister indexes on full copies (#161310)
2025-10-02 13:36:47 +09:00
pei-amdgpu-cs-chain-preserve.mir
…
pei-amdgpu-cs-chain.mir
…
pei-build-av-spill.mir
…
pei-build-spill-partial-agpr.mir
[AMDGPU] Use implicit operand to preserve liveness of COPY (#164911)
2025-10-27 10:47:11 -07:00
pei-build-spill.mir
…
pei-reg-scavenger-position.mir
…
pei-scavenge-sgpr-carry-out.mir
…
pei-scavenge-sgpr-gfx9.mir
…
pei-scavenge-sgpr.mir
…
pei-scavenge-vgpr-spill.mir
…
pei-vgpr-block-spill-csr.mir
[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)
2025-09-03 16:25:18 -07:00
perfhint.ll
…
permlane16_opsel.ll
…
permlane16_var-op-sel.ll
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
permlane-op-sel.ll
…
permute_i8.ll
…
permute.ll
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
phi-elim-mli-available.mir
[PHIElimination] Declare MachineLoopInfo dependency for Legacy PM (#169693)
2025-12-06 19:56:01 +05:30
phi-elimination-assertion.mir
…
phi-elimination-end-cf.mir
…
phi-vgpr-input-moveimm.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
phys-partial-liveness.mir
…
pk_max_f16_literal.ll
…
post-ra-sched-kill-bundle-use-inst.mir
…
post-ra-sched-reset.mir
…
post-ra-soft-clause-dbg-info.ll
…
postra-bundle-memops.mir
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
postra-bundle-vimage-vsample-gfx12.mir
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
postra-machine-sink-livein-subrange.mir
[MachineSink] Remove subrange of live-ins from super register as well. (#159145)
2025-09-26 14:45:26 +09:00
postra-machine-sink.mir
…
postra-norename.mir
…
postra-sched-attribute.ll
…
postra-sink-update-dependency.mir
…
power-sched-no-instr-sunit.mir
…
pr51516.mir
…
pr155452.ll
[DAG] ComputeNumSignBits - ISD::EXTRACT_ELEMENT needs to return at least 1 (#155455)
2025-08-26 14:28:02 -07:00
predicate-dp4.ll
…
predicates.ll
…
preload-implicit-kernargs-debug-info.ll
…
preload-implicit-kernargs-IR-lowering.ll
…
preload-implicit-kernargs.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
preload-kernarg-header.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
preload-kernargs-IR-lowering.ll
…
preload-kernargs.ll
[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#168852)
2025-11-25 10:11:04 +01:00
preserve-hi16.ll
[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)
2025-09-24 11:27:26 -04:00
preserve-only-inactive-lane.mir
…
preserve-user-waitcnt.ll
…
preserve-wwm-copy-dst-reg.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
prevent-fmul-hoist-ir.ll
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
print-pipeline-passes.ll
…
printf_builtin.ll
…
printf_nobuiltin.ll
…
printf-defined.ll
…
printf-existing-format-strings.ll
…
private-access-no-objects.ll
…
private-function.ll
[UTC] Update AMDGPU asm regexp for private functions (#166169)
2025-11-04 11:59:43 +00:00
private-memory-atomics.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
private-memory-r600.ll
…
prologue-epilogue-markers.ll
…
promote-alloca-addrspacecast.ll
…
promote-alloca-array-aggregate.ll
…
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
…
promote-alloca-budget-exhausted.ll
…
promote-alloca-calling-conv.ll
…
promote-alloca-cfg.ll
Reland "AMDGPU/PromoteAlloca: Simplify how deferred loads work (#170510)" (#170955)
2025-12-06 01:15:28 +00:00
promote-alloca-globals.ll
…
promote-alloca-invariant-markers.ll
…
promote-alloca-lifetime.ll
…
promote-alloca-loadstores.ll
…
promote-alloca-max-regs.ll
[AMDGPU] AMDGPUPromoteAlloca: increase default max-regs to 32 (#155076)
2025-08-26 09:30:16 +09:00
promote-alloca-mem-intrinsics.ll
[AMDGPU] AMDGPUPromoteAlloca: increase default max-regs to 32 (#155076)
2025-08-26 09:30:16 +09:00
promote-alloca-memset.ll
…
promote-alloca-multidim.ll
Reland "AMDGPU/PromoteAlloca: Always use i32 for indexing (#170511)" (#170956)
2025-12-06 08:54:44 -08:00
promote-alloca-negative-index.ll
AMDGPU/PromoteAlloca: Refactor into analysis / commit phases (#170512)
2025-12-12 01:24:38 +00:00
promote-alloca-no-opts.ll
…
promote-alloca-non-byte-sizes.ll
…
promote-alloca-non-constant-index.ll
…
promote-alloca-padding-size-estimate.ll
…
promote-alloca-pointer-array.ll
…
promote-alloca-scoring.ll
AMDGPU/PromoteAlloca: Refactor into analysis / commit phases (#170512)
2025-12-12 01:24:38 +00:00
promote-alloca-shufflevector.ll
…
promote-alloca-stored-pointer-value.ll
…
promote-alloca-strip-abi-opt-attributes.ll
…
promote-alloca-subvecs.ll
…
promote-alloca-to-lds-constantexpr-use.ll
…
promote-alloca-to-lds-icmp.ll
…
promote-alloca-to-lds-phi.ll
…
promote-alloca-to-lds-select.ll
…
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-use-after-erase.ll
[AMDGPU] Fix a potential use-after-erase in AMDGPUPromoteAlloca pass (#174529)
2026-01-08 11:44:16 -05:00
promote-alloca-user-mult.ll
AMDGPU: cleanup promote-alloca-user-mult.ll test (#173071)
2025-12-19 14:34:02 -06:00
promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
[AMDGPU] In promote-alloca, if index is dynamic, sandwich load with bitcasts to reduce excessive codegen (#171253)
2025-12-19 14:06:52 -05:00
promote-alloca-vector-dynamic-idx-bitcasts.ll
[AMDGPU] In promote-alloca, if index is dynamic, sandwich load with bitcasts to reduce excessive codegen (#171253)
2025-12-19 14:06:52 -05:00
promote-alloca-vector-gep-of-gep.ll
[AMDGPU] Generate canonical additions in AMDGPUPromoteAlloca (#157810)
2025-09-10 14:46:46 +02:00
promote-alloca-vector-gep.ll
Revert "[AMDGPU] Enable i8 GEP promotion for vector allocas" (#171087)
2025-12-08 08:25:48 +00:00
promote-alloca-vector-to-vector.ll
Reland "AMDGPU/PromoteAlloca: Always use i32 for indexing (#170511)" (#170956)
2025-12-06 08:54:44 -08:00
promote-alloca-vgpr-ratio.ll
…
promote-alloca-volatile.ll
…
promote-constOffset-to-imm-gfx10.mir
…
promote-constOffset-to-imm-gfx12.ll
[AMDGPU][SILoadStoreOptimizer] Fix lds address operand offset (#176816)
2026-01-26 09:23:17 +01:00
promote-constOffset-to-imm-gfx12.mir
[AMDGPU][SILoadStoreOptimizer] Fix lds address operand offset (#176816)
2026-01-26 09:23:17 +01:00
promote-constOffset-to-imm-gfx90a.mir
…
promote-constOffset-to-imm.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
promote-constOffset-to-imm.mir
…
promote-kernel-arguments.ll
…
promote-vect3-load.ll
…
propagate-amdgpu-cluster-dims.ll
[NFC][AMDGPU] Add a missing test case about cluster dims (#159179)
2025-09-16 22:56:24 -04:00
propagate-attributes-bitcast-function.ll
…
propagate-flat-work-group-size.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
propagate-waves-per-eu.ll
Revert "[AMDGPU] Allow amdgpu-waves-per-eu to lower target occupancy range" (#177544)
2026-01-23 08:55:14 +00:00
ps-shader-arg-count.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
pseudo-scalar-transcendental.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
pseudo-scalar-transcendental.mir
…
ptr-arg-dbg-value.ll
…
ptr-buffer-alias-scheduling.ll
[AMDGPU] Add the support for 45-bit buffer resource (#159702)
2025-09-24 11:12:02 -04:00
ptradd-sdag-mubuf.ll
[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)
2025-10-02 10:06:25 +02:00
ptradd-sdag-optimizations.ll
[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)
2025-10-02 10:06:25 +02:00
ptradd-sdag-undef-poison.ll
[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)
2025-10-02 10:06:25 +02:00
ptradd-sdag.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
ptrmask.ll
…
pv-packing.ll
…
pv.ll
…
r600-constant-array-fixup.ll
…
r600-encoding.ll
…
r600-export-fix.ll
…
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600-legalize-umax-bug.ll
…
r600.add.ll
…
r600.alu-limits.ll
…
r600.amdgpu-alias-analysis.ll
…
r600.bitcast.ll
…
r600.extract-lowbits.ll
…
r600.func-alignment.ll
…
r600.global_atomics.ll
…
r600.llvm.is.fpclass.ll
…
r600.private-memory.ll
…
r600.sub.ll
…
r600.work-item-intrinsics.ll
…
r600cfg.ll
…
ra-inserted-scalar-instructions.mir
…
ran-out-of-registers-error-all-regs-reserved.ll
…
ran-out-of-registers-errors.ll
…
ran-out-of-sgprs-allocation-failure.mir
[AMDGPU] Add liverange split instructions into BB Prolog (#117544)
2026-01-09 21:25:14 +05:30
rcp_iflag.ll
…
rcp-pattern.ll
…
read_register.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
read-register-invalid-register.ll
…
read-register-invalid-subtarget.ll
…
read-register-invalid-type-i32.ll
…
read-register-invalid-type-i64.ll
…
read-write-register-illegal-type.ll
…
readcyclecounter.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_READCYCLECOUNTER (#165754)
2025-10-31 09:12:56 -07:00
readlane_exec0.mir
…
README
…
readsteadycounter.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_READSTEADYCOUNTER (#163661)
2025-10-16 09:45:33 -07:00
reassoc-mul-add-1-to-mad.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
reassoc-scalar.ll
…
recursion.ll
…
recursive_global_initializer.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
recursive-resource-usage-mcexpr.ll
…
reduce-build-vec-ext-to-ext-build-vec.ll
…
reduce-load-width-alignment.ll
…
reduce-saveexec.mir
…
reduce-store-width-alignment.ll
…
reduction.ll
…
reg-coalescer-sched-crash.ll
…
reg-coalescer-subreg-liveness.mir
AMDGPU: Update test after e95f6fa12
2025-11-10 10:23:54 -08:00
reg-sequence-like-v-pk-mov-b32.mir
…
regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
…
regalloc-failure-overlapping-insert-assert.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
regalloc-fast-dont-drop-subreg-index-issue61134.mir
…
regalloc-illegal-eviction-assert.ll
…
regalloc-introduces-copy-sgpr-to-agpr.mir
…
regalloc-spill-wmma-scale.ll
[AMDGPU] Prioritize allocation of low 256 VGPR classes (#167978)
2025-11-19 16:00:46 -08:00
regalloc-undef-copy-fold.mir
…
regcoal-subrange-join-seg.mir
…
regcoal-subrange-join.mir
…
regcoalesce-64-bit-only-regs.mir
[AMDGPU] Drop high 32 bits of aperture registers (#158725)
2025-09-16 02:11:39 -07:00
regcoalesce-cannot-join-failures.mir
…
regcoalesce-dbg.mir
…
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
…
regcoalesce-prune.mir
…
regcoalescer-resolve-lane-conflict-by-subranges.mir
…
regcoalescing-remove-partial-redundancy-assert.mir
…
register-coalescer--set-undef-full-reg-use-implicit-def-erase-issue109249.mir
…
register-count-comments.ll
…
register-killed-error-after-alloc-failure0.mir
…
register-killed-error-after-alloc-failure1.ll
…
regpressure_printer.mir
[AMDGPU] Use correct SlotIndex to calculate live-out register set. (#161720)
2025-10-10 14:03:27 +02:00
reject-agpr-usage-before-gfx908.ll
…
rel32.ll
…
release-vgprs-dbg-loc.mir
…
release-vgprs-gfx12-dvgpr.mir
…
release-vgprs-gfx12.mir
…
release-vgprs.mir
[AMDGPU] Take BUF instructions into account in mayAccessScratchThroughFlat (#170274)
2025-12-03 10:37:58 +01:00
rem_i128.ll
Revert "SelectionDAG: Do not propagate divergence through glue (#174766)"
2026-01-07 14:23:15 +00:00
remaining-virtual-register-operands.ll
…
remaining-virtual-register-operands.mir
…
remat-dead-subreg.mir
…
remat-fp64-constants.ll
[AMDGPU] Correct validation for the intended behavior of the test (#167411)
2025-11-10 22:06:45 -08:00
remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
…
remat-smrd.mir
…
remat-sop.mir
[RegAlloc] Account for use availability when applying rematerializable weight discount (#159180)
2025-09-26 07:57:12 +08:00
remat-vop.mir
AMDGPU: Fix not diagnosing unaligned VGPRs for vsrc operands (#155104)
2025-08-25 17:42:58 +09:00
remove-incompatible-extended-image-insts.ll
…
remove-incompatible-functions.ll
…
remove-incompatible-gws.ll
…
remove-incompatible-s-time.ll
…
remove-incompatible-wave32-feature.ll
…
remove-incompatible-wave64-feature.ll
[AMDGPU] Remove wave64 functions (#153690)
2025-08-14 15:54:33 -07:00
remove-no-kernel-id-attribute.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
remove-not-short-exec-branch-on-unconditional-jump.mir
…
remove-register-flags.mir
[AMDGPU] Allow any SGPRs for chain callees (#168345)
2025-12-02 09:44:35 +01:00
remove-short-exec-branches-gpr-idx-mode.mir
…
remove-short-exec-branches-special-instructions.mir
…
rename-disconnected-bug.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
rename-independent-subregs-mac-operands.mir
…
rename-independent-subregs.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
reorder-stores.ll
…
repeated-divisor.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
replace-store-of-insert-load.ll
…
reqd-work-group-size.ll
…
required-export-priority.ll
…
required-export-priority.mir
…
reserved-reg-in-clause.mir
…
resource-optimization-remarks.ll
…
resource-usage-crash-unhandled-reg.mir
…
resource-usage-dead-function.ll
[AMDGPU] Move LowerBufferFatPointers after LoadStoreVectorizer and remove the fixme (#161531)
2025-10-01 17:52:15 -07:00
resource-usage-pal.ll
…
ret_jump.ll
…
ret.ll
…
return-with-successors.mir
…
returnaddress.ll
…
rewrite-out-arguments-address-space.ll
…
rewrite-out-arguments.ll
…
rewrite-partial-reg-uses-dbg.mir
…
rewrite-partial-reg-uses-gen.mir
…
rewrite-partial-reg-uses.mir
…
rewrite-undef-for-phi.ll
…
rewrite-vgpr-mfma-scale-to-agpr.mir
[AMDGPU] Fix AGPR_32 reg assign for mfma scale ops (#168964)
2025-12-02 13:41:16 -05:00
rewrite-vgpr-mfma-to-agpr-copy-from.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
rewrite-vgpr-mfma-to-agpr-phi.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
rewrite-vgpr-mfma-to-agpr.gfx90a.ll
AMDGPU: Add tests for every mfma intrinsic v-to-a mapping (#153026)
2025-09-04 11:24:54 +09:00
rewrite-vgpr-mfma-to-agpr.gfx950.ll
AMDGPU: Add tests for every mfma intrinsic v-to-a mapping (#153026)
2025-09-04 11:24:54 +09:00
rewrite-vgpr-mfma-to-agpr.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
rotate-add.ll
…
rotl.i64.ll
…
rotl.ll
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
rotr.i64.ll
…
rotr.ll
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
roundeven.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
rsq.f32-safe.ll
AMDGPU: Stop requiring afn for f32 rsq formation (#172082)
2025-12-23 18:16:15 +01:00
rsq.f32.ll
…
rsq.f64.ll
AMDGPU: Introduce f64 rsq pattern in AMDGPUCodeGenPrepare (#172053)
2025-12-22 15:49:59 +01:00
rv7x0_count3.ll
…
s_add_co_pseudo_lowering.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
s_addk_i32.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
s_cmp_0.ll
[AMDGPU] Remove redundant s_cmp_* after add X, 1 (#176962)
2026-01-23 07:51:36 -06:00
s_code_end.ll
…
s_movk_i32.ll
…
s_mulk_i32.ll
…
s_or_saveexec_xor_combine.mir
…
s_uaddo_usubo_pseudo.ll
[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)
2025-10-22 08:42:29 -05:00
s-barrier-lowering.ll
[AMDGPU] Add amdgpu-lower-exec-sync pass to lower named-barrier globals (#165692)
2025-11-17 10:08:40 +05:30
s-barrier.ll
[AMDGPU] Schedule independent instructions between s_barrier_signal and s_barrier_wait (#172057)
2025-12-16 11:48:50 +05:30
s-cluster-barrier.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
s-getpc-b64-remat.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
s-wakeup-barrier.ll
[AMDGPU] Add s_wakeup_barrier instruction for gfx1250 (#170501)
2025-12-10 09:45:13 +01:00
sad.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
saddo.ll
…
saddsat.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
salu-to-valu.ll
…
same-lds-variable-multiple-use-in-one-phi-node.ll
[ReplaceConstant] Don't create instructions for the same constant multiple times in the same basic block (#169141)
2025-11-26 22:44:40 -05:00
same-slot-agpr-sgpr.mir
…
sampler-resource-id.ll
…
save-fp.ll
…
scalar_to_vector_v2x16.ll
…
scalar_to_vector.gfx11plus.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
scalar_to_vector.ll
[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (#165295)
2025-11-11 13:14:48 -06:00
scalar_to_vector.v8i16.ll
…
scalar-branch-missing-and-exec.ll
…
scalar-float-sop1.ll
[AMDGPU] Improve codegen for uniform f16<-->i32 conversions (#176833)
2026-01-21 13:07:14 -06:00
scalar-float-sop2.ll
…
scalar-float-sopc.ll
…
scalar-store-cache-flush.mir
…
scalarize-insert-subvector.ll
…
scale-offset-flat.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
scale-offset-global.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
scale-offset-scratch.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
scale-offset-smem.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
scc-clobbered-sgpr-to-vmem-spill.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
sched_mfma_rewrite_copies.mir
AMDGPU: Disable scheduler mfma rewrite stage by default for now (#177624)
2026-01-23 23:39:03 +01:00
sched_mfma_rewrite_cost.mir
AMDGPU: Disable scheduler mfma rewrite stage by default for now (#177624)
2026-01-23 23:39:03 +01:00
sched-assert-dead-def-subreg-use-other-subreg.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
sched-assert-onlydbg-value-empty-region.mir
…
sched-barrier-hang-weak-dep.mir
…
sched-barrier-post-RA.mir
…
sched-barrier-pre-RA.mir
…
sched-crash-dbg-value.mir
…
sched-group-barrier-pipeline-solver.mir
…
sched-group-barrier-pre-RA.mir
…
sched-handleMoveUp-subreg-def-across-subreg-def.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
sched-image-sample-post-RA.mir
…
sched-no-schedmodel.mir
…
sched-prefer-non-mfma.mir
…
sched-setprio.ll
…
sched.barrier.inverted.mask.ll
…
sched.group.classification.mir
[AMDGPU] Do not put memory instructions in *ALU SchedGroups (#162560)
2025-10-13 11:49:32 -07:00
schedule-addrspaces.ll
…
schedule-amdgpu-tracker-physreg-crash.ll
…
schedule-amdgpu-tracker-physreg.ll
…
schedule-amdgpu-trackers.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
schedule-avoid-spills.ll
…
schedule-barrier-fpmode.mir
…
schedule-barrier-latency.mir
[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutation (#168500)
2025-11-19 17:49:14 +09:00
schedule-barrier.mir
…
schedule-fs-loop-nested-if.ll
…
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-ilp-liveness-tracking.mir
…
schedule-ilp.ll
…
schedule-ilp.mir
…
schedule-kernel-arg-loads.ll
…
schedule-pending-queue.mir
[AMDGPU] Examine instructions in pending queues during scheduling (#147653)
2025-10-16 08:46:29 -07:00
schedule-physregdeps.mir
…
schedule-regpressure-ilp-metric-spills.mir
…
schedule-regpressure-lds.ll
…
schedule-regpressure-limit2.ll
…
schedule-regpressure-limit3.ll
…
schedule-regpressure-limit-clustering.ll
…
schedule-regpressure-limit.ll
…
schedule-regpressure-misched-max-waves.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
schedule-regpressure-no-unclustered-regions.mir
[AMDGPU] Avoid changing minOccupancy if unclustered schedule was not run for any region. (#162025)
2025-11-12 10:11:22 -08:00
schedule-regpressure.mir
…
schedule-relaxed-occupancy.ll
…
schedule-vs-if-nested-loop-failure.ll
…
schedule-vs-if-nested-loop.ll
…
schedule-xdl-resource.ll
…
scheduler-handle-move-bundle.mir
…
scheduler-rp-calc-one-successor-two-predecessors-bug.ll
AMDGPU: Replace some undef uses in tests (#166813)
2025-11-06 11:08:16 -08:00
scheduler-subrange-crash.ll
…
scratch-buffer.ll
…
scratch-pointer-sink.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
scratch-simple.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
sdag-print-divergence.ll
[AMDGPU] TableGen-erate SDNode descriptions (#168248)
2025-11-17 00:10:07 +00:00
sdiv64.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
sdiv.ll
[AMDGPU] 32-bit ABS is a legal DAG node (#163907)
2025-10-17 16:11:59 -05:00
sdivrem24.ll
…
sdivrem64.r600.ll
…
sdwa-commute.ll
…
sdwa-cse.mir
…
sdwa-gfx9.mir
…
sdwa-op64-test.ll
…
sdwa-ops.mir
…
sdwa-peephole-cndmask-fail.ll
…
sdwa-peephole-cndmask-sext.ll
…
sdwa-peephole-cndmask-wave32.mir
…
sdwa-peephole-cndmask-wave64.mir
…
sdwa-peephole-instr-combine-sel-dst.mir
…
sdwa-peephole-instr-combine-sel-src.mir
…
sdwa-peephole-instr-combine-sel.ll
…
sdwa-peephole-instr-combine-sel.mir
…
sdwa-peephole-instr-gfx10.mir
…
sdwa-peephole-instr.mir
…
sdwa-peephole.ll
…
sdwa-preserve.mir
…
sdwa-scalar-ops.mir
…
sdwa-stack.mir
…
sdwa-vop2-64bit.mir
…
select64.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
select-cmp-shared-constant-fp.ll
…
select-cmp-shared-constant-int.ll
…
select-constant-cttz.ll
…
select-constant-xor.ll
…
select-fabs-fneg-extract-legacy.ll
…
select-fabs-fneg-extract.f16.ll
AMDGPU: Ignore type legality in isFAbsFree (#177630)
2026-01-23 19:43:23 +01:00
select-fabs-fneg-extract.legal.f16.ll
…
select-fabs-fneg-extract.ll
…
select-fabs-fneg-extract.v2f16.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
select-flags-to-fmin-fmax.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
select-i1.ll
…
select-load-to-load-select-ptr-combine.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
select-opt.ll
…
select-phi-s16-fp.ll
…
select-undef.ll
…
select-vectors.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
select.f16.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
select.ll
…
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
…
selectcc.ll
…
sema-v-unsched-bundle.ll
…
sendmsg-m0-hazard.mir
…
set_kill_i1_for_floation_point_comparison.ll
…
set-dx10.ll
…
set-gpr-idx-peephole.mir
[AMDGPU] Skip debug instructions when eliminating S_SET_GPR_IDX_ON/OFF (#160715)
2025-11-04 12:03:16 +00:00
set-inactive-wwm-overwrite.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
set-wave-priority.ll
…
setcc64.ll
…
setcc-equivalent.ll
…
setcc-fneg-constant.ll
…
setcc-limit-load-shrink.ll
…
setcc-multiple-use.ll
…
setcc-opt.ll
…
setcc-sext.ll
…
setcc.ll
…
seto.ll
…
setuo.ll
…
sext-divergence-driven-isel.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
sext-eliminate.ll
…
sext-in-reg-failure-r600.ll
…
sext-in-reg-vector-shuffle.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
sext-in-reg.ll
…
sgpr-control-flow.ll
…
sgpr-copy-duplicate-operand.ll
…
sgpr-copy-local-cse.ll
…
sgpr-copy.ll
[InstSimplify] Simplify fcmp implied by dominating fcmp (#161090)
2025-10-05 16:15:51 +08:00
sgpr-count-graphics.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
sgpr-phys-copy.mir
[AMDGPU] Enable saving SHARED_BASE to VCC (#163244)
2025-10-13 15:38:28 -05:00
sgpr-regalloc-flags.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
sgpr-spill-dead-frame-in-dbg-value.mir
…
sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
…
sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
…
sgpr-spill-incorrect-fi-bookkeeping-bug.ll
…
sgpr-spill-no-vgprs.ll
…
sgpr-spill-overlap-wwm-reserve.mir
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
sgpr-spill-partially-undef.mir
…
sgpr-spill-to-vmem-scc-clobber-unhandled.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
sgpr-spill-to-vmem-scc-clobber.mir
…
sgpr-spill-update-only-slot-indexes.ll
…
sgpr-spill-vmem-large-frame.mir
…
sgpr-spill-wrong-stack-id.mir
…
sgpr-spill.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
sgpr-spills-empty-prolog-block.mir
…
sgpr-spills-split-regalloc.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
sgpr-to-vreg1-copy.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
sgpr-to-vreg1-copy.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
sgprcopies.ll
…
shader-addr64-nonuniform.ll
…
shared-op-cycle.ll
…
shift-and-i64-ubfe.ll
[AMDGPU] Ensure divergence for v_alignbit (#129159)
2025-09-26 10:55:56 -07:00
shift-and-i128-ubfe.ll
…
shift-i64-opts.ll
…
shift-i128.ll
…
shift-select.ll
…
shl64_reduce_flags.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
shl64_reduce.ll
…
shl_add_constant.ll
…
shl_add_ptr_csub.ll
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
2025-12-05 12:37:33 +00:00
shl_add_ptr_global.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
shl_add_ptr.ll
…
shl_add.ll
…
shl_or.ll
…
shl-add-to-add-shl.ll
…
shl.ll
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
shl.v2i16.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
shlN_add.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
should-not-hoist-set-inactive.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
shrink-add-sub-constant.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
shrink-carry.mir
…
shrink-fma-f64.mir
…
shrink-i32-kimm.mir
…
shrink-instructions-flags.mir
…
shrink-instructions-illegal-fold.mir
…
shrink-instructions-implicit-vcclo.mir
…
shrink-insts-scalar-bit-ops.mir
[AMDGPU] When shrinking and/or to bitset*, remove implicit scc def (#168128)
2025-11-15 09:21:43 -06:00
shrink-mad-fma-fake16.mir
…
shrink-mad-fma-gfx10.mir
…
shrink-mad-fma.mir
…
shrink-true16.mir
…
shrink-v-cmp-wave32-dead-vcc-lo.mir
…
shrink-vop3-carry-out.mir
…
shufflevector-physreg-copy.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
shufflevector.v2bf16.v2bf16.ll
…
shufflevector.v2bf16.v3bf16.ll
…
shufflevector.v2bf16.v4bf16.ll
…
shufflevector.v2bf16.v8bf16.ll
…
shufflevector.v2f16.v2f16.ll
…
shufflevector.v2f16.v3f16.ll
…
shufflevector.v2f16.v4f16.ll
…
shufflevector.v2f16.v8f16.ll
…
shufflevector.v2f32.v2f32.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2f32.v3f32.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2f32.v4f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2f32.v8f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i16.v2i16.ll
…
shufflevector.v2i16.v3i16.ll
…
shufflevector.v2i16.v4i16.ll
…
shufflevector.v2i16.v8i16.ll
…
shufflevector.v2i32.v2i32.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2i32.v3i32.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2i32.v4i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i32.v8i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i64.v2i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i64.v3i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i64.v4i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i64.v8i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2p0.v2p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2p0.v3p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2p0.v4p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2p3.v2p3.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2p3.v3p3.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2p3.v4p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2p3.v8p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3bf16.v2bf16.ll
…
shufflevector.v3bf16.v3bf16.ll
…
shufflevector.v3bf16.v4bf16.ll
…
shufflevector.v3f16.v2f16.ll
…
shufflevector.v3f16.v3f16.ll
…
shufflevector.v3f16.v4f16.ll
…
shufflevector.v3f32.v2f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3f32.v3f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3f32.v4f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i16.v2i16.ll
…
shufflevector.v3i16.v3i16.ll
…
shufflevector.v3i16.v4i16.ll
…
shufflevector.v3i32.v2i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i32.v3i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i32.v4i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i64.v2i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i64.v3i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i64.v4i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p0.v2p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p0.v3p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p0.v4p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p3.v2p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p3.v3p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p3.v4p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4bf16.v2bf16.ll
…
shufflevector.v4bf16.v3bf16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4bf16.v4bf16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4f16.v2f16.ll
…
shufflevector.v4f16.v3f16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4f16.v4f16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4f32.v2f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4f32.v3f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4f32.v4f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i16.v2i16.ll
…
shufflevector.v4i16.v3i16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4i16.v4i16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4i32.v2i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i32.v3i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i32.v4i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i64.v2i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i64.v3i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i64.v4i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p0.v2p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p0.v3p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p0.v4p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p3.v2p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p3.v3p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p3.v4p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
si-annotate-cf-kill.ll
…
si-annotate-cf-noloop.ll
…
si-annotate-cf-unreachable.ll
…
si-annotate-cf.ll
…
si-annotate-cfg-loop-assert.ll
…
si-annotate-dbg-info.ll
…
si-annotate-nested-control-flows.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
si-annotatecfg-multiple-backedges.ll
…
si-fix-sgpr-copies-av-constrain.mir
AMDGPU: Constrain readfirstlane operand when writing to m0 (#168004)
2025-11-14 17:18:43 +00:00
si-fix-sgpr-copies-copy-to-sgpr.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
si-fix-sgpr-copies.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
si-fold-aligned-agprs.mir
AMDGPU: Stop special casing aligned VGPR targets in operand folding (#155559)
2025-09-02 16:15:25 +00:00
si-fold-aligned-vgprs.mir
AMDGPU: Stop special casing aligned VGPR targets in operand folding (#155559)
2025-09-02 16:15:25 +00:00
si-fold-copy-kills.mir
…
si-fold-kimm.mir
…
si-fold-operands-agpr-copy-reg-sequence.mir
AMDGPU: Avoid using exact class check in reg_sequence AGPR fold (#156135)
2025-09-03 09:05:48 +09:00
si-fold-operands-commute-same-operands-assert.mir
…
si-fold-operands-requires-ssa.mir
…
si-fold-operands-subreg-imm.gfx942.mir
…
si-fold-operands-subreg-imm.mir
…
si-fold-reg-sequence.mir
…
si-fold-scalar-clamp.mir
…
si-i1-copies.mir
…
si-init-whole-wave.mir
…
si-instr-info-correct-implicit-operands.ll
…
si-instr-info-vopc-exec.mir
…
si-lower-control-flow-kill.ll
…
si-lower-control-flow-preserve-dom-tree.mir
[AMDGPU] Fix DomTree preservation in SILowerControlFlow when nodes are removed (#176691)
2026-01-25 09:45:44 +05:30
si-lower-control-flow-unreachable-block.ll
…
si-lower-control-flow.mir
…
si-lower-i1-copies-order-of-phi-incomings.mir
…
si-lower-i1-copies.mir
…
si-lower-sgpr-spills-vgpr-lanes-usage.mir
…
si-lower-sgpr-spills.mir
…
si-lower-wwm-copies.mir
…
si-opt-vgpr-liverange-bug-deadlanes.mir
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
si-optimize-vgpr-live-range-dbg-instr.ll
…
si-optimize-vgpr-live-range-dbg-instr.mir
…
si-pre-allocate-wwm-regs.mir
…
si-pre-allocate-wwwmregs-dbg-noreg.mir
[AMDGPU] Fixed llvm-debuginfo-analyzer for AMDGPU. (#145125)
2025-08-12 22:04:52 +00:00
si-scheduler-exports.ll
…
si-scheduler.ll
…
si-sgpr-spill.ll
…
si-spill-cf.ll
…
si-split-load-store-alias-info.ll
[AMDGPU] Propagate AA info in vector load/store splitting. (#168871)
2025-11-24 03:30:35 +00:00
si-triv-disjoint-mem-access.ll
…
si-unify-exit-multiple-unreachables.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
si-unify-exit-return-unreachable.ll
…
si-vector-hang.ll
…
sibling-call.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
sign_extend.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
simple-indirect-call-2.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
simple-indirect-call.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
simplify-libcall-nobuiltin-def.ll
…
simplify-libcalls2.ll
…
simplify-libcalls.ll
…
simplifydemandedbits-recursion.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
simulated-trap-pseudo-expand.ll
[AMDGPU] Fix insertSimulatedTrap to return correct continuation block (#174774)
2026-01-21 11:52:38 +05:30
sink-addr-memory-intrinsics.ll
[CodeGenPrepare] Consider target memory intrinics as memory use (#159638)
2025-09-19 14:18:21 -07:00
sink-after-control-flow-postra.mir
…
sink-after-control-flow.mir
…
sink-image-sample.ll
…
sint_to_fp.f64.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
sint_to_fp.i64.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
sint_to_fp.ll
…
sitofp.f16.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
skip-branch-taildup-ret.mir
…
skip-branch-trap.ll
…
skip-fold-regsequence.mir
…
skip-if-dead.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
skip-promote-alloca-vector-users.ll
…
smed3.ll
…
smem-no-clause-coalesced.mir
…
smem-war-hazard.mir
…
smfmac_alloc_failure_no_agpr_O0.ll
AMDGPU: Track minNumAGPRs in MFI instead of mayUseAGPRs (#161996)
2025-10-07 08:48:45 +09:00
smfmac_no_agprs.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
sminmax.ll
…
sminmax.v2i16.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
smrd_vmem_war.ll
…
smrd-fold-offset.mir
…
smrd-gfx10.ll
…
smrd-vccz-bug.ll
…
smrd.ll
…
snippet-copy-bundle-regression.mir
…
soft-clause-dbg-value.mir
…
soft-clause-exceeds-register-budget.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
sopk-compares.ll
…
sopk-no-literal.ll
…
speculative-execution-freecasts.ll
…
spill192.mir
…
spill224.mir
…
spill288.mir
…
spill320.mir
…
spill352.mir
…
spill384.mir
…
spill_kill_v16.mir
[AMDGPU] Support true16 spill restore with sram-ecc (#165320)
2025-10-29 12:35:01 -07:00
spill_more_than_wavesize_csr_sgprs.ll
…
spill-agpr-partially-undef.mir
…
spill-agpr.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
spill-agpr.mir
…
spill-alloc-sgpr-init-bug.ll
…
spill-before-exec.mir
Revert "[RegAlloc] Relax the split constrain on MBB prolog" (#169990)
2025-11-29 08:01:23 -05:00
spill-cfg-position.ll
…
spill-csr-frame-ptr-reg-copy.ll
…
spill-empty-live-interval.mir
…
spill-m0.ll
…
spill-offset-calculation.ll
…
spill-partial-csr-sgpr-live-ins.mir
…
spill-reg-tuple-super-reg-use.mir
…
spill-regpressure-less.mir
…
spill-restore-partial-copy.mir
[AMDGPU] Use implicit operand to preserve liveness of COPY (#164911)
2025-10-27 10:47:11 -07:00
spill-scavenge-offset.ll
Revert "[RegAlloc] Relax the split constrain on MBB prolog" (#169990)
2025-11-29 08:01:23 -05:00
spill-sgpr-csr-live-ins.mir
…
spill-sgpr-stack-no-sgpr.ll
…
spill-sgpr-to-virtual-vgpr.mir
…
spill-sgpr-used-for-exec-copy.mir
…
spill-special-sgpr.mir
…
spill-to-agpr-partial.mir
[AMDGPU] Use implicit operand to preserve liveness of COPY (#164911)
2025-10-27 10:47:11 -07:00
spill-vector-superclass.ll
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
spill-vgpr-block.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
spill-vgpr-to-agpr-update-regscavenger.ll
[AMDGPU] Stop optimising readfirstlane in pass AMDGPUUniformIntrinsicCombine (#166955)
2025-11-08 01:17:39 +05:30
spill-vgpr-to-agpr.ll
…
spill-vgpr.ll
…
spill-wait.mir
…
spill-wide-sgpr.ll
…
spill-writelane-vgprs.ll
…
spillv16.ll
[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#168852)
2025-11-25 10:11:04 +01:00
spillv16.mir
[AMDGPU] Support true16 spill restore with sram-ecc (#165320)
2025-10-29 12:35:01 -07:00
split-arg-dbg-value.ll
…
split-liverange-overlapping-copies.mir
…
split-mbb-lis-subrange.mir
…
split-scalar-i64-add.ll
…
split-smrd.ll
…
split-vector-memoperand-offsets.ll
…
splitkit-copy-bundle.mir
…
splitkit-copy-live-lanes.mir
…
splitkit-do-not-undo-subclass-split-with-remat.mir
…
splitkit-getsubrangeformask.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
splitkit-nolivesubranges.mir
…
splitkit.mir
…
sra.ll
…
sram-ecc-default.ll
[AMDGPU] gfx1250 sram-ecc feature codegen tests. NFC. (#155293)
2025-08-25 14:32:29 -07:00
sramecc-subtarget-feature-any.ll
[AMDGPU] gfx1250 sram-ecc feature codegen tests. NFC. (#155293)
2025-08-25 14:32:29 -07:00
sramecc-subtarget-feature-disabled.ll
…
sramecc-subtarget-feature-enabled.ll
[AMDGPU] gfx1250 sram-ecc feature codegen tests. NFC. (#155293)
2025-08-25 14:32:29 -07:00
sreg-xnull-regclass-bitwidth.mir
…
srem64.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
srem-seteq-illegal-types.ll
…
srem.ll
[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)
2025-10-22 08:42:29 -05:00
srl64_reduce_flags.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
srl64_reduce.ll
…
srl.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
sroa-before-unroll.ll
…
SRSRC-GIT-clobber-check.mir
…
ssubo.ll
…
ssubsat.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
stack-passed-subdword-arg-crash-issue157997.ll
AMDGPU: Fix returning wrong type for stack passed sub-dword arguments (#158002)
2025-09-12 10:50:03 +09:00
stack-pointer-offset-relative-frameindex.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
stack-realign-kernel.ll
…
stack-realign.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
stack-size-overflow.ll
…
stack-slot-color-sgpr-vgpr-spills.mir
…
stackguard.ll
CodeGen: Fix crash when no libcall is available for stackguard (#164211)
2025-10-23 10:40:40 +09:00
stacksave_stackrestore.invalid.ll
…
stacksave_stackrestore.ll
…
stale-livevar-in-twoaddr-pass.mir
…
statepoint-asm-printer.mir
AMDGPU: Avoid crashing on statepoint-like pseudoinstructions (#170657)
2025-12-29 19:08:08 +01:00
statepoint-insert-waitcnts.mir
AMDGPU: Avoid crashing on statepoint-like pseudoinstructions (#170657)
2025-12-29 19:08:08 +01:00
stop-tail-duplicate-cfg-intrinsic.mir
…
store_typed.ll
…
store-barrier.ll
…
store-clobbers-load.ll
[AMDGPU][LIT][NFC] Adding -mtriple for AMDGPUAnnotateUniformValues Pass tests (#156437)
2025-09-03 15:32:28 +05:30
store-global.ll
…
store-hi16.ll
…
store-local.96.ll
…
store-local.128.ll
…
store-local.ll
…
store-private.ll
…
store-to-constant.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
store-v3i64.ll
…
store-vector-ptrs.ll
…
store-weird-sizes.ll
[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)
2025-10-02 10:06:25 +02:00
stress-calls.ll
…
strict_fadd.f16.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fadd.f32.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fadd.f64.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fma.f16.ll
…
strict_fma.f32.ll
…
strict_fma.f64.ll
…
strict_fmul.f16.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fmul.f32.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fmul.f64.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fpext.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
strict_fptrunc.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
strict_fsub.f16.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_FSUB (#173929)
2025-12-30 09:20:51 -08:00
strict_fsub.f32.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_FSUB (#173929)
2025-12-30 09:20:51 -08:00
strict_fsub.f64.ll
[AMDGPU] Update strict floating point tests to be more comprehensive (#169578)
2025-11-25 21:15:42 -08:00
strict_ldexp.f16.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_STRICT_FLDEXP (#177525)
2026-01-23 10:49:14 -08:00
strict_ldexp.f32.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_STRICT_FLDEXP (#177525)
2026-01-23 10:49:14 -08:00
strict_ldexp.f64.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_STRICT_FLDEXP (#177525)
2026-01-23 10:49:14 -08:00
strictfp_f16_abi_promote.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
structurize1.ll
…
structurize-hoist.ll
[StructurizeCFG] nested-if zerocost hoist bugfix (#155408)
2025-08-28 09:04:14 -05:00
structurize.ll
…
sub64-low-32-bits-known-zero.ll
…
sub_i1.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
sub_u64.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
sub-zext-cc-zext-cc.ll
…
sub.i16.ll
…
sub.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
sub.v2i16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
subreg_interference.mir
…
subreg-coalescer-crash.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
subreg-coalescer-undef-use.ll
…
subreg-eliminate-dead.ll
…
subreg-intervals.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
subreg-split-live-in-error.mir
[RegAlloc] Account for use availability when applying rematerializable weight discount (#159180)
2025-09-26 07:57:12 +08:00
subreg-undef-def-with-other-subreg-defs.mir
AMDGPU: Start using RegClassByHwMode for wavesize operands
2025-11-11 15:07:59 -08:00
subvector-test.mir
…
swdev282079.ll
…
swdev282079.mir
…
swdev373493.ll
…
swdev380865.ll
[DAGCombiner] Relax nsz constraint for FP optimizations (#165011)
2025-12-09 12:07:46 +02:00
swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
[RegAlloc] Account for use availability when applying rematerializable weight discount (#159180)
2025-09-26 07:57:12 +08:00
swdev503538-move-to-valu-stack-srd-physreg.ll
…
swdev504645-global-fold.ll
…
swdev-549940.ll
[AMDGPU] Rematerialize VGPR candidates when SGPR spills results in VGPR Excess (#168079)
2026-01-16 09:08:55 +01:00
switch-default-block-unreachable.ll
…
switch-unreachable.ll
…
swizzle-export.ll
…
swizzle.bit.extract.ll
…
syncscopes.ll
…
tail-call-amdgpu-gfx.ll
…
tail-call-cgp.ll
…
tail-call-inreg-arguments.convergencetokens.ll
…
tail-call-inreg-arguments.error.ll
…
tail-call-inreg-arguments.ll
…
tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
…
tail-call-uniform-target-in-vgprs-issue110930.ll
…
tail-dup-bundle.mir
…
tail-duplication-convergent.ll
…
target-cpu.ll
…
target-mem-intrinsic-metadata.ll
…
tex-clause-antidep.ll
…
texture-input-merge.ll
…
tgsplit.ll
…
threeaddr-wmma.mir
…
tid-kd-xnack-any.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
tid-kd-xnack-off.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
tid-kd-xnack-on.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
tid-mul-func-xnack-all-any.ll
…
tid-mul-func-xnack-all-not-supported.ll
…
tid-mul-func-xnack-all-off.ll
…
tid-mul-func-xnack-all-on.ll
…
tid-mul-func-xnack-any-off-1.ll
…
tid-mul-func-xnack-any-off-2.ll
…
tid-mul-func-xnack-any-on-1.ll
…
tid-mul-func-xnack-any-on-2.ll
…
tid-mul-func-xnack-invalid-any-off-on.ll
…
tid-one-func-xnack-any.ll
…
tid-one-func-xnack-not-supported.ll
…
tid-one-func-xnack-off.ll
…
tid-one-func-xnack-on.ll
…
tied-op-for-wwm-scratch-reg-spill-restore.mir
…
token-factor-inline-limit-test.ll
…
track-spilled-vgpr-liveness.mir
…
trans-coexecution-hazard.mir
…
trans-forwarding-hazards.mir
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
transform-block-with-return-to-epilog.ll
…
trap-abis.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
trap.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
triton_regression_no_waterfall.ll
…
triton_regression_no_waterfall.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
triv-disjoint-mem-access-neg-offset.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
true16-fold.mir
AMDGPU: Delete redundant recursive copy handling code (#157032)
2025-11-05 18:01:12 -08:00
true16-imm-folded-to-0-regression.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
true16-ra-pre-gfx11-regression-test.mir
…
true16-saveexec.mir
…
trunc-bitcast-vector.ll
…
trunc-cmp-constant.ll
…
trunc-combine.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
trunc-store-f64-to-f16.ll
AMDGPU: Fix truncstore from v6f32 to v6f16 (#171212)
2025-12-08 22:46:36 +00:00
trunc-store-i1.ll
…
trunc-store-i64.ll
…
trunc-store-vec-i16-to-i8.ll
…
trunc-store.ll
AMDGPU: Fix truncstore from v6f32 to v6f16 (#171212)
2025-12-08 22:46:36 +00:00
trunc-vector-store-assertion-failure.ll
…
trunc.ll
…
truncate-lshr-cast-build-vector-combine.ll
…
tti-unroll-prefs.ll
…
tuple-allocation-failure.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
twoaddr-bundle.mir
CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (#166213)
2025-11-12 22:04:46 +00:00
twoaddr-constrain.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
twoaddr-fma-f64.mir
…
twoaddr-fma.mir
…
twoaddr-mad.mir
…
twoaddr-regsequence.mir
…
twoaddr-wmma.mir
AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)
2025-11-20 16:25:47 -08:00
uaddo.ll
[AMDGPU] Delete redundant s_or_b32 (#165261)
2025-11-07 09:27:20 -06:00
uaddsat.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
udiv64.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
udiv.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
udivrem24.ll
…
udivrem64.r600.ll
…
udivrem.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
uint_to_fp.f64.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
uint_to_fp.i64.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
uint_to_fp.ll
…
uitofp.f16.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
umed3.ll
…
umin-sub-to-usubo-select-combine.ll
AMDGPU: Add baseline test for #161651 (#165921)
2025-10-31 21:50:17 +00:00
unaligned-buffer.ll
…
unaligned-load-store.ll
…
unallocatable-bundle-regression.mir
…
undef-build-vector.ll
…
undef-copy-propagation.mir
…
undef-handling-crash-in-ra.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
undef-subreg-use-after-coalesce.mir
…
undefined-physreg-sgpr-spill.mir
…
undefined-subreg-liverange.ll
…
unexpected-reg-unit-state.mir
…
unfold-masked-merge-scalar-variablemask.ll
…
unhandled-loop-condition-assertion.ll
…
uniform_branch_with_floating_point_cond.ll
…
uniform-alignbit.ll
[AMDGPU] Ensure divergence for v_alignbit (#129159)
2025-09-26 10:55:56 -07:00
uniform-branch-intrinsic-cond.ll
…
uniform-cfg.ll
…
uniform-crash.ll
…
uniform-load-from-tid.ll
[AMDGPU] Mark workitem IDs uniform in more cases (#152581)
2025-08-29 01:21:04 -05:00
uniform-loop-inside-nonuniform.ll
…
uniform-phi-with-undef.ll
…
uniform-select.ll
[AMDGPU] Use reverse iteration in CodeGenPrepare (#145484)
2025-10-10 13:00:40 +02:00
uniform-vgpr-to-sgpr-return.ll
…
uniform-work-group-attribute-missing.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
uniform-work-group-multistep.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
uniform-work-group-nested-function-calls.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
uniform-work-group-prevent-attribute-propagation.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
uniform-work-group-propagate-attribute.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
uniform-work-group-recursion-test.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
uniform-work-group-test.ll
AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)
2025-10-08 01:25:50 +09:00
unigine-liveness-crash.ll
…
unknown-processor.ll
…
unnamed-function-resource-info.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
unpack-half.ll
…
unpack-non-coissue-insts-post-ra-scheduler.mir
[AMDGPU]: Packed instructions unpacking to co-issue post-RA scheduling - fix flag handling (#160195)
2025-10-10 08:56:38 -07:00
unroll.ll
…
unspill-vgpr-after-rewrite-vgpr-mfma.ll
Greedy: Take copy hints involving subregisters (#159570)
2025-09-19 09:37:36 +09:00
unstructured-cfg-def-use-issue.ll
…
unsupported-atomics.ll
…
unsupported-calling-conv-call.ll
…
unsupported-calling-conv-func.ll
…
unsupported-calls.ll
…
unsupported-cc.ll
…
unsupported-code-object-version.ll
…
unsupported-cs-chain.ll
…
unsupported-image-a16.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
unsupported-image-g16.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
unsupported-image-sample.ll
…
update-lds-alignment.ll
…
update-phi.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
urem64.ll
[AMDGPU] Delete redundant s_or_b32 (#165261)
2025-11-07 09:27:20 -06:00
urem-seteq-illegal-types.ll
…
urem.ll
…
use_restore_frame_reg.mir
…
use-after-free-after-cleanup-failed-vreg.ll
RenameIndependentSubregs: try to only implicit def used subregs (#167486)
2025-11-20 09:28:34 +09:00
use-sgpr-multiple-times.ll
…
usubo.ll
[AMDGPU] Delete redundant s_or_b32 (#165261)
2025-11-07 09:27:20 -06:00
usubsat.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
v1i64-kernel-arg.ll
…
v1024.ll
…
v_add_u64_pseudo_sdwa.ll
[AMDGPU] Skip debug uses in SIPeepholeSDWA (#160092)
2025-09-22 14:40:00 +01:00
v_ashr_pk.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
v_cmp_gfx11.ll
…
v_cndmask.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
v_cvt_pk_u8_f32.ll
…
v_mac_f16.ll
[TargetLowering] Remove NoSignedZerosFPMath uses (#160975)
2025-09-29 14:33:56 +08:00
v_mac.ll
[TargetLowering] Remove NoSignedZerosFPMath uses (#160975)
2025-09-29 14:33:56 +08:00
v_madak_f16.ll
…
v_mov_b64_expand_and_shrink.mir
…
v_mov_b64_expansion.mir
…
v_pack.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
v_sat_pk_u8_i16.ll
[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)
2025-10-17 14:29:37 -04:00
v_sub_u64_pseudo_sdwa.ll
…
v_swap_b16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
v_swap_b32.mir
[AMDGPU] Skip debug instructions in SIShrinkInstructions::matchSwap (#160123)
2025-09-23 09:36:09 +01:00
valu-i1.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
valu-mask-write-hazard-true16.mir
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
valu-mask-write-hazard.mir
[AMDGPU] Fix test after #169378
2025-11-25 12:17:17 +00:00
valu-read-sgpr-hazard-attrs.mir
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
valu-read-sgpr-hazard.mir
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
vccz-corrupt-bug-workaround.mir
…
vcmp-saveexec-to-vcmpx-set-kill.mir
…
vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
…
vcmp-saveexec-to-vcmpx.ll
…
vcmp-saveexec-to-vcmpx.mir
…
vcmpx-exec-war-hazard.mir
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
vcmpx-permlane16var-hazard.mir
…
vcmpx-permlane-hazard-sdwa.mir
…
vcmpx-permlane-hazard.mir
…
vector_range_metadata.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
vector_rebroadcast.ll
[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)
2025-10-17 14:29:37 -04:00
vector_shuffle.packed.ll
[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)
2025-10-17 14:29:37 -04:00
vector-alloca-addrspacecast.ll
[InstCombine] Strip leading zero indices from GEP (#155415)
2025-09-01 09:58:11 +02:00
vector-alloca-atomic.ll
AMDGPU: Generalize and normalize some tests to avoid future churn (#170508)
2025-12-03 17:11:05 +00:00
vector-alloca-bitcast.ll
AMDGPU: Generalize and normalize some tests to avoid future churn (#170508)
2025-12-03 17:11:05 +00:00
vector-alloca-limits.ll
…
vector-alloca.ll
…
vector-extract-insert.ll
…
vector-legalizer-divergence.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
vector-reduce-add.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
vector-reduce-and.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
vector-reduce-fadd.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
vector-reduce-fmax.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
vector-reduce-fmaximum.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
vector-reduce-fmin.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
vector-reduce-fminimum.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
vector-reduce-fmul.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
vector-reduce-mul.ll
Reland "[AMDGPU][GlobalISel] Add RegBankLegalize support for G_MUL (#… (#177481)
2026-01-22 14:59:52 -08:00
vector-reduce-or.ll
DAG: Use poison for unused shuffle operands in legalizer (#177578)
2026-01-23 18:20:56 +01:00
vector-reduce-smax.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
vector-reduce-smin.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
vector-reduce-umax.ll
DAG: Use poison for unused shuffle operands in legalizer (#177578)
2026-01-23 18:20:56 +01:00
vector-reduce-umin.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
vector-reduce-xor.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
vector-spill-restore-to-other-vector-type.mir
[AMDGPU] Use implicit operand to preserve liveness of COPY (#164911)
2025-10-27 10:47:11 -07:00
vectorize-buffer-fat-pointer.ll
…
vectorize-global-local.ll
…
vectorize-loads.ll
…
vectorize-unroll-metadata.ll
…
verifier-sdwa-cvt.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-constant-bus-violations.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-ds-gws-align.mir
AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)
2025-11-25 18:55:34 +00:00
verify-duplicate-literal.mir
…
verify-gfx12-gds.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-gfx90a-aligned-vgprs.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-image-vaddr-align.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-image.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-scalar-store.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-sop.mir
…
verify-vimage-vsample.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-vopd-gfx12.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-vopd.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
vertex-fetch-encoding.ll
…
vgpr_constant64_to_sgpr.mir
…
vgpr_constant_to_sgpr.ll
…
vgpr-agpr-limit-gfx90a.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-blocks-funcinfo.mir
…
vgpr-count-compute.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-count-graphics-chain.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-count-graphics.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-descriptor-waterfall-loop-idom-update.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
vgpr-large-tuple-alloc-error.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
vgpr-limit-gfx1250.ll
Revert "[AMDGPU] Allow amdgpu-waves-per-eu to lower target occupancy range" (#177544)
2026-01-23 08:55:14 +00:00
vgpr-liverange-ir.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
vgpr-liverange.ll
…
vgpr-lowering-gfx1250-t16.mir
[AMDGPU] Fix wrong MSB encoding for V_FMAMK instructions (#168107)
2025-11-14 22:50:17 +00:00
vgpr-lowering-gfx1250.mir
[AMDGPU] Do not use s_delay_alu instskip to skip s_set_vgpr_msb (#175925)
2026-01-20 10:59:55 +00:00
vgpr-mark-last-scratch-load.ll
…
vgpr-mark-last-scratch-load.mir
…
vgpr-remat-v_pk_mov_b32.mir
…
vgpr-remat.mir
AMDGPU: Add pseudoinstruction for 64-bit agpr or vgpr constants (#154499)
2025-08-20 22:54:37 +09:00
vgpr-set-msb-coissue.mir
[AMDGPU] Fix typo in LowerVGPREncoding to allow it to hoist past waitcnt instructions (#176355)
2026-01-16 13:52:47 +00:00
vgpr-setreg-mode-swar.mir
[AMDGPU] Handle s_setreg_imm32_b32 targeting MODE register (#174681)
2026-01-09 14:43:41 -05:00
vgpr-spill-dead-frame-in-dbg-value.mir
…
vgpr-spill-emergency-stack-slot-compute.ll
…
vgpr-spill-emergency-stack-slot.ll
Revert "[LICM] Sink unused l-invariant loads in preheader. #157559"
2025-11-14 14:51:33 +01:00
vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
…
vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
…
vgpr-spill-placement-issue61083.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
vgpr-spill-scc-clobber.mir
…
vgpr-spill.mir
…
vgpr-tuple-allocation.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
vi-removed-intrinsics.ll
…
virtregrewrite-undef-identity-copy.mir
…
visit-physreg-vgpr-imm-folding-bug.ll
…
vmem-to-salu-hazard.mir
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
vmem-vcc-hazard.mir
…
vni8-across-blocks.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
vni8-live-reg-opt.ll
…
vop-shrink-frame-index.mir
…
vop-shrink-non-ssa.mir
…
vop-shrink.ll
…
vopc_dpp-true16.mir
…
vopc_dpp.ll
…
vopc_dpp.mir
…
vopd-combine-gfx1250.mir
[AMDGPU] Fix VGPR lowering for V_DUAL_FMAMK_F32 (#170567)
2025-12-03 15:12:26 -08:00
vopd-combine.mir
…
vopd-src2acc-delay.mir
…
vselect64.ll
…
vselect.ll
…
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait-before-stores-with-scope_sys.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
wait-before-stores-with-scope_sys.mir
[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#168852)
2025-11-25 10:11:04 +01:00
wait-xcnt-atomic-rmw-optimization.ll
[AMDGPU][GFX1250] Optimize s_wait_xcnt for back-to-back atomic RMWs (#177620)
2026-01-24 08:21:41 +05:30
wait-xcnt.mir
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
wait.ll
…
waitcnt-agpr.mir
…
waitcnt-back-edge-loop.mir
…
waitcnt-bvh.mir
…
waitcnt-debug-non-first-terminators.mir
…
waitcnt-debug-output-crash.ll
[AMDGPU] Fix crash in SIInsertWaitcnts debug output (#175518)
2026-01-12 14:48:53 +00:00
waitcnt-debug.mir
[AMDGPU] Readd assertions requirement to test after #170468
2025-12-04 02:24:52 +00:00
waitcnt-flat.ll
…
waitcnt-func-global-inv.mir
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
waitcnt-gfx1250.mir
[AMDGPU] High VGPR waitcnt generation tests. NFC. (#157533)
2025-09-08 16:13:27 -07:00
waitcnt-global-inv-wb.mir
…
waitcnt-kmcnt-scc-different-block.mir
[AMDGPU][SIInsertWaitcnts] Track SCC. Insert KM_CNT waits for SCC writes. (#157843)
2025-09-18 14:41:01 +02:00
waitcnt-loop-ds-prefetch-pattern.ll
[AMDGPU] Add DS loop waitcnt optimization for GFX12+ (#172728)
2026-01-12 13:34:02 -08:00
waitcnt-loop-irreducible.mir
…
waitcnt-loop-opt.mir
[AMDGPU] Add DS loop waitcnt optimization for GFX12+ (#172728)
2026-01-12 13:34:02 -08:00
waitcnt-loop-single-basic-block.mir
…
waitcnt-looptest.ll
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
waitcnt-meta-instructions.mir
…
waitcnt-multiple-funcs.mir
…
waitcnt-no-redundant.mir
…
waitcnt-overflow.mir
…
waitcnt-permute.mir
…
waitcnt-preexisting-vscnt.mir
[AMDGPU] Reenable BackOffBarrier on GFX11/12 (#155370)
2025-09-02 09:37:43 +02:00
waitcnt-preexisting.mir
…
waitcnt-sample-out-order.mir
…
waitcnt-sample-waw.mir
…
waitcnt-skip-meta.mir
…
waitcnt-trailing.mir
…
waitcnt-unscoped.ll
[AMDGPU] Remove scope check in SIInsertWaitcnts::generateWaitcntInstBefore (#157821)
2025-09-12 14:51:36 -04:00
waitcnt-vinterp.mir
…
waitcnt-vmcnt-loop.mir
[AMDGPU] Skip debug uses in SIInsertWaitcnts::shouldFlushVmCnt (#160818)
2025-09-26 08:39:11 +01:00
waitcnt-vmem-waw.mir
…
waitcnt-vscnt.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
waitcnt-vscnt.mir
…
waitcnt.mir
…
waterfall_kills_scc.ll
…
waterfall-call-target-av-register-failure.ll
AMDGPU: Fix verifier error when waterfall call target is in AV register (#168017)
2025-11-14 09:49:40 -08:00
wave32.ll
AMDGPU: Add pattern for copysign of 0 (#172699)
2025-12-18 11:34:24 +01:00
wave_dispatch_regs.ll
…
while-break.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
whole-wave-functions-pei.mir
[AMDGPU] Tail call support for whole wave functions (#145860)
2025-09-04 10:34:43 +02:00
whole-wave-functions.ll
[AMDGPU] Fix typo in LowerVGPREncoding to allow it to hoist past waitcnt instructions (#176355)
2026-01-16 13:52:47 +00:00
whole-wave-register-copy.ll
…
whole-wave-register-spill.ll
[AMDGPU] Remove odd syntax in some RUN lines. NFC. (#169831)
2025-11-27 17:00:54 +00:00
widen_extending_scalar_loads.ll
…
widen-smrd-loads.ll
…
widen-vselect-and-mask.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
wmma_modifiers.ll
…
wmma_multiple_32.ll
…
wmma_multiple_64.ll
…
wmma-coececution-valu-hazards.mir
Reapply "[AMDGPU] Rework the clamp support for WMMA instructions" (#174674) (#174697)
2026-01-07 06:12:19 +00:00
wmma-gfx12-convergent.mir
[AMDGPU] Mark WMMA machine instructions as convergent (#165602)
2025-11-04 15:37:27 -06:00
wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
…
wmma-gfx12-w32-imm.ll
…
wmma-gfx12-w32-iu-modifiers.ll
…
wmma-gfx12-w32-swmmac-index_key.ll
…
wmma-gfx12-w32.ll
…
wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
…
wmma-gfx12-w64-imm.ll
…
wmma-gfx12-w64-iu-modifiers.ll
…
wmma-gfx12-w64-swmmac-index_key.ll
…
wmma-gfx12-w64.ll
…
wmma-hazards-gfx12-w32.mir
…
wmma-hazards-gfx12-w64.mir
…
wmma-hazards-gfx1250-w32.mir
Reapply "[AMDGPU] Rework the clamp support for WMMA instructions" (#174674) (#174697)
2026-01-07 06:12:19 +00:00
wmma-hazards.mir
…
wmma-nop-hoisting.mir
[AMDGPU] Pre-commit test for WMMA NOP hoisting optimization (#176745)
2026-01-20 11:37:49 +05:30
workgroup-id-in-arch-sgprs.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
workitem-intrinsic-opts.ll
[AMDGPU] Invert scc uses to delete s_cmp_eq* (#167382)
2026-01-14 10:24:24 -06:00
wqm-gfx11.ll
…
wqm-terminators.mir
…
wqm.ll
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
wqm.mir
…
write_register.ll
…
write-register-invalid-register.ll
…
write-register-vgpr-into-sgpr.ll
…
wrong-transalu-pos-fix.ll
…
wwm-reg-shift-down-gfx11plus.mir
…
wwm-regalloc-error.ll
…
wwm-reserved-spill.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
wwm-reserved.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
wwm-spill-superclass-pseudo.mir
…
xfail.r600.bitcast.ll
…
xnack-subtarget-feature-any.ll
…
xnack-subtarget-feature-disabled.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
xnack-subtarget-feature-enabled.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
xnor.ll
…
xor3-i1-const.ll
[InstCombine] Optimize redundant floating point comparisons in or/and inst's (#158097)
2025-09-16 20:52:11 +05:30
xor3.ll
…
xor_add.ll
…
xor-r600.ll
…
xor.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
zero_extend.ll
…
zext-divergence-driven-isel.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
zext-i64-bit-operand.ll
…
zext-lid.ll
…

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.