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llvm-project/llvm/test/CodeGen/AMDGPU
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michaelselehov 621fc8774e
[AMDGPU] Implement LSR cost model for GFX9+ (#184138) 
AMDGPU previously had no target-specific LSR cost model, so the generic
heuristic would often introduce extra induction variables and base-add
chains that hurt VALU throughput on GFX9+ (observed on gfx942).

Implement a custom cost model:

- isLSRCostLess(): prioritize per-iteration instruction count over setup
costs, penalize IV multiplies, and demote register count. Pre-GFX9 falls
back to the default comparator.
- getScalingFactorCost(): report that base+scale*index addressing
requires an extra ADD instruction.
- isNumRegsMajorCostOfLSR(): return false.
- shouldDropLSRSolutionIfLessProfitable(): return true.

Assisted-by: Claude Opus
2026-03-23 12:18:11 +01:00
..
GlobalISel
[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn.class (#178827)
2026-03-20 12:50:06 -07:00
32-bit-local-address-space.ll
…
a-v-ds-atomic-cmpxchg.ll
AMDGPU: Add agpr variants of multi-data DS instructions (#156420)
2025-09-04 09:13:36 +09:00
a-v-ds-atomicrmw.ll
AMDGPU: Add tests for atomics with AGPR operands (#155820)
2025-08-28 22:21:07 +09:00
a-v-flat-atomic-cmpxchg.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
a-v-flat-atomicrmw.ll
[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
2026-02-25 15:24:54 -08:00
a-v-global-atomic-cmpxchg.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
a-v-global-atomicrmw.ll
[AMDGPU] Align loop headers to prevent instruction fetch split on GFX950 (#181999)
2026-02-19 14:18:44 -05:00
aa-as-infer.ll
…
aa-points-to-constant-memory.ll
…
abi-attribute-hints-undefined-behavior.ll
…
abs_i16.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
abs_i32.ll
[AMDGPU] 32-bit abs is not legal on R600 (#164103)
2025-10-18 20:47:40 -05:00
absdiff.ll
[AMDGPU] Lower S_ABSDIFF_I32 to VALU instructions (#167691)
2025-11-13 14:35:44 +01:00
acc-ldst.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
accvgpr-copy.mir
…
accvgpr-spill-scc-clobber.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
add3.ll
…
add64-low-32-bits-known-zero.ll
…
add_i1.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
add_i64.ll
[AMDGPU] Update codegen tests for PR #154069 (#154862)
2025-08-22 07:58:21 -06:00
add_i128.ll
…
add_shl.ll
…
add_sub_u64_pseudos.mir
…
add_u64.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
add-debug.ll
…
add-max.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
add.i16.ll
…
add.ll
…
add.v2i16.ll
[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)
2025-10-17 14:29:37 -04:00
addrspacecast-captured.ll
…
addrspacecast-constantexpr.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
addrspacecast-gas.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
addrspacecast-initializer-unsupported.ll
…
addrspacecast-initializer.ll
…
addrspacecast-known-non-null.ll
…
addrspacecast.gfx6.ll
AMDGPU/GlobalISel: Lower G_EXTRACT/INSERT in legalizer (#181036)
2026-03-12 10:03:44 -07:00
addrspacecast.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
addrspacecast.r600.ll
…
addsub64_carry.ll
[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)
2025-10-22 08:42:29 -05:00
adjust-writemask-cse.ll
…
adjust-writemask-invalid-copy.ll
…
adjust-writemask-vectorized.ll
…
agpr-copy-no-free-registers-assertion-after-ra-failure.ll
…
agpr-copy-no-free-registers.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
agpr-copy-no-vgprs.mir
…
agpr-copy-propagation.mir
AMDGPU: Stop handling AGPR case in getCrossCopyRegClass (#161800)
2025-10-06 23:34:39 +09:00
agpr-copy-reuse-writes.mir
…
agpr-copy-sgpr-no-vgprs.mir
…
agpr-csr.ll
…
agpr-register-count.ll
…
agpr-remat.ll
…
agpr-spill-copy.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
agpr-to-agpr-copy.mir
…
alignbit-pat.ll
[AMDGPU] Ensure divergence for v_alignbit (#129159)
2025-09-26 10:55:56 -07:00
alloc-aligned-tuples-gfx90a.mir
…
alloc-aligned-tuples-gfx908.mir
…
alloc-aligned-tuples-gfx1250.mir
…
alloc-all-regs-reserved-in-class.mir
…
alloca.ll
…
allow-check.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
always-uniform.ll
…
amd.endpgm.ll
AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_endpgm (#186217)
2026-03-13 10:42:38 -07:00
amdgcn-call-whole-wave.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
[AMDGPU] Fixup 30219f0f4300 (#170266)
2025-12-02 10:16:53 +01:00
amdgcn-ieee.ll
[NFC][AMDGPU] Precommit test amdgcn-ieee.ll (#163118)
2025-10-13 07:00:57 -04:00
amdgcn-load-offset-from-reg.ll
…
amdgcn-sin-cos-f16-f32.ll
[AMDGPU][GlobalIsel] Add register bank legalization rules for amdgcn sin cos intrinsics. (#185934)
2026-03-13 07:35:45 -05:00
amdgcn.bitcast.16bit.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
amdgcn.bitcast.32bit.ll
AMDGPU: Perform zero/any extend combine into permute (#177370)
2026-01-28 10:47:22 -06:00
amdgcn.bitcast.48bit.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
amdgcn.bitcast.64bit.ll
AMDGPU: Perform zero/any extend combine into permute (#177370)
2026-01-28 10:47:22 -06:00
amdgcn.bitcast.96bit.ll
AMDGPU: Perform zero/any extend combine into permute (#177370)
2026-01-28 10:47:22 -06:00
amdgcn.bitcast.128bit.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
amdgcn.bitcast.160bit.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
amdgcn.bitcast.192bit.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
amdgcn.bitcast.224bit.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
amdgcn.bitcast.256bit.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
amdgcn.bitcast.288bit.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
amdgcn.bitcast.320bit.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
amdgcn.bitcast.352bit.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
amdgcn.bitcast.384bit.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
amdgcn.bitcast.448bit.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
amdgcn.bitcast.512bit.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
amdgcn.bitcast.576bit.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
amdgcn.bitcast.640bit.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
amdgcn.bitcast.704bit.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
amdgcn.bitcast.768bit.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
amdgcn.bitcast.832bit.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
amdgcn.bitcast.896bit.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
amdgcn.bitcast.960bit.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
amdgcn.bitcast.1024bit.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
amdgcn.bitcast.ptr.ll
…
amdgcn.private-memory.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
amdgpu-alias-analysis.ll
…
amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
amdgpu-attributor-flat-scratch-init-asan.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
amdgpu-attributor-intrinsic-missing-nocallback.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
amdgpu-attributor-min-agpr-alloc.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
amdgpu-attributor-nocallback-intrinsics.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
amdgpu-attributor-trap-leaf.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
amdgpu-branch-weight-metadata.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
amdgpu-codegenprepare-break-large-phis-heuristics.ll
[AMDGPU] Use reverse iteration in CodeGenPrepare (#145484)
2025-10-10 13:00:40 +02:00
amdgpu-codegenprepare-break-large-phis.ll
…
amdgpu-codegenprepare-fdiv.f64.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
amdgpu-codegenprepare-fdiv.ll
AMDGPU: Stop requiring afn for f32 rsq formation (#172082)
2025-12-23 18:16:15 +01:00
amdgpu-codegenprepare-fold-binop-select.ll
[AMDGPU] 32-bit ABS is a legal DAG node (#163907)
2025-10-17 16:11:59 -05:00
amdgpu-codegenprepare-idiv.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
amdgpu-codegenprepare-log.ll
AMDGPU: Use fpmath metadata on f16 log/log10 intrinsics (#180489)
2026-02-17 09:58:43 +01:00
amdgpu-codegenprepare-mul24.ll
…
amdgpu-codegenprepare-sqrt.ll
…
amdgpu-cs-chain-cc.ll
[AMDGPU] Make chain functions receive a stack pointer (#184616)
2026-03-06 11:01:42 +01:00
amdgpu-cs-chain-fp-nosave.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
amdgpu-cs-chain-preserve-cc.ll
[AMDGPU] Make chain functions receive a stack pointer (#184616)
2026-03-06 11:01:42 +01:00
amdgpu-export-kernel-runtime-handles.ll
…
amdgpu-function-calls-option.ll
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amdgpu-inline.ll
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amdgpu-late-codegenprepare-crash-splat.ll
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amdgpu-late-codegenprepare.ll
…
amdgpu-libcall-sincos-pass-ordering.ll
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amdgpu-llvm-debuginfo-analyzer.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
amdgpu-lower-exec-sync-and-module-lds.ll
[AMDGPU] Add s_wakeup_barrier instruction for gfx1250 (#170501)
2025-12-10 09:45:13 +01:00
amdgpu-lower-exec-sync-and-sw-lds.ll
[AMDGPU] Add amdgpu-lower-exec-sync pass to lower named-barrier globals (#165692)
2025-11-17 10:08:40 +05:30
amdgpu-lower-exec-sync.ll
[AMDGPU] Add s_wakeup_barrier instruction for gfx1250 (#170501)
2025-12-10 09:45:13 +01:00
amdgpu-max-num-workgroups-load-annotate.ll
Reapply "AMDGPU: Annotate group size ABI loads with range metadata (#185420)" (#185588)
2026-03-10 07:41:26 +00:00
amdgpu-miscellaneous-uniform-intrinsic.ll
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
amdgpu-mul24-knownbits.ll
…
amdgpu-no-agprs-violations.ll
…
amdgpu-nsa-threshold.ll
…
amdgpu-num-agpr.ll
…
amdgpu-prepare-agpr-alloc.mir
AMDGPU: Start using AV_MOV_B64_IMM_PSEUDO (#154500)
2025-08-22 13:59:36 +09:00
amdgpu-reloc-const.ll
…
amdgpu-shader-calling-convention.ll
…
amdgpu-simplify-libcall-ceil.ll
…
amdgpu-simplify-libcall-copysign.ll
…
amdgpu-simplify-libcall-exp2.ll
…
amdgpu-simplify-libcall-exp.ll
…
amdgpu-simplify-libcall-fabs.ll
…
amdgpu-simplify-libcall-floor.ll
…
amdgpu-simplify-libcall-fma.ll
…
amdgpu-simplify-libcall-fmax-splat.ll
…
amdgpu-simplify-libcall-fmax.ll
…
amdgpu-simplify-libcall-fmin-splat.ll
…
amdgpu-simplify-libcall-fmin.ll
…
amdgpu-simplify-libcall-image-function-signatures.ll
…
amdgpu-simplify-libcall-ldexp-splat.ll
…
amdgpu-simplify-libcall-ldexp.ll
…
amdgpu-simplify-libcall-log2.ll
…
amdgpu-simplify-libcall-log10.ll
…
amdgpu-simplify-libcall-log.ll
…
amdgpu-simplify-libcall-mad.ll
…
amdgpu-simplify-libcall-pow-codegen.ll
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135)
2026-02-19 11:49:32 +01:00
amdgpu-simplify-libcall-pow-fast.ll
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135)
2026-02-19 11:49:32 +01:00
amdgpu-simplify-libcall-pow.ll
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135)
2026-02-19 11:49:32 +01:00
amdgpu-simplify-libcall-pown-fast.ll
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135)
2026-02-19 11:49:32 +01:00
amdgpu-simplify-libcall-pown.ll
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135)
2026-02-19 11:49:32 +01:00
amdgpu-simplify-libcall-powr-fast.ll
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135)
2026-02-19 11:49:32 +01:00
amdgpu-simplify-libcall-powr.ll
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135)
2026-02-19 11:49:32 +01:00
amdgpu-simplify-libcall-rint.ll
…
amdgpu-simplify-libcall-rootn-codegen.ll
AMDGPU: Fix selection failure on fast vector rootn (#185035)
2026-03-09 10:22:47 +00:00
amdgpu-simplify-libcall-rootn-fast.ll
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135)
2026-02-19 11:49:32 +01:00
amdgpu-simplify-libcall-rootn.ll
AMDGPU: Fix selection failure on fast vector rootn (#185035)
2026-03-09 10:22:47 +00:00
amdgpu-simplify-libcall-round.ll
…
amdgpu-simplify-libcall-sincos.defined.ll
…
amdgpu-simplify-libcall-sincos.defined.nobuiltin.ll
…
amdgpu-simplify-libcall-sincos.defined.sin.cos.ll
…
amdgpu-simplify-libcall-sincos.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
amdgpu-simplify-libcall-sincos.nobuiltins.ll
…
amdgpu-simplify-libcall-sincos.weak.ll
…
amdgpu-simplify-libcall-sqrt.ll
…
amdgpu-simplify-libcall-tdo-acos.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-acosh.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-acospi.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-asin.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-asinh.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-asinpi.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-atan.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-atanh.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-atanpi.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-cbrt.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-cos.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-cosh.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-cospi.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-erf.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-erfc.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-exp2.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-exp10.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-exp.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-expm1.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-log2.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-log10.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-log.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-rsqrt.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-sin.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-sinh.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-sinpi.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-sqrt.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-tan.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-tanh.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-tanpi.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-tdo-tgamma.ll
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
2026-03-04 08:42:44 +01:00
amdgpu-simplify-libcall-trunc.ll
…
amdgpu-simplify-libcall-unexpected-types.ll
…
amdgpu-simplify-uniform-waterfall.ll
[AMDGPU] Stop optimising readfirstlane in pass AMDGPUUniformIntrinsicCombine (#166955)
2025-11-08 01:17:39 +05:30
amdgpu-snop-padding.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-dynamic-indirect-access.ll
…
amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-dynamic-lds-test.ll
…
amdgpu-sw-lower-lds-lower-all.ll
…
amdgpu-sw-lower-lds-lower-none.ll
…
amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
…
amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access.ll
…
amdgpu-sw-lower-lds-multiple-blocks-return-asan.ll
…
amdgpu-sw-lower-lds-multiple-blocks-return.ll
…
amdgpu-sw-lower-lds-non-kernel-declaration.ll
…
amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
…
amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-dynamic-lds-test.ll
…
amdgpu-sw-lower-lds-static-indirect-access-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-indirect-access-function-param.ll
…
amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
…
amdgpu-sw-lower-lds-static-indirect-access-lower-none.ll
…
amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
…
amdgpu-sw-lower-lds-static-indirect-access-nested.ll
…
amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
…
amdgpu-sw-lower-lds-static-indirect-access.ll
…
amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-lds-O0.ll
…
amdgpu-sw-lower-lds-static-lds-test-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
[AMDGPU] Add nocreateundeforpoison annotations (#166450)
2026-01-02 10:12:58 -08:00
amdgpu-sw-lower-lds-static-lds-test.ll
…
amdgpu-sw-lower-lds-static-lds-vector-ptrs.ll
…
amdgpu-uniform-intrinsic-combine.ll
[InstCombine] Canonicalize GEP source element types (#180745)
2026-03-06 14:48:01 +00:00
amdgpu-uniform-temporal-divergence.ll
[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)
2025-10-30 12:32:32 +05:30
amdgpu-unroll-threshold.ll
…
amdgpu.private-memory.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
amdgpu.work-item-intrinsics.deprecated.ll
…
amdhsa-kernarg-preload-num-sgprs.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
amdhsa-trap-num-sgprs.ll
…
amdpal_scratch_mergedshader.ll
…
amdpal-callable.ll
[AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (#182107)
2026-03-04 12:16:41 +01:00
amdpal-chain-metadata.ll
[AMDGPU] Stop treating AMDGPU_CS_ChainPreserve as a module entry funtion (#183718)
2026-03-01 09:33:22 +08:00
amdpal-cs.ll
…
amdpal-elf.ll
…
amdpal-es.ll
…
amdpal-gs.ll
…
amdpal-hs.ll
…
amdpal-ls.ll
…
amdpal-metadata-agpr-register-count.ll
…
amdpal-msgpack-cs.ll
…
amdpal-msgpack-default.ll
[AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (#182107)
2026-03-04 12:16:41 +01:00
amdpal-msgpack-denormal.ll
[AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (#182107)
2026-03-04 12:16:41 +01:00
amdpal-msgpack-dx10-clamp-on.ll
[AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (#182107)
2026-03-04 12:16:41 +01:00
amdpal-msgpack-dx10-clamp.ll
[AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (#182107)
2026-03-04 12:16:41 +01:00
amdpal-msgpack-es.ll
…
amdpal-msgpack-gs.ll
…
amdpal-msgpack-hs.ll
…
amdpal-msgpack-ieee.ll
[AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (#182107)
2026-03-04 12:16:41 +01:00
amdpal-msgpack-ls.ll
…
amdpal-msgpack-ps.ll
…
amdpal-msgpack-psenable.ll
…
amdpal-msgpack-vs.ll
…
amdpal-ps.ll
…
amdpal-psenable.ll
…
amdpal-usersgpr-init.ll
…
amdpal-vs.ll
…
amdpal.ll
…
and_or.ll
…
and-gcn.ll
…
and.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
and.r600.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
andorbitset.ll
…
andorn2.ll
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
2025-09-03 20:04:01 +01:00
andorxorinvimm.ll
…
annotate-existing-abi-attributes.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
annotate-kernel-features-hsa-call.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
annotate-kernel-features-hsa.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
annotate-kernel-features.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
annotate-noclobber.ll
…
anonymous-gv.ll
…
any_extend_vector_inreg.ll
[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (#165295)
2025-11-11 13:14:48 -06:00
anyext.ll
[AMDGPU] Use "v_bfi_b32 x, 0, z" to implement (z & ~x) (#156636)
2025-09-03 11:00:03 +00:00
arbitrary-fp-to-float.ll
[SelectionDAG] Add expansion for llvm.convert.from.arbitrary.fp (#179318)
2026-03-04 10:40:47 +01:00
are-loads-from-same-base-ptr.ll
…
array-ptr-calc-i32.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
array-ptr-calc-i64.ll
…
artificial-terminators.mir
…
ashr64_reduce_flags.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
ashr64_reduce.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
ashr.v2i16.ll
…
asm-printer-check-vcc.mir
…
async-buffer-loads.ll
[AMDGPU] Introduce asyncmark/wait intrinsics (#180467)
2026-02-11 07:15:51 +00:00
asyncmark-err.ll
[AMDGPU] Introduce asyncmark/wait intrinsics (#180467)
2026-02-11 07:15:51 +00:00
asyncmark-max-pregfx12.ll
[AMDGPU] Introduce asyncmark/wait intrinsics (#180467)
2026-02-11 07:15:51 +00:00
asyncmark-pregfx12.ll
[AMDGPU] fix asyncmark soft waitcnt bug (#184851)
2026-03-06 11:38:32 -08:00
asyncmark-waitcnt.mir
[AMDGPU] fix asyncmark soft waitcnt bug (#184851)
2026-03-06 11:38:32 -08:00
at-least-one-def-value-assert.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
atomic_cmp_swap_local.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
atomic_load_add.ll
…
atomic_load_local.ll
[AMDGPU] Use true16 loads with +real-true16 and sram-ecc (#161256)
2025-10-07 09:31:07 -07:00
atomic_load_sub.ll
…
atomic_optimization_split_dt_update.ll
…
atomic_optimizations_buffer.ll
ValueTracking/AMDGPU: handle mbcnt in computeKnownBitsFromOperator (#183229)
2026-03-02 10:48:15 +08:00
atomic_optimizations_global_pointer.ll
Revert "[AMDGPU] Generate more swaps" (#187723)
2026-03-20 12:03:20 -05:00
atomic_optimizations_local_pointer.ll
ValueTracking/AMDGPU: handle mbcnt in computeKnownBitsFromOperator (#183229)
2026-03-02 10:48:15 +08:00
atomic_optimizations_pixelshader.ll
ValueTracking/AMDGPU: handle mbcnt in computeKnownBitsFromOperator (#183229)
2026-03-02 10:48:15 +08:00
atomic_optimizations_raw_buffer.ll
ValueTracking/AMDGPU: handle mbcnt in computeKnownBitsFromOperator (#183229)
2026-03-02 10:48:15 +08:00
atomic_optimizations_struct_buffer.ll
ValueTracking/AMDGPU: handle mbcnt in computeKnownBitsFromOperator (#183229)
2026-03-02 10:48:15 +08:00
atomic_store_local.ll
[AMDGPU] Use true16 loads with +real-true16 and sram-ecc (#161256)
2025-10-07 09:31:07 -07:00
atomic-optimizer-promote-i8.ll
…
atomic-optimizer-strict-wqm.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
atomicrmw_usub_cond.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
atomicrmw_usub_sat.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
atomicrmw-bf16-gfx11plus.ll
…
atomicrmw-expand.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
atomicrmw-nand.ll
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
2025-09-03 20:04:01 +01:00
atomics_cond_sub.ll
AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)
2025-12-09 23:13:33 +00:00
atomics-cas-remarks-gfx90a.ll
…
atomics-hw-remarks-gfx90a.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
atomics-system-scope.ll
AMDGPU: Fix constrain register logic for physregs (#161794)
2025-10-03 21:20:36 +09:00
attr-amdgpu-align.ll
[AMDGPU] Apply alignment attr for make.buffer.rsrc (#166914)
2025-12-08 12:48:54 +08:00
attr-amdgpu-flat-work-group-size-vgpr-limit.ll
[AMDGPU] Make the options consistent across 3 RA pipelines(NFC) (#184190)
2026-03-03 11:22:24 +05:30
attr-amdgpu-flat-work-group-size.ll
…
attr-amdgpu-max-num-workgroups-propagate.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
attr-amdgpu-max-num-workgroups.ll
…
attr-amdgpu-num-sgpr.ll
…
attr-amdgpu-num-vgpr.ll
…
attr-amdgpu-num-workgroups_error_check.ll
…
attr-amdgpu-waves-per-eu.ll
Revert "[AMDGPU] Allow amdgpu-waves-per-eu to lower target occupancy range" (#177544)
2026-01-23 08:55:14 +00:00
attr-unparseable.ll
…
attributor-flatscratchinit-globalisel.ll
…
attributor-flatscratchinit-undefined-behavior2.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
attributor-flatscratchinit-undefined-behavior.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
attributor-flatscratchinit.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
attributor-loop-issue-58639.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
attributor-noalias-addrspace.ll
Revert "[AMDGPU][Attributor] Infer inreg attribute in AMDGPUAttributor (#146720)"
2025-08-18 22:59:52 -04:00
attributor-noopt.ll
…
av_movimm_pseudo_expansion.mir
[AMDGPU] Emit b32 movs if (a)v_mov_b64_pseudo dest vgprs are misaligned (#160547)
2026-01-30 15:01:14 +00:00
av_spill_cross_bb_usage.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
av-spill-expansion-with-machine-cp.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
av-split-dead-valno-crash.ll
Reapply "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325) (#184114)
2026-03-02 14:47:35 +00:00
back-off-barrier-subtarget-feature.ll
[AMDGPU] BackOffBarrier feature added to gfx1250; Removed incorrect "DS Store drain" check. (#179818)
2026-02-19 08:41:44 -08:00
bad-agpr-vgpr-regalloc-priority.mir
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
barrier-elimination-gfx12.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_barrier/wave_barrier (#186512)
2026-03-16 08:55:07 -07:00
barrier-elimination.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_barrier/wave_barrier (#186512)
2026-03-16 08:55:07 -07:00
barrier-signal-wait-latency.ll
[AMDGPU] Schedule independent instructions between s_barrier_signal and s_barrier_wait (#172057)
2025-12-16 11:48:50 +05:30
basic-branch.ll
…
basic-call-return.ll
…
basic-loop.ll
…
bb-prolog-spill-during-regalloc.ll
…
bf16-conversions.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
bf16-math.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
bf16-ops.ll
…
bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
bfe_uint.ll
…
bfe-combine.ll
…
bfe-i8-i16.ll
[AMDGPU] Select v_bfe_u32 for i8/i16 (and (srl x, c), mask) (#182446)
2026-03-04 13:31:15 -06:00
bfe-patterns.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
bfi_int.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
bfi_int.r600.ll
…
bfi_nested.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
bfm.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
big_alu.ll
…
bit-op-reduce-width-known-bits.ll
…
bitcast_vector_bigint.ll
[AMDGPU] Select v_bfe_u32 for i8/i16 (and (srl x, c), mask) (#182446)
2026-03-04 13:31:15 -06:00
bitcast-constant-to-vector.ll
…
bitcast-v4f16-v4i16.ll
…
bitcast-vector-extract.ll
…
bitop3.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
bitreverse-inline-immediates.ll
…
bitreverse.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_BITREVERSE (#172101)
2025-12-15 17:45:33 -08:00
blender-coalescer-verifier-error-empty-subrange.mir
…
blender-no-live-segment-at-def-implicit-def.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
block-should-not-be-in-alive-blocks.mir
…
br_cc.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
branch-condition-and.ll
…
branch-folder-requires-no-phis.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
branch-folding-implicit-def-subreg.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
branch-relax-bundle.ll
…
branch-relax-indirect-branch.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
branch-relax-no-terminators.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
branch-relax-spill.ll
…
branch-relaxation-debug-info.mir
…
branch-relaxation-gfx10-branch-offset-bug.ll
…
branch-relaxation-gfx1250.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
branch-relaxation-inst-size-gfx10.ll
…
branch-relaxation-inst-size-gfx11.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
branch-relaxation-inst-size-gfx1250.mir
[AMDGPU] Fix instruction size for 64-bit literal constant operands (#180387)
2026-02-09 14:31:52 +00:00
branch-relaxation.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
branch-uniformity.ll
…
break-smem-soft-clauses.mir
…
break-vmem-soft-clauses.mir
…
bswap.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
buffer-atomic-fadd.f32-no-rtn.ll
…
buffer-atomic-fadd.f32-rtn.ll
[AMDGPU] Fix duplicate RUN lines in tests (#182286)
2026-02-19 16:07:20 +00:00
buffer-atomic-fadd.f64.ll
AMDGPU: Start to use AV classes for unknown vector class (#166482)
2025-11-13 09:28:33 -08:00
buffer-atomic-fadd.v2f16-no-rtn.ll
…
buffer-atomic-fadd.v2f16-rtn.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
buffer-fat-pointer-atomicrmw-fadd.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
buffer-fat-pointer-atomicrmw-fmax.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
buffer-fat-pointer-atomicrmw-fmin.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
buffer-fat-pointer-atomicrmw-usub_cond.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
buffer-fat-pointer-atomicrmw-usub_sat.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
buffer-fat-pointer-unsupported-errors.ll
[AMDGPU] Poison invalid globals after emitting error in LowerBufferFatPointers pass (#184662)
2026-03-10 15:35:27 +01:00
buffer-fat-pointers-contents-legalization.ll
[AMDGPU] Select v_bfe_u32 for i8/i16 (and (srl x, c), mask) (#182446)
2026-03-04 13:31:15 -06:00
buffer-fat-pointers-memcpy.ll
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
2025-12-03 11:13:52 +01:00
buffer-intrinsic-mmo-type.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
buffer-intrinsics-mmo-offsets.ll
…
buffer-rsrc-ptr-ops.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
buffer-schedule.ll
…
bug-cselect-b64.ll
…
bug-deadlanes.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
bug-multi-operands-to-update-after-fold.mir
…
bug-pk-f32-imm-fold.mir
[AMDGPU] Don't fold an i64 immediate value if it can't be replicated from its lower 32-bit (#168458)
2025-11-18 17:11:10 -05:00
bug-sdag-emitcopyfromreg.ll
…
bug-sdag-scheduler-cycle.ll
…
bug-undef-spilled-agpr.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
bug-v4f64-subvector.ll
…
bug-vopc-commute.ll
…
build_vector-r600.ll
…
build_vector.gfx11plus.ll
[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)
2025-09-04 18:08:18 -04:00
build_vector.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
build-vector-insert-elt-infloop.ll
…
build-vector-packed-partial-undef.ll
[AMDGPU][True16] extractEltcheap check 16bit in true16 mode (#171762)
2026-01-20 09:45:05 -05:00
bundle-breaks-phy-liveness.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
bundle-latency.mir
…
bypass-div.ll
[AMDGPU][ISel] Reduce 64-bit setcc to upper 32 bits if lower 32 bits are known (#181238)
2026-02-23 11:15:31 -07:00
byval-frame-setup.ll
…
call_fs.ll
…
call-alias-register-usage0.ll
…
call-alias-register-usage1.ll
…
call-alias-register-usage2.ll
…
call-alias-register-usage3.ll
…
call-alias-register-usage-agpr.ll
…
call-args-inreg-bfloat.ll
[AMDGPU] Fix caller/callee mismatch in SGPR assignment for inreg args (#182754)
2026-02-23 18:13:41 +00:00
call-args-inreg-no-sgpr-for-csrspill.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
call-args-inreg.ll
[AMDGPU] Fix caller/callee mismatch in SGPR assignment for inreg args (#182754)
2026-02-23 18:13:41 +00:00
call-argument-types.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
call-c-function.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-constant.ll
…
call-constexpr.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-defs-mode-register.ll
[DAG] Add strictfp implicit def reg after metadata. (#168282)
2025-11-17 10:57:21 +00:00
call-encoding.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-graph-register-usage.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-preserved-registers.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-reqd-group-size.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
call-return-types.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-skip.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-waitcnt.ll
[NFC][AMDGPU][GISel] Precommit GlobalISel specific tests for call instruction (#165898)
2025-11-07 10:10:17 -08:00
call-waw-waitcnt.mir
…
callbr-intrinsics.ll
[AMDGPU][GlobalISel] Fix / workaround amdgcn.kill/.unreachable lowering (#170639)
2025-12-04 13:42:53 +01:00
callbr.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
callee-frame-setup.ll
[AMDGPU] Update test to match comment. NFC (#187273)
2026-03-23 09:36:14 +00:00
callee-special-input-sgprs-fixed-abi.ll
…
callee-special-input-vgprs-packed.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
callee-special-input-vgprs.ll
[AMDGPU] callee-special-input-vgprs.ll / callee-special-input-vgprs-packed.ll - regenerate test coverage (#159587)
2025-09-18 15:19:48 +00:00
calling-conventions.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
captured-frame-index.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
carryout-selection.ll
[AMDGPU][ISel] Reduce 64-bit setcc to upper 32 bits if lower 32 bits are known (#181238)
2026-02-23 11:15:31 -07:00
cayman-loop-bug.ll
…
cc-entry.ll
[AMDGPU] Remove AMDGPUArgumentUsageInfo pass (#182490)
2026-02-23 18:47:01 +05:30
cc-inreg-sgpr0-3-mismatch.ll
[AMDGPU] Fix caller/callee mismatch in SGPR assignment for inreg args (#182754)
2026-02-23 18:13:41 +00:00
cc-sgpr-limit.ll
…
cc-sgpr-over-limit.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
cc-update.ll
…
cf_end.ll
…
cf-loop-on-constant.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
cf-stack-bug.ll
…
cgp-addressing-modes-flat.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
cgp-addressing-modes-gfx908.ll
…
cgp-addressing-modes-gfx1030.ll
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
2025-12-05 12:37:33 +00:00
cgp-addressing-modes-smem.ll
…
cgp-addressing-modes.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
cgp-bitfield-extract.ll
[AMDGPU] Ensure divergence for v_alignbit (#129159)
2025-09-26 10:55:56 -07:00
chain-hi-to-lo.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
chain-node-divergence-update-crash-issue-173885.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
change-scc-to-vcc.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
check-subtarget-features.ll
…
clamp-modifier.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
clamp-omod-special-case.mir
…
clamp.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
cluster_stores.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
cluster-dims.ll
[AMDGPU] Add the support for .cluster_dims code object metadata (#158721)
2025-09-15 16:13:07 -04:00
cluster-flat-loads-postra.mir
…
cluster-flat-loads.mir
…
cmp_shrink.mir
…
cndmask-no-def-vcc.ll
…
coalesce-copy-to-agpr-to-av-registers.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
coalesce-identity-copies-undef-subregs.mir
…
coalesce-into-dead-subreg-copies.mir
…
coalesce-liveout-undef-copy.mir
…
coalesce-vgpr-alignment.ll
…
coalescer_distribute.ll
…
coalescer_remat.ll
…
coalescer-avoid-coalesce-class-with-no-registers.ll
RegisterCoalescer: Do not introduce uses of empty register classes (#161809)
2025-10-10 04:01:04 +00:00
coalescer-avoid-coalesce-class-with-no-registers.mir
RegisterCoalescer: Do not introduce uses of empty register classes (#161809)
2025-10-10 04:01:04 +00:00
coalescer-early-clobber-subreg.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
coalescer-extend-pruned-subrange.mir
…
coalescer-identical-values-undef.mir
…
coalescer-remat-dead-use.mir
…
coalescer-removepartial-extend-undef-subrange.mir
…
coalescer-subranges-another-copymi-not-live.mir
…
coalescer-subranges-another-prune-error.mir
…
coalescer-subranges-prune-kill-copy.mir
…
coalescer-subreg-join.mir
…
coalescer-subregjoin-fullcopy.mir
…
coalescer-undef-subreg-use-invalid-lanemask.mir
…
coalescer-with-subregs-bad-identical.mir
…
coalescing_makes_lanes_undef.mir
Fix typos and spelling errors across codebase (#156270)
2026-01-13 11:52:46 -05:00
coalescing-subreg-was-undef-but-became-def.mir
…
coalescing-with-subregs-in-loop-bug.mir
…
code-object-v3.ll
…
code-size-estimate-gfx1250.ll
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
code-size-estimate.ll
[AMDGPU] Add asm comments if setreg changes MSBs (#185774)
2026-03-11 11:37:03 -07:00
code-size-estimate.mir
…
codegen-internal-only-func.ll
…
codegen-prepare-addrmode-sext.ll
…
codegen-prepare-addrspacecast-non-null-vector.ll
…
codegen-prepare-addrspacecast-non-null.ll
AMDGPU: Try to use zext to implement constant-32-bit addrspacecast (#168977)
2025-12-01 18:40:26 -05:00
collapse-endcf2.mir
…
collapse-endcf-broken.mir
…
collapse-endcf.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
collapse-endcf.mir
…
combine_andor_with_cmps_nnan.ll
[SelectionDAGBuilder] Remove NoNaNsFPMath uses (#169904)
2026-02-09 09:48:07 +08:00
combine_andor_with_cmps.ll
[SelectionDAG] Remove NoNaNsFPMath uses (#183448)
2026-03-10 14:06:42 +08:00
combine_vloads.ll
…
combine-add-zext-xor.ll
…
combine-and-sext-bool.ll
…
combine-cond-add-sub.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
combine-ftrunc.ll
…
combine-reg-or-const.ll
[AMDGPU] Optimize S_OR_B32 to S_ADDK_I32 where possible (#177949)
2026-02-07 09:10:12 +00:00
combine-sreg64-inits.mir
…
combine-vload-extract.ll
…
comdat.ll
…
commute_modifiers.ll
…
commute-compares-scalar-float.ll
…
commute-compares.ll
[AMDGPU][ISel] setcc peephole for comparisons with upper 32 bits of a 64-bit register pair (#177662)
2026-02-11 13:41:03 -07:00
commute-frame-index-operand.mir
…
commute-op-sel.mir
…
commute-shifts.ll
…
commute-vop3.mir
…
complex-folding.ll
[SDAG] Remove non-canonical fabs libcall handling (#177967)
2026-01-26 15:11:17 +00:00
compute-known-bits-nofpclass.ll
DAG: Handle AssertNoFPClass in computeKnownBits (#167289)
2025-11-10 08:56:08 -08:00
computeKnownBits-scalar-to-vector-crash.ll
…
computeNumSignBits-mul.ll
…
concat_vectors.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
constant-address-space-32bit.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
constant-fold-imm-immreg.mir
…
constant-fold-mi-operands.ll
…
constrained-shift.ll
…
control-flow-fastregalloc.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
control-flow-optnone.ll
…
convergence-laneops.ll
…
convergence-tokens.ll
…
convergent-inlineasm.ll
…
convergent.mir
[AMDGPU] Add basic verification for source modifiers (#186733)
2026-03-20 20:32:30 +01:00
copy_phys_vgpr64.mir
…
copy_to_scc.ll
…
copy-hoist-no-spills.ll
…
copy-illegal-type.ll
…
copy-overlap-sgpr-kill.mir
…
copy-overlap-vgpr-kill.mir
…
copy-phys-reg-implicit-operand-kills-subregs.mir
…
copy-to-reg-frameindex.ll
AMDGPU: Fix verifier error when waterfall call target is in AV register (#168017)
2025-11-14 09:49:40 -08:00
copy-to-reg-scc-clobber.ll
…
copy-to-reg.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
copy-vgpr-clobber-spill-vgpr.mir
…
copyprop_regsequence_with_undef.mir
…
copysign-simplify-demanded-bits.ll
DAG: Fold copysign with a known signmask to a disjoint or (#167266)
2025-11-10 08:55:45 -08:00
copysign-to-disjoint-or-combine.ll
DAG: Fix arith_fence handling in SignBitIsZeroFP (#172537)
2025-12-16 20:10:38 +00:00
couldnt-join-subrange-3.mir
…
cross-block-use-is-not-abi-copy.ll
…
cse-convergent.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
cse-phi-incoming-val.ll
…
csr-gfx10.ll
…
csr-sgpr-spill-live-ins.mir
…
ctlz_zero_undef.ll
AMDGPU/GlobalISel: RegBankLegalize rules for ctlz/cttz_zero_undef (#186546)
2026-03-16 10:21:47 -07:00
ctlz.ll
AMDGPU/GlobalISel: RegBankLegalize rules for FFBH/FFBL (#186017)
2026-03-13 11:00:07 -07:00
ctpop16.ll
[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)
2025-10-22 08:42:29 -05:00
ctpop64.ll
…
ctpop.ll
…
cttz_zero_undef.ll
AMDGPU/GlobalISel: RegBankLegalize rules for ctlz/cttz_zero_undef (#186546)
2026-03-16 10:21:47 -07:00
cttz.ll
[GISel] handle CTTZ in computeKnownBits (#181474)
2026-02-15 15:43:05 -08:00
cube.ll
…
cvt_f32_ubyte.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
cvt_flr_i32_f32.ll
[AMDGPU] Update patterns for v_cvt_flr and v_cvt_rpi (#177962)
2026-01-26 19:33:00 +01:00
cvt_rpi_i32_f32.ll
[AMDGPU] Update patterns for v_cvt_flr and v_cvt_rpi (#177962)
2026-01-26 19:33:00 +01:00
dag-divergence-atomic.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
dag-divergence.ll
Revert "SelectionDAG: Do not propagate divergence through glue (#174766)"
2026-01-07 14:23:15 +00:00
dag-preserve-disjoint-flag.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
dagcomb-extract-vec-elt-different-sizes.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
dagcomb-mullohi.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
dagcomb-shuffle-vecextend-non2.ll
…
dagcombine-fma-crash.ll
…
dagcombine-fma-fmad.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
dagcombine-fmul-sel.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
dagcombine-lshr-and-cmp.ll
…
dagcombine-reassociate-bug.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
dagcombine-reassociate-multi-memop.ll
[DAGCombiner] Fix crash in reassociationCanBreakAddressingModePattern for multi-memop nodes (#180268)
2026-02-10 13:53:36 -08:00
dagcombine-select.ll
[SelectionDAGBuilder] Remove NoNaNsFPMath uses (#169904)
2026-02-09 09:48:07 +08:00
dagcombine-setcc-select.ll
…
dagcombine-v1i8-extractvecelt-crash.ll
…
dagcombiner-bug-illegal-vec4-int-to-fp.ll
…
dbg-info-inline-at.ll
…
dbg-value-ends-sched-region.mir
…
dbg-value-starts-sched-region.mir
…
dce-disjoint-intervals.mir
…
dead_bundle.mir
…
dead_copy.mir
…
dead-lane.mir
…
dead-machine-elim-after-dead-lane.ll
…
debug_frame.ll
…
debug-independence-adjustSchedDependency.ll
[AMDGPU] Latency calculation must be independent of meta insts (#177052)
2026-01-21 12:19:55 -06:00
debug-independence-revertScheduling.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
debug-independence-scheduleRegion.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
debug-value2.ll
…
debug-value-scheduler-crash.mir
…
debug-value-scheduler-liveins.mir
…
debug-value-scheduler.mir
[AMDGPU][Scheduler] Simplify scheduling revert logic (#177203)
2026-02-01 17:55:12 +01:00
debug-value.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
debug.ll
…
default_amdhsa_code_object_version.ll
…
default-flat-work-group-size-overrides-waves-per-eu.ll
Revert "[AMDGPU] Allow amdgpu-waves-per-eu to lower target occupancy range" (#177544)
2026-01-23 08:55:14 +00:00
default-fp-mode.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
detect-dead-lanes.mir
…
direct-indirect-call.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
directive-amdgcn-target.ll
[AMDGPU] Add gfx12-5-generic subtarget (#183381)
2026-02-25 13:34:48 -08:00
disable_form_clauses.ll
…
disable-preload-kernargs.ll
[AMDGPU] Add an option to completely disable kernel argument preload (#153975)
2025-08-18 09:44:20 -04:00
disconnected-predset-break-bug.ll
…
div_i128.ll
[CodeGen] Expand power-of-2 div/rem at IR level in ExpandIRInsts. (#180654)
2026-02-25 22:54:34 +01:00
div_v2i128.ll
[CodeGen] Expand power-of-2 div/rem at IR level in ExpandIRInsts. (#180654)
2026-02-25 22:54:34 +01:00
div-rem-by-constant-64.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
diverge-extra-formal-args.ll
…
diverge-interp-mov-lower.ll
…
diverge-switch-default.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
divergence-at-use.ll
…
divergence-driven-abs.ll
…
divergence-driven-bfe-isel.ll
…
divergence-driven-bitreverse.ll
…
divergence-driven-buildvector.ll
[AMDGPU] Use FPImmLeaf for float constants, fix build_vector patterns (#178018)
2026-01-28 10:51:42 +01:00
divergence-driven-ctlz-cttz.ll
…
divergence-driven-ctpop.ll
…
divergence-driven-min-max.ll
…
divergence-driven-negsubinlineconst.ll
…
divergence-driven-not-isel.ll
…
divergence-driven-sext-inreg.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
divergence-driven-trunc-to-i1.ll
[AMDGPU][ISel] setcc peephole for comparisons with upper 32 bits of a 64-bit register pair (#177662)
2026-02-11 13:41:03 -07:00
divergence-driven-xnor.ll
…
divergent-branch-uniform-condition.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
divrem24-assume.ll
…
do-not-fold-copy.mir
…
do-not-unify-divergent-exit-nodes-with-musttail.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
dpp64_combine.ll
[AMDGPU] gfx1251 VOP3 dpp support (#159654)
2025-09-18 16:18:09 -07:00
dpp64_combine.mir
[AMDGPU] gfx1251 VOP1 dpp support (#159637)
2025-09-18 13:42:06 -07:00
dpp_combine_gfx11.mir
AMDGPU: Fix DPP combiner using isOperandLegal on incomplete inst (#155595)
2025-09-03 01:19:01 +09:00
dpp_combine_gfx1250.mir
[AMDGPU] Fix DPP combining into V_BITOP3_B32 (#153083)
2025-08-11 15:39:02 -07:00
dpp_combine-true16.mir
…
dpp_combine.ll
[AMDGPU] gfx1251 VOP2 dpp support (#159641)
2025-09-18 15:38:29 -07:00
dpp_combine.mir
…
drop-mem-operand-move-smrd.ll
…
ds_gws_align.ll
…
ds_permute_a_v.ll
AMDGPU: Define agpr versions of ds permute instructions (#156695)
2025-09-04 15:13:59 +09:00
ds_read2_offset_order.ll
…
ds_read2_superreg.ll
…
ds_read2-gfx1250.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
ds_read2.ll
…
ds_read2st64.ll
…
ds_write2_a_v.ll
Revert "CodeGen: Record MMOs in finalizeBundle" (#166520)
2025-11-05 11:11:08 +01:00
ds_write2.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
ds_write2st64.ll
…
ds-alignment.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
ds-combine-large-stride.ll
…
ds-combine-with-dependence.ll
…
ds-negative-offset-addressing-mode-loop.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
ds-read2-write2-debug-info.ll
AMDGPU: Use getMergedLocation in SILoadStoreOptimizer (#156396)
2025-11-10 15:04:24 -08:00
ds-sub-offset.ll
[DAG] Remove AssertZext if the input is masked (#146052)
2025-07-29 13:05:30 +02:00
ds-vectorization-alignment.ll
…
dst-sel-hazard.mir
[MIR] Support symbolic INLINEASM extra-info flags (#186818)
2026-03-17 11:08:28 +00:00
dual-source-blend-export.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
dummy-regalloc-priority-advisor.mir
…
dumpcode.ll
…
duplicate-attribute-indirect.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
dvgpr_sym_fail_too_many_block_size_16_anon.ll
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
dvgpr_sym_fail_too_many_block_size_16.ll
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
dvgpr_sym.ll
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
2025-08-15 16:33:06 +01:00
dwarf-multi-register-use-crash.ll
…
dynamic_stackalloc.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
dynamic-vgpr-reserve-stack-for-cwsr.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
early-if-convert-cost.ll
…
early-if-convert.ll
…
early-inline-alias.ll
…
early-inline.ll
…
early-lis-two-address-partial-def.mir
…
early-tailduplicator-nophis.mir
…
early-tailduplicator-terminator.mir
…
early-term.mir
…
eh_frame.ll
…
elf-header-flags-mach.ll
[AMDGPU] Add gfx12-5-generic subtarget (#183381)
2026-02-25 13:34:48 -08:00
elf-header-flags-sramecc.ll
[AMDGPU] Fix duplicate RUN lines in tests (#182286)
2026-02-19 16:07:20 +00:00
elf-header-flags-xnack.ll
…
elf-header-osabi.ll
…
elf-notes.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
elf.ll
…
elf.metadata.ll
…
elf.r600.ll
…
eliminate-frame-index-s-add-i32.mir
…
eliminate-frame-index-s-add-u32.mir
…
eliminate-frame-index-s-mov-b32.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
eliminate-frame-index-scalar-bit-ops.mir
…
eliminate-frame-index-select.ll
[AMDGPU] fix eliminateFrameIndex to use SGPR frame index (#178991)
2026-02-23 09:12:38 -06:00
eliminate-frame-index-select.mir
[AMDGPU] fix eliminateFrameIndex to use SGPR frame index (#178991)
2026-02-23 09:12:38 -06:00
eliminate-frame-index-v-add-co-u32-wave32.mir
…
eliminate-frame-index-v-add-co-u32.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
eliminate-frame-index-v-add-u32.mir
…
else.ll
…
emit-high-vgprs.mir
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
empty-function.ll
…
empty-text.ll
MC,AMDGPU: Don't pad .text with s_code_end if it would otherwise be empty (#147980)
2025-08-06 13:25:45 +01:00
enable-no-signed-zeros-fp-math.ll
…
enable-scratch-only-dynamic-stack.ll
…
endcf-loop-header.ll
…
endpgm-dce.mir
…
exceed-max-sgprs.ll
…
exec-mask-opt-cannot-create-empty-or-backward-segment.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
expand-atomicrmw-syncscope.ll
…
expand-scalar-carry-out-select-user.ll
[AMDGPU] Delete redundant s_or_b32 (#165261)
2025-11-07 09:27:20 -06:00
expand-si-indirect.mir
…
expand-variadic-call.ll
[IR] Remove size argument from lifetime intrinsics (#150248)
2025-08-08 11:09:34 +02:00
expand-waitcnt-profiling.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
expert_scheduling_gfx12.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
export-cluster-postra.mir
…
extend-bit-ops-i16.ll
…
extend-phi-subrange-not-in-parent.mir
…
extend-wwm-virt-reg-liveness.mir
…
extload-align.ll
…
extload-private.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
extload.ll
…
extra-lds-size.ll
[AMDGPU] update LDS block size for gfx1250 (#167614)
2025-11-17 16:03:47 -08:00
extra-sroa-after-unroll.ll
…
extract_subvector_vec4_vec3.ll
…
extract_vector_dynelt.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
extract_vector_elt-f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
extract_vector_elt-f64.ll
…
extract_vector_elt-i8.ll
…
extract_vector_elt-i16.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
extract_vector_elt-i64.ll
…
extract-load-i1.ll
…
extract-lowbits.ll
…
extract-subvector-16bit.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
extract-subvector-equal-length.ll
…
extract-subvector.ll
[AMDGPU][ISel] Reduce 64-bit setcc to upper 32 bits if lower 32 bits are known (#181238)
2026-02-23 11:15:31 -07:00
extract-vector-elt-build-vector-combine.ll
…
extractelt-to-trunc.ll
…
fabs-known-signbit-combine-fast-fdiv-lowering.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fabs-r600.ll
[SDAG] Remove non-canonical fabs libcall handling (#177967)
2026-01-26 15:11:17 +00:00
fabs.bf16.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
fabs.f16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fabs.f64.ll
[SDAG] Remove non-canonical fabs libcall handling (#177967)
2026-01-26 15:11:17 +00:00
fabs.ll
[SDAG] Remove non-canonical fabs libcall handling (#177967)
2026-01-26 15:11:17 +00:00
fadd64.ll
…
fadd-fma-fmul-combine.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fadd.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
fadd.ll
…
fast-ra-kills-vcc.mir
…
fast-regalloc-bundles.mir
…
fast-unaligned-load-store.global.ll
…
fast-unaligned-load-store.private.ll
…
fastregalloc-illegal-subreg-physreg.mir
…
fastregalloc-self-loop-heuristic.mir
…
fastregalloc-sgpr-only.mir
…
fcanonicalize-elimination.bf16.ll
…
fcanonicalize-elimination.ll
Revert "Avoid maxnum(sNaN, x) optimizations / folds (#170181)" (#184125)
2026-03-03 12:45:26 +00:00
fcanonicalize.bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
fcanonicalize.f16.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fcanonicalize.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fceil64.ll
…
fceil.ll
…
fcmp64.ll
…
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
fcmp.ll
…
fconst64.ll
…
fcopysign.bf16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fcopysign.f16.ll
[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)
2026-01-30 15:13:33 +00:00
fcopysign.f32.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fcopysign.f32.r600.ll
…
fcopysign.f64.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fcopysign.gfx11plus.ll
[AMDGPU][True16][CodeGen] Fixed two lit tests (#157684)
2025-09-09 11:13:23 -04:00
fdiv32-to-rcp-folding.ll
…
fdiv_flags.f32.ll
[AMDGPU] Use reverse iteration in CodeGenPrepare (#145484)
2025-10-10 13:00:40 +02:00
fdiv-nofpexcept.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fdiv.bf16.ll
[AMDGPU] Add support for safe bfloat16 fdiv on targets with bf16 trans instructions (#154373)
2025-08-19 16:03:45 -04:00
fdiv.f16.ll
[AMDGPU] Fix pattern selecting fmul to v_fma_mix_f32 (#180210)
2026-02-07 09:31:07 +00:00
fdiv.f64.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
fdiv.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fdot2.ll
…
fence-barrier.ll
…
fence-lds-read2-write2.ll
…
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
ffloor.f64.ll
…
ffloor.ll
…
finalize-isel-kill-scc-vcc.mir
…
finalizebundle.mir
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
fix-crash-valu-hazard.ll
[AMDGPU] Global and Buffer loads to LDS should not increase lgkmcnt (#179305)
2026-02-05 09:36:00 -08:00
fix-frame-ptr-reg-copy-livein.ll
…
fix-frame-reg-in-custom-csr-spills.ll
…
fix-sgpr-copies-f16-fake16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-f16-gfx12-fake16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-f16-gfx12-true16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-f16-true16.mir
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
fix-sgpr-copies-f16.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-sgpr-copies-nondeterminism.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
fix-sgpr-copies-phi-block-end-iterator-debugloc.ll
…
fix-sgpr-copies-phi-regression-av-classes.ll
[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)
2025-11-21 15:17:55 +00:00
fix-sgpr-copies-phi-regression-issue130646-issue130119.ll
…
fix-sgpr-copies-phi-regression-issue130646.mir
…
fix-sgpr-copies-readfirstlane-av-register-regression.ll
AMDGPU: Constrain readfirstlane operand when writing to m0 (#168004)
2025-11-14 17:18:43 +00:00
fix-sgpr-copies-sgpr32-to-vgpr16.ll
[AMDGPU][True16] change vdst_in regclass and remove opsel for cvt_pk_f8_fp32 pattern (#179995)
2026-02-26 10:19:18 -05:00
fix-sgpr-copies-vgpr16-to-spgr32.ll
…
fix-sgpr-copies-wmma-scale-lo256.mir
[AMDGPU] Constrain register class during COPY elimination based on their uses (#181909)
2026-02-17 13:47:54 -08:00
fix-sgpr-copies-wwm.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
fix-sgpr-copies-wwm.mir
…
fix-sgpr-copies.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
fix-vgpr-copies.mir
…
fix-wwm-vgpr-copy.ll
…
flat_atomics_i32_system.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
flat_atomics_i64_noprivate.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
flat_atomics_i64_system_noprivate.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
flat_atomics_i64_system.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
flat_atomics_i64.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
flat_atomics.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
flat-address-space.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
flat-atomic-fadd.f32.ll
…
flat-atomic-fadd.f64.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
flat-atomicrmw-fadd.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
flat-atomicrmw-fmax.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
flat-atomicrmw-fmin.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
flat-atomicrmw-fsub.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
flat-error-unsupported-gpu-hsa.ll
[AMDGPU] Fix duplicate RUN lines in tests (#182286)
2026-02-19 16:07:20 +00:00
flat-for-global-subtarget-feature.ll
…
flat-load-clustering.mir
…
flat-load-saddr-to-vaddr.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
flat-offset-bug.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
flat-saddr-atomics.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
flat-saddr-load.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
flat-saddr-store.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
flat-scratch-alloca-issue-155902.ll
[CodeGen] Consider imm offsets when sorting framerefs (#171012)
2026-01-08 17:48:30 -05:00
flat-scratch-fold-fi-gfx1250.mir
…
flat-scratch-fold-fi.mir
…
flat-scratch-i8-i16.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
flat-scratch-init.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
flat-scratch-reg.ll
…
flat-scratch-svs.ll
[AMDGPU] [GlobalIsel] Enabling lit tests for new regbank select (#180680)
2026-02-11 07:52:47 +05:30
flat-scratch.ll
Reapply "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325) (#184114)
2026-03-02 14:47:35 +00:00
floor.ll
[SDAG] Remove most non-canonical libcall handing (#171288)
2025-12-10 11:45:26 +01:00
fma-combine.ll
[SelectionDAG] Remove NoInfsFPMath uses (#162788)
2025-10-12 09:34:24 +08:00
fma-mix.gfx11plus.ll
[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)
2025-09-24 11:27:26 -04:00
fma.f16.gfx11plus.ll
[AMDGPU][True16][CodeGen] insert proper register for 16bit data type in vop3p insts (#153143)
2025-08-14 12:02:15 -04:00
fma.f16.ll
[AMDGPU] Extend RA hints to handle VGPR_16_Lo128 (#176819)
2026-01-19 13:41:14 -08:00
fma.f64.ll
…
fma.ll
…
fmac.sdwa.ll
…
fmad-formation-fmul-distribute-denormal-mode.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
fmad.ll
…
fmamk_fmaak-t16.mir
[AMDGPU] Make VGPR_16_Lo128 allocatable (#173309)
2026-01-14 10:40:05 -08:00
fmax3-maximumnum.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fmax3.f64.ll
…
fmax3.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
fmax_legacy.f16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fmax_legacy.f64.ll
…
fmax_legacy.ll
[SelectionDAGBuilder] Remove NoNaNsFPMath uses (#169904)
2026-02-09 09:48:07 +08:00
fmax.ll
…
fmaximum3.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
fmaximum3.v2f16.ll
AMDGPU: Support V_PK_MAXIMUM3_F16 and V_PK_MINIMUM3_F16 on gfx1250 (#150307)
2025-07-23 13:45:01 -07:00
fmaximum.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
fmaxnum.f64.ll
…
fmaxnum.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)
2026-02-20 09:44:58 -08:00
fmaxnum.r600.ll
…
fmed3-cast-combine.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)
2026-02-20 09:44:58 -08:00
fmed3.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fmed3.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)
2026-02-20 09:44:58 -08:00
fmin3-minimumnum.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fmin3.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
fmin_fmax_legacy.amdgcn.ll
[DAGCombiner] Remove most NoSignedZerosFPMath uses (#161180)
2025-09-30 11:44:34 +08:00
fmin_legacy.f16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fmin_legacy.f64.ll
…
fmin_legacy.ll
[SelectionDAGBuilder] Remove NoNaNsFPMath uses (#169904)
2026-02-09 09:48:07 +08:00
fmin.ll
…
fminimum3.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
fminimum3.v2f16.ll
AMDGPU: Support V_PK_MAXIMUM3_F16 and V_PK_MINIMUM3_F16 on gfx1250 (#150307)
2025-07-23 13:45:01 -07:00
fminimum.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
fminnum.f64.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fminnum.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)
2026-02-20 09:44:58 -08:00
fminnum.r600.ll
…
fmul64.ll
…
fmul-2-combine-multi-use.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
fmul-to-ldexp.ll
[AMDGPU] Extend RA hints to handle VGPR_16_Lo128 (#176819)
2026-01-19 13:41:14 -08:00
fmul.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
fmul.ll
…
fmuladd.f16.ll
…
fmuladd.f32.ll
[AMDGPU] fmuladd.f32.ll - clean up prefixes and regenerate checks (#151832)
2025-08-03 09:13:34 +01:00
fmuladd.f64.ll
…
fmuladd.v2f16.ll
[AMDGPU] Fix duplicate RUN lines in tests (#182286)
2026-02-19 16:07:20 +00:00
fncall-implicitdef.ll
[LiveVariables] Mark use without implicit if defined at instr (#119446)
2025-08-18 08:34:59 -04:00
fnearbyint.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
fneg-combines-gfx1200.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)
2026-02-20 09:44:58 -08:00
fneg-combines.f16.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fneg-combines.legal.f16.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fneg-combines.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fneg-combines.new.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fneg-combines.si.ll
…
fneg-fabs-divergence-driven-isel.ll
…
fneg-fabs-r600.ll
[SDAG] Remove non-canonical fabs libcall handling (#177967)
2026-01-26 15:11:17 +00:00
fneg-fabs.bf16.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
fneg-fabs.f16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fneg-fabs.f64.ll
[SDAG] Remove non-canonical fabs libcall handling (#177967)
2026-01-26 15:11:17 +00:00
fneg-fabs.ll
[SDAG] Remove non-canonical fabs libcall handling (#177967)
2026-01-26 15:11:17 +00:00
fneg-fold-legalize-dag-increase-insts.ll
…
fneg-modifier-casting.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fneg.bf16.ll
[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (#165295)
2025-11-11 13:14:48 -06:00
fneg.f16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fneg.f64.ll
…
fneg.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
fold_acc_copy_into_valu.mir
…
fold-agpr-phis.mir
…
fold-cndmask-wave32.mir
…
fold-cndmask.mir
…
fold-commute-sgpr.mir
…
fold-fabs.ll
[SelectionDAGBuilder] Remove NoNaNsFPMath uses (#169904)
2026-02-09 09:48:07 +08:00
fold-fi-mubuf.mir
…
fold-fi-operand-shrink.mir
…
fold-fmaak-bug.ll
…
fold-fmul-to-neg-abs.ll
…
fold-freeze-fmul-to-fma.ll
…
fold-gep-offset.ll
[AMDGPU] Disable negative imm offset for async load/store instructions (#185078)
2026-03-06 21:55:39 +00:00
fold-imm-copy-agpr.mir
AMDGPU: Check if immediate is legal for av_mov_b32_imm_pseudo (#160819)
2025-09-27 08:24:20 +09:00
fold-imm-copy.mir
AMDGPU: Check if immediate is legal for av_mov_b32_imm_pseudo (#160819)
2025-09-27 08:24:20 +09:00
fold-imm-f16-f32.mir
…
fold-immediate-operand-shrink-with-carry.mir
…
fold-immediate-operand-shrink.mir
…
fold-immediate-output-mods.mir
…
fold-implicit-operand.mir
…
fold-int-pow2-with-fmul-or-fdiv.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
fold-literal-multiple-gfx10.mir
…
fold-multiple-commute.mir
…
fold-multiple.mir
…
fold-omod-crash.mir
…
fold-operands-frame-index-agpr.mir
AMDGPU: Check if immediate is legal for av_mov_b32_imm_pseudo (#160819)
2025-09-27 08:24:20 +09:00
fold-operands-frame-index.gfx10.mir
…
fold-operands-frame-index.mir
[AMDGPU] Do not fold an immediate into instructions with frame indexes (#151263)
2025-08-06 11:47:37 -07:00
fold-operands-order.mir
…
fold-operands-remove-m0-redef.mir
…
fold-operands-s-add-copy-to-vgpr.mir
…
fold-operands-scalar-fmac.mir
…
fold-over-exec.mir
…
fold-readlane.mir
…
fold-reload-into-exec.mir
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
fold-reload-into-m0.mir
…
fold-restore-undef-use.mir
…
fold-sgpr-copy.mir
AMDGPU: Relax legal register operand constraint (#157989)
2025-09-12 08:57:47 +09:00
fold-sgpr-multi-imm.mir
[AMDGPU] Do not fold an immediate into instructions with frame indexes (#151263)
2025-08-06 11:47:37 -07:00
fold-short-64-bit-literals.mir
…
fold-vgpr-copy.mir
…
fold-vgpr-phyreg.mir
…
fold-zero-high-bits-clear-kill-flags.mir
…
fold-zero-high-bits-skips-non-reg.mir
…
folding-of-i32-as-i64.mir
…
force-alwaysinline-lds-global-address-codegen.ll
…
force-alwaysinline-lds-global-address.ll
[AMDGPU] Fix duplicate RUN lines in tests (#182286)
2026-02-19 16:07:20 +00:00
force-wait-after-always-gds.mir
…
fp32_to_fp16.ll
…
fp64-atomics-gfx90a.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
fp64-min-max-buffer-atomics.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for atomic fmin/fmax (#182824)
2026-03-17 14:06:29 +00:00
fp64-min-max-buffer-ptr-atomics.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for atomic fmin/fmax (#182824)
2026-03-17 14:06:29 +00:00
fp_to_sint.f64.ll
…
fp_to_sint.ll
[AMDGPU] Implement codegen for GFX11+ V_CVT_PK_[IU]16_F32 (#168719)
2025-12-10 22:26:59 +00:00
fp_to_uint.f64.ll
…
fp_to_uint.ll
[AMDGPU] Implement codegen for GFX11+ V_CVT_PK_[IU]16_F32 (#168719)
2025-12-10 22:26:59 +00:00
fp_trunc_store_fp32_to_bf16.ll
AMDGPU: Fix truncstore from v6f32 to v6f16 (#171212)
2025-12-08 22:46:36 +00:00
fp_trunc_store_fp64_to_bf16.ll
…
fp-atomic-to-s_denormmode.mir
…
fp-atomics-gfx942.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
fp-atomics-gfx950.ll
…
fp-atomics-gfx1200.ll
…
fp-classify.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fp-min-max-buffer-atomics.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for atomic fmin/fmax (#182824)
2026-03-17 14:06:29 +00:00
fp-min-max-buffer-ptr-atomics.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for atomic fmin/fmax (#182824)
2026-03-17 14:06:29 +00:00
fp-min-max-image-atomics.ll
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
fp-min-max-num-flat-atomics.ll
[AMDGPU][GlobalIsel] Add register bank legalization rules for amdgcn atomic fminmax num (#184564)
2026-03-10 14:53:32 -05:00
fp-min-max-num-global-atomics.ll
[AMDGPU][GlobalIsel] Add register bank legalization rules for amdgcn atomic fminmax num (#184564)
2026-03-10 14:53:32 -05:00
fp-to-int-to-fp.ll
[DAGCombiner] Extend fp->int->fp optimizations to include clamping (#164502)
2025-12-23 20:26:40 +02:00
fpenv.ll
…
fpext-free.ll
[AMDGPU] Fix and simplify patterns selecting fsub to v_fma_mix_f32 (#180169)
2026-02-06 14:39:13 +00:00
fpext.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
fpext.ll
…
fpow.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
fptoi.i128.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_PHI (#179735)
2026-03-06 14:01:50 +01:00
fptosi-sat-scalar.ll
[AMDGPU] Use s_cvt_i32/u32_f32 instructions for saturated uniform conversions (#187711)
2026-03-23 10:56:44 +00:00
fptosi-sat-vector.ll
[AMDGPU] Use s_cvt_i32/u32_f32 instructions for saturated uniform conversions (#187711)
2026-03-23 10:56:44 +00:00
fptosi.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
fptoui_uitofp.ll
[DAGCombiner] Extend FP-to-Int cast without requiring nsz (#161093)
2025-10-11 00:34:33 +09:00
fptoui-sat-scalar.ll
[AMDGPU] Use s_cvt_i32/u32_f32 instructions for saturated uniform conversions (#187711)
2026-03-23 10:56:44 +00:00
fptoui-sat-vector.ll
[AMDGPU] Use s_cvt_i32/u32_f32 instructions for saturated uniform conversions (#187711)
2026-03-23 10:56:44 +00:00
fptoui.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
fptrunc.f16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
fptrunc.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
fptrunc.v2f16.no.fast.math.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPTRUNC (#171723)
2025-12-18 13:16:46 -08:00
fract-match.ll
AMDGPU: Use SimplifyQuery in AMDGPUCodeGenPrepare (#179133)
2026-02-02 09:33:16 +01:00
fract.f64.ll
[AMDGPU] Fix duplicate RUN lines in tests (#182286)
2026-02-19 16:07:20 +00:00
fract.ll
[AMDGPU] Fix duplicate RUN lines in tests (#182286)
2026-02-19 16:07:20 +00:00
frame-index-elimination-tied-operand.mir
…
frame-index-elimination.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
frame-index.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
frame-lowering-entry-all-sgpr-used.mir
…
frame-lowering-fp-adjusted.mir
…
frame-setup-without-sgpr-to-vgpr-spills.ll
…
freeze-binary.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
freeze.ll
[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
2026-02-25 15:24:54 -08:00
frem.ll
[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180940)
2026-02-11 19:14:54 +00:00
frexp-constant-fold.ll
…
fshl.ll
[AMDGPU] Invert scc uses to delete s_cmp_eq* (#167382)
2026-01-14 10:24:24 -06:00
fshr.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
fsqrt.f32.ll
AMDGPU: Teach lowering that sqrt never returns subnormal (#174838)
2026-01-08 12:05:29 +01:00
fsqrt.f64.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
fsqrt.r600.ll
[AMDGPU][test] Remove unsafe-fp-math uses (NFC) (#164609)
2025-10-23 01:45:54 +00:00
fsub64.ll
…
fsub-as-fneg-src-modifier.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fsub.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
fsub.ll
[DAGCombiner] Remove NoSignedZerosFPMath in visitFNEG (#162052)
2025-10-08 17:01:47 +08:00
ftrunc.f64.ll
…
ftrunc.ll
…
function-alignment.ll
[AMDGPU] Set preferred function alignment based on icache geometry (#183064)
2026-03-11 07:57:37 -04:00
function-args-inreg.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
function-args.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
function-call-relocs.ll
…
function-esm2-prologue-epilogue.ll
[AMDGPU] Add support for GFX12 expert scheduling mode 2 (#170319)
2026-01-09 15:49:10 +00:00
function-resource-usage.ll
[AMDGPU] Emit amdgpu.max_num_named_barrier resource symbol (#169851)
2025-12-04 12:48:23 -08:00
function-returns.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
fused-bitlogic.ll
…
gcn-reg-pressure-true16-integer-overflow.mir
…
gds-allocation.ll
…
gds-atomic.ll
…
gds-unsupported.ll
…
generic-targets-require-v6.ll
[AMDGPU] Add gfx12-5-generic subtarget (#183381)
2026-02-25 13:34:48 -08:00
gep-address-space.ll
…
gep-const-address-space.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
gep-flags-stack-offsets.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
gfx10-twoaddr-fma.mir
…
gfx10-vop-literal.ll
…
gfx10plus-wavefront-sgpr-count.ll
[AMDGPU] Set GRANULATED_WAVEFRONT_SGPR_COUNT of compute_pgm_rsrc1 to 0 for gfx10+ (#154666)
2025-08-27 09:48:42 +08:00
gfx11-sgpr-hazard-latency.mir
[AMDGPU] Add machineFunctionInfo to recent MIR tests (#179602)
2026-02-04 22:12:01 +09:00
gfx11-twoaddr-fma.mir
…
gfx11-user-sgpr-init16-bug.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
gfx12_scalar_subword_loads.ll
…
gfx90a-enc.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
gfx902-without-xnack.ll
…
gfx942-hazards.mir
…
gfx-call-non-gfx-func.ll
…
gfx-callable-argument-types.ll
AMDGPU: Perform zero/any extend combine into permute (#177370)
2026-01-28 10:47:22 -06:00
gfx-callable-preserved-registers.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
gfx-callable-return-types.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
global_atomic_optimizer_fp_rtn.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
global_atomics_i32_system.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
global_atomics_i64_system.ll
PeepholeOpt: Fix losing subregister indexes on full copies (#161310)
2025-10-02 13:36:47 +09:00
global_atomics_i64.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
global_atomics_iterative_scan_fp.ll
…
global_atomics_iterative_scan.ll
…
global_atomics_optimizer_fp_no_rtn.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
global_atomics_scan_fadd.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
global_atomics_scan_fmax.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
global_atomics_scan_fmin.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
global_atomics_scan_fsub.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
global_atomics.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
global_smrd_cfg.ll
…
global_smrd.ll
…
global-address.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
global-alias.ll
…
global-atomic-fadd.f32-no-rtn.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
global-atomic-fadd.f32-rtn.ll
AMDGPU: Start to use AV classes for unknown vector class (#166482)
2025-11-13 09:28:33 -08:00
global-atomic-fadd.f64.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
global-atomic-fadd.v2f16-no-rtn.ll
…
global-atomic-fadd.v2f16-rtn.ll
…
global-atomic-scan.ll
…
global-atomicrmw-fadd-wrong-subtarget.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
global-atomicrmw-fadd.ll
[AMDGPU] Fix encoding of inline constants in v_fma_mix_f32_bf16 (#183487)
2026-02-26 19:30:20 +00:00
global-atomicrmw-fmax.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
global-atomicrmw-fmin.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
global-atomicrmw-fsub.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
global-atomics-fp-wrong-subtarget.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
global-constant.ll
AMDGPU: Use ELF mangling in data layout (#163011)
2025-10-13 03:01:45 +00:00
global-directive.ll
…
global-extload-gfx11plus.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
global-extload-i16.ll
…
global-i16-load-store.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
global-load-saddr-to-vaddr.ll
…
global-load-xcnt.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
global-saddr-atomics-min-max-system.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
global-saddr-atomics.gfx908.ll
…
global-saddr-atomics.gfx1030.ll
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
2025-12-05 12:37:33 +00:00
global-saddr-atomics.ll
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
global-saddr-load.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
global-saddr-store.ll
…
global-smrd-unknown.ll
…
global-variable-relocs.ll
AMDGPU: Use ELF mangling in data layout (#163011)
2025-10-13 03:01:45 +00:00
greedy-alloc-fail-sgpr1024-spill.mir
…
greedy-broken-ssa-verifier-error.mir
…
greedy-global-heuristic.mir
…
greedy-instruction-split-subrange.mir
…
greedy-liverange-priority.mir
…
greedy-remark-crash-unassigned-reg.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
greedy-reverse-local-assignment.ll
…
group-image-instructions.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
gv-const-addrspace.ll
…
gv-offset-folding.ll
…
gws_agpr.ll
AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)
2025-11-25 18:55:34 +00:00
gws-hazards.mir
…
half-alloca-promotion.ll
…
half.ll
[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
2026-02-25 15:24:54 -08:00
hard-clause-limit-attr.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clause-limit.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clauses-gfx1250.mir
[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)
2025-08-13 10:41:44 +08:00
hard-clauses-img-gfx10.mir
…
hard-clauses-img-gfx11.mir
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
hard-clauses-img-gfx12.mir
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
hard-clauses-load-monitor.mir
[AMDGPU] Update hard-clauses-load-monitor.mir. NFC (#157546)
2025-09-08 16:19:10 -07:00
hard-clauses.mir
[MachineStripDebug] Remove debug instructions from inside bundles (#160297)
2025-09-25 09:40:54 +01:00
hazard-buffer-store-v-interp.mir
…
hazard-flat-instruction-valu-check.mir
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
hazard-getreg-waitalu.mir
[AMDGPU] Test hazard-getreg-waitalu.mir on gfx13 (#183007)
2026-03-05 14:03:26 +01:00
hazard-gfx1250-flat-scr-hi.mir
[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC (#170396)
2025-12-03 00:14:32 -08:00
hazard-hidden-bundle.mir
…
hazard-in-bundle.mir
…
hazard-inlineasm.mir
…
hazard-kill.mir
…
hazard-lds-addtid.mir
…
hazard-pass-ordering.mir
…
hazard-pseudo-machineinstrs.mir
…
hazard-recognizer-meta-insts.mir
…
hazard-recognizer-src-shared-base.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
hazard-setreg-vgpr-msb-gfx1250.mir
[AMDGPU] Fix GFX1250 hazard: S_SET_VGPR_MSB dropped (#184904)
2026-03-10 09:35:45 -04:00
hazard-shift64.mir
[AMDGPU] Enable shift64 hazard recognition for gfx9 (#183839)
2026-02-28 08:59:55 -06:00
hazard.mir
…
hazards-gfx950.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
hazards-gfx1250.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
high-bits-zeroed-16-bit-ops.mir
…
high-RP-reschedule.mir
…
hip.extern.shared.array.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
hoist-cond.ll
…
hsa-default-device.ll
…
hsa-fp-mode.ll
[AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (#182107)
2026-03-04 12:16:41 +01:00
hsa-func-align.ll
[AMDGPU] Set preferred function alignment based on icache geometry (#183064)
2026-03-11 07:57:37 -04:00
hsa-func.ll
[AMDGPU] Set preferred function alignment based on icache geometry (#183064)
2026-03-11 07:57:37 -04:00
hsa-generic-target-features.ll
[AMDGPU] Add gfx12-5-generic subtarget (#183381)
2026-02-25 13:34:48 -08:00
hsa-globals.ll
…
hsa-group-segment.ll
…
hsa-metadata-agpr-register-count.ll
…
hsa-metadata-agpr-small.ll
…
hsa-metadata-deduced-arg-attr.ll
…
hsa-metadata-dynlds-func-hidden-args-v5.ll
…
hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
…
hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
…
hsa-metadata-enqueue-kernel-.ll
…
hsa-metadata-from-llvm-ctor-dtor-list.ll
…
hsa-metadata-from-llvm-ir-full.ll
…
hsa-metadata-heap-v5.ll
…
hsa-metadata-hidden-args-v4.ll
…
hsa-metadata-hidden-args-v5.ll
…
hsa-metadata-hostcall-present-asan.ll
…
hsa-metadata-hostcall-v4.ll
…
hsa-metadata-hostcall-v5.ll
…
hsa-metadata-images.ll
…
hsa-metadata-invalid-ocl-version-1.ll
…
hsa-metadata-invalid-ocl-version-3.ll
…
hsa-metadata-kernel-code-props.ll
…
hsa-metadata-multigrid-sync-arg-v5.ll
…
hsa-metadata-queue-ptr-v4.ll
…
hsa-metadata-queue-ptr-v5.ll
…
hsa-metadata-queueptr-v5.ll
…
hsa-metadata-resource-usage-function-ordering.ll
…
hsa-metadata-uniform-workgroup-size-v5.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
hsa-metadata-wavefrontsize.ll
…
hsa-metadata-workgroup-processor-mode-v5.ll
…
hsa-note-no-func.ll
…
hsa.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
huge-number-operand-folds.mir
…
huge-private-buffer.ll
…
i1_copy_phi_with_phi_incoming_value.mir
…
i1-copies-rpo.mir
…
i1-copy-from-loop.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
i1-copy-implicit-def.ll
…
i1-copy-phi-uniform-branch.ll
…
i1-copy-phi.ll
…
i1-divergent-phi-fix-sgpr-copies-assert.mir
…
i1-to-bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
i8-to-double-to-float.ll
…
icmp64.ll
…
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
…
idemponent-atomics.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
identical-subrange-spill-infloop.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
idiv-licm.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
idot2.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
idot4s.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
idot4u.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
idot8s.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
idot8u.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
iglp-no-clobber.ll
[CodeGen] Treat hasOrderedMemoryRef as implying arbitrary loads or stores (#182000)
2026-03-04 17:49:11 +00:00
iglp.opt.reentry.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
illegal-eviction-assert.mir
…
illegal-sgpr-to-vgpr-copy.ll
[NFC][FIX] Add -verify-machineinstrs=0 explicitly to some test files
2025-07-23 19:12:46 -04:00
image-attributes.ll
…
image-load-d16-tfe.ll
…
image-resource-id.ll
…
image-sample-waterfall.ll
…
image-schedule.ll
…
img-nouse-adjust.ll
…
imm16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
imm.ll
Reapply "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325) (#184114)
2026-03-02 14:47:35 +00:00
immv216.ll
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
implicit-arg-block-count.ll
AMDGPU: Add dereferenceable attribute to dispatch ptr intrinsic (#185955)
2026-03-12 07:28:39 +01:00
implicit-arg-v5-opt.ll
AMDGPU: Annotate grid_dims ABI load with range metadata (#185610)
2026-03-16 23:31:32 +01:00
implicit-def-muse.ll
…
implicit-kernarg-backend-usage.ll
[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)
2025-09-16 02:26:32 -07:00
implicit-kernel-argument-alignment.ll
…
implicitarg-attributes.ll
…
implicitarg-offset-attributes.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
indirect-addressing-si-gfx9.ll
…
indirect-addressing-si.ll
AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 (#168166)
2025-11-14 20:19:24 -08:00
indirect-addressing-term.ll
…
indirect-call-known-callees.ll
…
indirect-call-set-from-other-function.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
indirect-call.ll
…
indirect-private-64.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
indirect-reg-read-imm-idx.ll
[AMDGPU] Fix V_INDIRECT_REG_READ_GPR_IDX expansion with immediate index (#179699)
2026-02-09 11:33:30 +01:00
indirect-reg-read-imm-idx.mir
[AMDGPU] Fix V_INDIRECT_REG_READ_GPR_IDX expansion with immediate index (#179699)
2026-02-09 11:33:30 +01:00
infer-addrpace-pipeline.ll
…
infer-addrspace-flat-atomic.ll
[AMDGPU][SDAG] Only fold flat offsets if they are inbounds PTRADDs (#165427)
2025-11-19 11:48:12 +01:00
infer-uniform-load-shader.ll
…
infinite-loop-evergreen.ll
…
infinite-loop.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
inflate-av-remat-imm.mir
AMDGPU: Add pseudoinstruction for 64-bit agpr or vgpr constants (#154499)
2025-08-20 22:54:37 +09:00
inflate-reg-class-vgpr-mfma-to-agpr-negative-tests.mir
AMDGPU: Handle rewriting VGPR MFMA to AGPR with subregister copies (#153019)
2025-08-21 01:17:03 +00:00
inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
inflate-reg-class-vgpr-mfma-to-av.mir
…
inflated-reg-class-snippet-copy-use-after-free.mir
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
infloop-subrange-spill-inspect-subrange.mir
…
infloop-subrange-spill.mir
…
init-whole-wave-vgpr-count-large.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
init-whole-wave-vgpr-count-leaf.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
init-whole-wave-vgpr-count-use-inactive.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
init-whole-wave-vgpr-count.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
inline-asm-av-constraint-err.ll
AMDGPU: Add new VA inline asm constraint for AV registers (#152665)
2025-08-12 10:17:28 +09:00
inline-asm-av-constraint.ll
AMDGPU: Add new VA inline asm constraint for AV registers (#152665)
2025-08-12 10:17:28 +09:00
inline-asm-out-of-bounds-register.ll
[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)
2025-09-03 16:25:18 -07:00
inline-asm-reserved-regs.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
inline-asm.i128.ll
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
inline-asm.ll
…
inline-attr.ll
[LLVM] Remove "no-nans-fp-math" attribute support (#186285)
2026-03-13 09:29:28 +00:00
inline-calls.ll
…
inline-constraints.ll
…
inline-maxbb.ll
…
inlineasm-16-fake16.ll
…
inlineasm-16-true16.ll
…
inlineasm-16.ll
…
inlineasm-illegal-type.ll
[AMDGPU] Fix crash for inline-asm inputs of type MVT::Other (#153425)
2025-08-13 17:27:31 +02:00
inlineasm-mismatched-size-error.ll
[AMDGPU] Fix a crash when a bool variable is used in inline asm (#171004)
2025-12-08 14:44:21 -05:00
inlineasm-mismatched-size.ll
…
inlineasm-packed.ll
…
inlineasm-sgmask.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
inlineasm-v16.ll
…
InlineAsmCrash.ll
…
input-mods.r600.ll
…
insert_subreg.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
insert_vector_dynelt.ll
Reapply "[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#170323) (#171838)
2025-12-15 09:05:00 +01:00
insert_vector_elt.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
insert_vector_elt.v2bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
insert_vector_elt.v2i16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
…
insert_vector_elt.v2i16.subtest-saddr.ll
…
insert_waitcnt_for_precise_memory.ll
ValueTracking/AMDGPU: handle mbcnt in computeKnownBitsFromOperator (#183229)
2026-03-02 10:48:15 +08:00
insert-branch-w32.mir
…
insert-delay-alu-bug.ll
[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)
2025-10-22 08:42:29 -05:00
insert-delay-alu-literal.mir
…
insert-delay-alu-parse.mir
…
insert-delay-alu-wmma-xdl.mir
…
insert-delay-alu.mir
[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180940)
2026-02-11 19:14:54 +00:00
insert-handle-flat-vmem-ds.mir
…
insert-skip-from-vcc.mir
AMDGPU: Fix assert when looking for s_and_b64 + vcc branch pattern (#177031)
2026-01-20 22:23:52 +00:00
insert-skips-gfx10.mir
…
insert-skips-gfx12.mir
[AMDGPU] Add s_barrier_init|join|leave instructions (#153296)
2025-08-12 15:07:07 -07:00
insert-skips-gfx1250.mir
[AMDGPU] Handle S_WAIT_XCNT in SIInstrInfo::isWaitcnt (#187726)
2026-03-23 10:19:43 +00:00
insert-skips-gws.mir
…
insert-skips-ignored-insts.mir
…
insert-subvector-unused-scratch.ll
…
insert-waitcnts-callee.mir
…
insert-waitcnts-crash.ll
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
insert-waitcnts-exp.mir
…
insert-waitcnts-fence-soft.mir
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
insert-waitcnts-gfx12-wbinv.mir
…
insert-waitcnts-hang.mir
…
insert-waitcnts-merge.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
inserted-wait-states.mir
…
inst-prefetch-hint.ll
…
integer-canonicalizing-src-modifiers.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
integer-mad-patterns.ll
[AMDGPU] Update gfx1250 sched model to latest table (#182923)
2026-02-23 13:25:07 -08:00
integer-select-src-modifiers.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
internalize.ll
…
intrinsic-amdgcn-s-alloc-vgpr.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
invalid-addrspacecast.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
invalid-cast-load-i1.ll
…
invalid-hidden-kernarg-in-kernel-signature.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
invalid-inline-asm-constraint-crash.ll
…
invariant-image-load.ll
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
invariant-load-no-alias-store.ll
AMDGPU: Handle invariant loads when considering if a load can be scalar (#168787)
2025-11-20 13:07:23 -05:00
invert-br-undef-vcc.mir
…
ipra-regmask.ll
[CodeGen][NPM] Add support for -print-regusage in New Pass Manager (#169761)
2026-01-14 11:00:02 +05:30
ipra-return-address-save-restore.ll
…
ipra.ll
…
irtranslator-whole-wave-functions.ll
Reapply "[AMDGPU] Intrinsic for launching whole wave functions" (#153584)
2025-08-15 10:12:47 +02:00
isel-amdgcn-cs-chain-intrinsic-w32.ll
[AMDGPU] Relax restrictions on amdgcn.cs.chain intrinsic (#169785)
2025-12-10 11:12:46 +01:00
isel-amdgcn-cs-chain-intrinsic-w64.ll
[AMDGPU] Allow any SGPRs for chain callees (#168345)
2025-12-02 09:44:35 +01:00
isel-amdgpu-cs-chain-cc.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
[AMDGPU] Allow any SGPRs for chain callees (#168345)
2025-12-02 09:44:35 +01:00
isel-amdgpu-cs-chain-preserve-cc.ll
AMDGPU/GlobalISel: Regbanklegalize for G_CONCAT_VECTORS (#171471)
2025-12-15 10:37:40 +01:00
isel-whole-wave-functions.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
issue48473.mir
…
issue92561-restore-undef-scc-verifier-error.ll
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
issue98474-assigned-physreg-interference.mir
…
issue98474-need-live-out-undef-subregister-def.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
issue98474-virtregrewriter-live-out-undef-subregisters.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
issue120256-annotate-constexpr-addrspacecast.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
issue121601-combine-concat-vectors-assumes-f16.ll
…
issue130120-eliminate-frame-index.ll
[AMDGPU] Do not fold an immediate into instructions with frame indexes (#151263)
2025-08-06 11:47:37 -07:00
issue139317-bad-opsel-reg-sequence-fold.ll
…
issue153808-extract-subvector-legalize.ll
DAG: Handle half spanning extract_subvector in type legalization (#154101)
2025-08-21 00:05:12 +00:00
issue176578.ll
AMDGPU: Fix assert when looking for s_and_b64 + vcc branch pattern (#177031)
2026-01-20 22:23:52 +00:00
issue176966-extend-vector-inreg.ll
Fix EXTEND_VECTOR_INREG widening when input > result size (#177095)
2026-01-22 09:33:46 +01:00
itofp.i128.bf.ll
[AMDGPU][ISel] setcc peephole for comparisons with upper 32 bits of a 64-bit register pair (#177662)
2026-02-11 13:41:03 -07:00
itofp.i128.ll
[AMDGPU][ISel] setcc peephole for comparisons with upper 32 bits of a 64-bit register pair (#177662)
2026-02-11 13:41:03 -07:00
jump-address.ll
…
kcache-fold.ll
…
kernarg-size.ll
[AMDGPU] Fix duplicate RUN lines in tests (#182286)
2026-02-19 16:07:20 +00:00
kernarg-stack-alignment.ll
…
kernel_code_t_recurse.ll
…
kernel-args.ll
R600: Really remove softPromoteHalfType (#178040)
2026-01-26 20:46:37 +00:00
kernel-argument-dag-lowering.ll
AMDGPU: Perform zero/any extend combine into permute (#177370)
2026-01-28 10:47:22 -06:00
kernel-mubuf-with-voffset.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
kernel-vgpr-spill-mubuf-with-voffset.ll
…
kill-infinite-loop.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
kill-true-in-return-block.ll
…
known-never-nan.ll
…
known-never-snan.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
knownbits-recursion.ll
…
large-alloca-compute.ll
…
large-alloca-graphics.ll
…
large-avgpr-assign-last.mir
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
large-constant-initializer.ll
…
large-work-group-promote-alloca.ll
…
lcssa-optnone.ll
…
lds-alignment.ll
…
lds-bounds.ll
…
lds-branch-vmem-hazard.mir
[AMDGPU] Consider FLAT instructions for VMEM hazard detection (#137170)
2025-11-18 18:41:04 +01:00
lds-direct-hazards-gfx11.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
lds-direct-hazards-gfx12.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
lds-dma-hazards.mir
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
lds-dma-waitcnt.mir
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
lds-dma-waits.ll
(reland) [AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077) (#171779)
2025-12-12 09:41:04 +01:00
lds-dma-workgroup-release.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
lds-frame-extern.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
lds-global-non-entry-func.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for amd_gcn_end_cf (#175118)
2026-01-13 18:18:39 +05:30
lds-initializer.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
lds-limit-diagnostics-gfx1250.ll
[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)
2025-08-14 12:52:00 -07:00
lds-limit-diagnostics.ll
…
lds-m0-init-in-loop.ll
…
lds-misaligned-bug.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
lds-mixed-absolute-addresses-unused.ll
…
lds-mixed-absolute-dynlds.ll
…
lds-no-realign-allocated-variables.ll
…
lds-oqap-crash.ll
…
lds-output-queue.ll
…
lds-reject-anonymous-kernels.ll
…
lds-reject-mixed-absolute-addresses.ll
…
lds-relocs.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
lds-run-twice-absolute-md.ll
[AIX] Fix AIX failures due to switch to internal shell (#160566)
2025-09-24 14:11:44 -04:00
lds-run-twice.ll
[AIX] Fix AIX failures due to switch to internal shell (#160566)
2025-09-24 14:11:44 -04:00
lds-size-hsa-gfx950.ll
…
lds-size-hsa-gfx1250.ll
[AMDGPU] update LDS block size for gfx1250 (#167614)
2025-11-17 16:03:47 -08:00
lds-size-pal-gfx950.ll
…
lds-size-pal-gfx1250.ll
[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)
2025-08-14 12:52:00 -07:00
lds-size-pal-metadata.ll
[AMDGPU] Fix hw stage metadata setting for unsigned values (#154502)
2025-09-02 10:42:11 +02:00
lds-size.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
lds-zero-initializer.ll
…
legalize-amdgcn.dead.mir
[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)
2025-10-28 09:57:31 +00:00
legalize-amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.load.format.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.load.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.buffer.store.format.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.buffer.store.format.f32.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.buffer.store.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.load.format.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.load.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.buffer.store.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.tbuffer.load.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.ptr.tbuffer.store.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.tbuffer.load.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
legalize-amdgcn.raw.tbuffer.store.f16.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-amdgcn.raw.tbuffer.store.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalize-fp-load-invariant.ll
…
legalize-soffset-mbuf.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
legalizedag-bug-expand-setcc.ll
…
licm-regpressure.mir
…
licm-valu.mir
…
licm-wwm.mir
…
limit-soft-clause-reg-pressure.mir
…
lit.local.cfg
…
literal64.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
literal-constant-like-operand-instruction-size.ll
…
literals.ll
…
live-interval-bug-in-rename-independent-subregs.mir
RenameIndependentSubregs: try to only implicit def used subregs (#167486)
2025-11-20 09:28:34 +09:00
liveness.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
liveout-implicit-def-subreg-redef-blender-verifier-error.mir
…
livevars-implicitdef.mir
[LiveVariables] Mark use without implicit if defined at instr (#119446)
2025-08-18 08:34:59 -04:00
llc-pipeline-npm.ll
[AMDGPU] Remove AMDGPUArgumentUsageInfo pass (#182490)
2026-02-23 18:47:01 +05:30
llc-pipeline.ll
[CodeGenPrepare][NFC] Get BPI/BFI from pass/analysis manager (#186651)
2026-03-15 17:41:22 +01:00
llvm.amdgcn.add.min.max.ll
[AMDGPU] Add intrinsics for v_[pk]_add_{min|max}_* instructions (#164731)
2025-10-22 17:46:33 -07:00
llvm.amdgcn.addrspacecast.nonnull.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
llvm.amdgcn.alignbyte.ll
…
llvm.amdgcn.atomic.dec.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
llvm.amdgcn.atomic.inc.ll
[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)
2025-11-17 12:17:26 +01:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU] Support bfloat comparison for ballot intrinsic (#165495)
2025-10-30 09:44:25 -07:00
llvm.amdgcn.ballot.i64.ll
[AMDGPU] Support bfloat comparison for ballot intrinsic (#165495)
2025-10-30 09:44:25 -07:00
llvm.amdgcn.ballot.i64.wave32.ll
…
llvm.amdgcn.bitop3.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.bitreplicate.ll
…
llvm.amdgcn.buffer.load-last-use.ll
…
llvm.amdgcn.buffer.load.dwordx3.ll
…
llvm.amdgcn.buffer.load.lds.err.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer load lds intrinsics (#180998)
2026-02-12 14:04:58 -08:00
llvm.amdgcn.buffer.store.dwordx3.ll
…
llvm.amdgcn.bvh8_intersect_ray.ll
…
llvm.amdgcn.class.f16.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn.class (#178827)
2026-03-20 12:50:06 -07:00
llvm.amdgcn.class.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn.class (#178827)
2026-03-20 12:50:06 -07:00
llvm.amdgcn.cluster.id.ll
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
2025-11-21 19:42:17 +05:30
llvm.amdgcn.cluster.load.async.to.lds.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cluster.load.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cluster.workgroup.id.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cluster.workgroup.max.flat.id.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cluster.workgroup.max.id.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cooperative.atomic-agent.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
llvm.amdgcn.cooperative.atomic-basic.ll
[AMDGPU] Add gfx1251 runlines to cooperative atomcis tests. NFC (#159437)
2025-09-17 14:08:05 -07:00
llvm.amdgcn.cooperative.atomic-singlethread.ll
[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)
2025-09-04 09:19:25 +00:00
llvm.amdgcn.cooperative.atomic-system.ll
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
2026-01-15 03:25:03 -08:00
llvm.amdgcn.cooperative.atomic-wavefront.ll
[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)
2025-09-04 09:19:25 +00:00
llvm.amdgcn.cooperative.atomic-workgroup.ll
[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)
2025-09-10 10:18:11 +02:00
llvm.amdgcn.cos.bf16.ll
…
llvm.amdgcn.cos.f16.ll
…
llvm.amdgcn.cos.ll
…
llvm.amdgcn.cubeid.ll
…
llvm.amdgcn.cubema.ll
…
llvm.amdgcn.cubesc.ll
…
llvm.amdgcn.cubetc.ll
…
llvm.amdgcn.cvt.f16.fp8.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.f32.fp8.err.ll
…
llvm.amdgcn.cvt.fp8.dpp.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.fp8.dpp.mir
[AMDGPU] Add fp8/bf8 conversion instructions for gfx1170 (#180191)
2026-02-09 13:56:43 +01:00
llvm.amdgcn.cvt.fp8.e5m3.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.fp8.f16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.fp8.ll
[AMDGPU][True16] change vdst_in regclass and remove opsel for cvt_pk_f8_fp32 pattern (#179995)
2026-02-26 10:19:18 -05:00
llvm.amdgcn.cvt.off.f32.i4.ll
…
llvm.amdgcn.cvt.pk.f16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.pk.i16.ll
AMDGPU/GlobalISel: RegBankLegalize cvt_pk_u16/i16/pkrtz (#185534)
2026-03-11 13:59:32 -07:00
llvm.amdgcn.cvt.pk.u16.ll
AMDGPU/GlobalISel: RegBankLegalize cvt_pk_u16/i16/pkrtz (#185534)
2026-03-11 13:59:32 -07:00
llvm.amdgcn.cvt.pknorm.i16.ll
…
llvm.amdgcn.cvt.pknorm.u16.ll
…
llvm.amdgcn.cvt.pkrtz.ll
AMDGPU/GlobalISel: RegBankLegalize cvt_pk_u16/i16/pkrtz (#185534)
2026-03-11 13:59:32 -07:00
llvm.amdgcn.cvt.sat.pk.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.scale.pk.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.scalef32.pk8.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
[AMDGPU] Fix destination op_sel for v_cvt_scale32_* and v_cvt_sr_* (#151411)
2025-07-30 16:15:50 -07:00
llvm.amdgcn.cvt.scalef32.pk.ll
…
llvm.amdgcn.cvt.scalef32.sr.ll
[AMDGPU] Fix destination op_sel for v_cvt_scale32_* and v_cvt_sr_* (#151411)
2025-07-30 16:15:50 -07:00
llvm.amdgcn.cvt.scalef32.sr.pk16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
[AMDGPU] Fix destination op_sel for v_cvt_scale32_* and v_cvt_sr_* (#151411)
2025-07-30 16:15:50 -07:00
llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.cvt.scalef32.sr.pk.ll
…
llvm.amdgcn.cvt.sr.ll
…
llvm.amdgcn.cvt.sr.pk.bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.dead.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_PHI (#179735)
2026-03-06 14:01:50 +01:00
llvm.amdgcn.dispatch.id.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
llvm.amdgcn.dispatch.ptr.ll
…
llvm.amdgcn.div.fixup.f16.ll
…
llvm.amdgcn.div.fixup.ll
…
llvm.amdgcn.div.fmas.ll
[AMDGPU] Update codegen tests for PR #154069 (#154862)
2025-08-22 07:58:21 -06:00
llvm.amdgcn.div.scale.ll
…
llvm.amdgcn.dot4.f32.ll
[AMDGPU] Add dot4 fp8/bf8 instructions for gfx1170 (#180516)
2026-02-10 12:14:49 +01:00
llvm.amdgcn.ds.add.gs.reg.rtn.ll
AMDGPU/GlobalISel: RegBankLegalize rules for ds_add/sub_gs_reg_rtn (#185991)
2026-03-18 09:00:13 -07:00
llvm.amdgcn.ds.append.ll
…
llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
…
llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
…
llvm.amdgcn.ds.bpermute.fi.b32.ll
…
llvm.amdgcn.ds.bpermute.ll
…
llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
AMDGPU/GlobalISel: RegBankLegalize rules for ds_bvh_stack (#186219)
2026-03-13 11:50:22 -07:00
llvm.amdgcn.ds.bvh.stack.rtn.ll
AMDGPU/GlobalISel: RegBankLegalize rules for ds_bvh_stack (#186219)
2026-03-13 11:50:22 -07:00
llvm.amdgcn.ds.consume.ll
…
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
llvm.amdgcn.ds.gws.barrier.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
llvm.amdgcn.ds.gws.init.ll
…
llvm.amdgcn.ds.gws.sema.br.ll
…
llvm.amdgcn.ds.gws.sema.p.ll
…
llvm.amdgcn.ds.gws.sema.release.all.ll
…
llvm.amdgcn.ds.gws.sema.v.ll
…
llvm.amdgcn.ds.ordered.add-errors.ll
…
llvm.amdgcn.ds.ordered.add-unsupported.ll
…
llvm.amdgcn.ds.ordered.add.gfx10.ll
…
llvm.amdgcn.ds.ordered.add.gfx11.ll
[AMDGPU] TableGen-erate SDNode descriptions (#168248)
2025-11-17 00:10:07 +00:00
llvm.amdgcn.ds.ordered.add.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
llvm.amdgcn.ds.ordered.swap.ll
…
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.read.tr.gfx950.ll
AMDGPU/GlobalISel: RegBankLegalize rules for ds_read_tr* (#186006)
2026-03-16 10:20:09 -07:00
llvm.amdgcn.ds.sub.gs.reg.rtn.ll
AMDGPU/GlobalISel: RegBankLegalize rules for ds_add/sub_gs_reg_rtn (#185991)
2026-03-18 09:00:13 -07:00
llvm.amdgcn.ds.swizzle.ll
AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_ds_swizzle (#186024)
2026-03-13 15:13:50 -07:00
llvm.amdgcn.dual_intersect_ray.ll
…
llvm.amdgcn.exp2.ll
…
llvm.amdgcn.exp.bf16.ll
…
llvm.amdgcn.exp.compr.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
llvm.amdgcn.exp.ll
AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_exp/exp_row (#181956)
2026-03-06 14:03:14 -08:00
llvm.amdgcn.exp.prim.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
llvm.amdgcn.exp.row.ll
AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_exp/exp_row (#181956)
2026-03-06 14:03:14 -08:00
llvm.amdgcn.fcmp.w32.ll
…
llvm.amdgcn.fcmp.w64.ll
…
llvm.amdgcn.fdiv.fast.ll
…
llvm.amdgcn.fdot2.bf16.bf16.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
llvm.amdgcn.fdot2.f16.f16.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
llvm.amdgcn.fdot2.f32.bf16.ll
…
llvm.amdgcn.fdot2.ll
[AMDGPU] Remove V_DOT2ACC_F32_F16 from gfx1170 (#182088)
2026-02-18 20:16:22 +01:00
llvm.amdgcn.flat.prefetch.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.fma.legacy.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for fma_legacy (#178759)
2026-01-30 08:52:48 -08:00
llvm.amdgcn.fmad.ftz.f16.ll
…
llvm.amdgcn.fmad.ftz.ll
…
llvm.amdgcn.fmed3.f16.ll
…
llvm.amdgcn.fmed3.ll
…
llvm.amdgcn.fmul.legacy.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
llvm.amdgcn.fract.f16.ll
…
llvm.amdgcn.fract.ll
…
llvm.amdgcn.frexp.exp.f16.ll
…
llvm.amdgcn.frexp.exp.ll
…
llvm.amdgcn.frexp.mant.f16.ll
…
llvm.amdgcn.frexp.mant.ll
…
llvm.amdgcn.global.atomic.csub.ll
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
2025-12-05 12:37:33 +00:00
llvm.amdgcn.global.atomic.ordered.add.b64.ll
AMDGPU/GlobalISel: RegBankLegalize for global atomic ordered add (#180829)
2026-02-11 09:30:11 -08:00
llvm.amdgcn.global.load.async.to.lds.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.global.load.lds.err.ll
…
llvm.amdgcn.global.load.lds.gfx950.ll
…
llvm.amdgcn.global.load.lds.ll
…
llvm.amdgcn.global.load.tr-w32.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for global_load_tr_b* (#178545)
2026-01-29 10:49:26 -08:00
llvm.amdgcn.global.load.tr-w64.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for global_load_tr_b* (#178545)
2026-01-29 10:49:26 -08:00
llvm.amdgcn.global.prefetch.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.global.store.async.from.lds.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.groupstaticsize.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for groupstaticsize (#178618)
2026-01-29 11:00:44 -08:00
llvm.amdgcn.icmp.w32.ll
…
llvm.amdgcn.icmp.w64.ll
…
llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
llvm.amdgcn.iglp.opt.exp.large.mir
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
llvm.amdgcn.iglp.opt.exp.simple.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.iglp.opt.exp.small.mir
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
llvm.amdgcn.iglp.opt.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.iglp.opt.single.2b.mir
…
llvm.amdgcn.iglp.opt.single.2c.mir
…
llvm.amdgcn.image.a16.dim.ll
…
llvm.amdgcn.image.a16.encode.ll
…
llvm.amdgcn.image.atomic.dim.gfx90a.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
llvm.amdgcn.image.atomic.dim.ll
…
llvm.amdgcn.image.atomic.flt.ll
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
llvm.amdgcn.image.atomic.noret.ll
[AMDGPU] Support image atomic no return instructions (#150742)
2025-10-29 10:42:15 +08:00
llvm.amdgcn.image.atomic.pk.add.ll
[AMDGPU] Support image atomic no return instructions (#150742)
2025-10-29 10:42:15 +08:00
llvm.amdgcn.image.d16.dim.ll
…
llvm.amdgcn.image.dim.gfx90a.ll
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
llvm.amdgcn.image.dim.ll
…
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Regenerate test case to cover gfx10 check lines. (#154909)
2025-08-22 15:00:28 +05:30
llvm.amdgcn.image.gather4.d16.dim.ll
…
llvm.amdgcn.image.gather4.dim.ll
…
llvm.amdgcn.image.gather4.o.dim.ll
…
llvm.amdgcn.image.getlod.dim.ll
…
llvm.amdgcn.image.load.2dmsaa.ll
…
llvm.amdgcn.image.load.a16.d16.ll
…
llvm.amdgcn.image.load.a16.ll
…
llvm.amdgcn.image.msaa.load.ll
…
llvm.amdgcn.image.msaa.load.x.ll
…
llvm.amdgcn.image.nsa.ll
…
llvm.amdgcn.image.sample.a16.dim.ll
…
llvm.amdgcn.image.sample.cd.a16.dim.ll
…
llvm.amdgcn.image.sample.cd.dim.ll
…
llvm.amdgcn.image.sample.cd.g16.encode.ll
…
llvm.amdgcn.image.sample.cd.g16.ll
…
llvm.amdgcn.image.sample.d16.dim.ll
…
llvm.amdgcn.image.sample.dim.gfx90a.ll
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
llvm.amdgcn.image.sample.dim.ll
…
llvm.amdgcn.image.sample.g16.a16.dim.ll
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
llvm.amdgcn.image.sample.g16.encode.ll
…
llvm.amdgcn.image.sample.g16.ll
…
llvm.amdgcn.image.sample.noret.ll
AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (#179810)
2026-02-20 13:34:13 +01:00
llvm.amdgcn.image.sample.o.dim.ll
…
llvm.amdgcn.image.store.a16.d16.ll
…
llvm.amdgcn.image.store.a16.ll
…
llvm.amdgcn.implicit.ptr.buffer.hsa.ll
…
llvm.amdgcn.implicit.ptr.buffer.ll
…
llvm.amdgcn.implicitarg.ptr.ll
…
llvm.amdgcn.init.exec.ll
…
llvm.amdgcn.init.exec.wave32.ll
…
llvm.amdgcn.init.whole.wave-w32.ll
[AMDGPU] Make chain functions receive a stack pointer (#184616)
2026-03-06 11:01:42 +01:00
llvm.amdgcn.init.whole.wave-w64.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.interp.f16.ll
…
llvm.amdgcn.interp.inreg.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
llvm.amdgcn.interp.ll
…
llvm.amdgcn.intersect_ray.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.inverse.ballot.i32.ll
AMDGPU: llvm.amdgcn.inverse.ballot needs to be convergent (#155725)
2025-08-27 19:40:27 -07:00
llvm.amdgcn.inverse.ballot.i64.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.is.private.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.is.shared.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll
…
llvm.amdgcn.kill.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
llvm.amdgcn.lds.direct.load.ll
…
llvm.amdgcn.lds.kernel.id.ll
…
llvm.amdgcn.lds.param.load.ll
AMDGPU/GlobalISel: RegBankLegalize rules for lds_param_load (#186035)
2026-03-13 10:17:20 -07:00
llvm.amdgcn.lerp.ll
[AMDGPU] Adding instruction specific features (#167809)
2025-11-19 11:06:00 +08:00
llvm.amdgcn.load.monitor.gfx1250.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.load.to.lds.gfx950.ll
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
llvm.amdgcn.load.to.lds.ll
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
llvm.amdgcn.load.tr.gfx1250.w32.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.log.bf16.ll
…
llvm.amdgcn.log.clamp.ll
…
llvm.amdgcn.log.ll
…
llvm.amdgcn.make.buffer.rsrc.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
llvm.amdgcn.mbcnt.ll
[AMDGPU][GlobalISel][NFC] Change mbcnt test to use new-reg-bank-select (#187772)
2026-03-20 18:25:16 -07:00
llvm.amdgcn.mfma.bf16.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.form.ll
AMDGPU: Track minNumAGPRs in MFI instead of mayUseAGPRs (#161996)
2025-10-07 08:48:45 +09:00
llvm.amdgcn.mfma.gfx90a.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.gfx942.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.gfx950.bf16.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.gfx950.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.i8.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
llvm.amdgcn.mfma.xf32.gfx942.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.mov.dpp8.ll
…
llvm.amdgcn.mov.dpp.gfx1251.ll
[AMDGPU] gfx1251 VOP1 dpp support (#159637)
2025-09-18 13:42:06 -07:00
llvm.amdgcn.mov.dpp.ll
…
llvm.amdgcn.mqsad.pk.u16.u8.ll
…
llvm.amdgcn.mqsad.u32.u8.ll
…
llvm.amdgcn.msad.u8.ll
…
llvm.amdgcn.mul.i24.ll
…
llvm.amdgcn.mul.u24.ll
…
llvm.amdgcn.mulhi.i24.ll
[AMDGPU][GlobalISel] Add RegBankLegalize mul24 and fmul.legacy (#173123)
2025-12-23 12:35:28 -08:00
llvm.amdgcn.mulhi.u24.ll
[AMDGPU][GlobalISel] Add RegBankLegalize mul24 and fmul.legacy (#173123)
2025-12-23 12:35:28 -08:00
llvm.amdgcn.perm.ll
…
llvm.amdgcn.perm.pk.ll
[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)
2025-09-10 11:03:58 +02:00
llvm.amdgcn.permlane16.swap.ll
…
llvm.amdgcn.permlane16.var.ll
…
llvm.amdgcn.permlane32.swap.ll
…
llvm.amdgcn.permlane64.ll
[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)
2025-10-30 12:32:32 +05:30
llvm.amdgcn.permlane64.ptr.ll
[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)
2025-10-30 12:32:32 +05:30
llvm.amdgcn.permlane.gfx1250.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.permlane.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.permlane.ptr.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.pops.exiting.wave.id.ll
AMDGPU/GlobalISel: RegBankLegalize rules for pops_exiting_wave_id (#187778)
2026-03-20 18:26:30 -07:00
llvm.amdgcn.prng.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_prng_b32 (#178741)
2026-01-30 08:39:27 -08:00
llvm.amdgcn.ps.live.ll
…
llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
[AMDGPU] Add legalization rules for G_AMDGPU_BUFFER_ATOMIC_FADD (#175258)
2026-02-20 11:30:05 +00:00
llvm.amdgcn.qsad.pk.u16.u8.ll
…
llvm.amdgcn.quadmask.ll
[AMDGPU] s_quadmask* implicitly defines SCC (#161582)
2025-10-02 10:29:09 -05:00
llvm.amdgcn.queue.ptr.ll
…
llvm.amdgcn.raw.atomic.buffer.load.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.buffer.atomic.ll
…
llvm.amdgcn.raw.buffer.load.format.d16.ll
…
llvm.amdgcn.raw.buffer.load.format.ll
…
llvm.amdgcn.raw.buffer.load.lds.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer load lds intrinsics (#180998)
2026-02-12 14:04:58 -08:00
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
llvm.amdgcn.raw.buffer.load.tfe.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
…
llvm.amdgcn.raw.buffer.store.format.ll
…
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
[AMDGPU] Fix buffer addressing mode matching (#152584)
2025-08-07 14:23:41 -07:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.raw.ptr.buffer.atomic.ll
…
llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.amdgcn.raw.ptr.buffer.load.bf16.xfail.ll
…
llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
…
llvm.amdgcn.raw.ptr.buffer.load.format.ll
…
llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer load lds intrinsics (#180998)
2026-02-12 14:04:58 -08:00
llvm.amdgcn.raw.ptr.buffer.load.lds.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer load lds intrinsics (#180998)
2026-02-12 14:04:58 -08:00
llvm.amdgcn.raw.ptr.buffer.load.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.raw.ptr.buffer.store.bf16.xfail.ll
…
llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
…
llvm.amdgcn.raw.ptr.buffer.store.format.ll
…
llvm.amdgcn.raw.ptr.buffer.store.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
Reapply [IR] Remove options to make scalable TypeSize access a warning (#156336)
2025-09-03 11:12:11 +02:00
llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
…
llvm.amdgcn.raw.ptr.tbuffer.load.ll
…
llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
…
llvm.amdgcn.raw.ptr.tbuffer.store.ll
…
llvm.amdgcn.raw.tbuffer.load.d16.ll
…
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)
2025-09-30 07:56:23 -07:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
[AMDGPU][GlobalISel] Add tbuffer store d16 RegBankLegalize rule (#179411)
2026-02-03 09:14:51 -08:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
llvm.amdgcn.rcp.bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.rcp.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
llvm.amdgcn.rcp.legacy.ll
…
llvm.amdgcn.rcp.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
llvm.amdgcn.readfirstlane.ll
[AMDGPU] [GlobalIsel] Enabling lit tests for new regbank select (#180680)
2026-02-11 07:52:47 +05:30
llvm.amdgcn.readfirstlane.m0.ll
…
llvm.amdgcn.readfirstlane.ptr.ll
…
llvm.amdgcn.readlane.ll
AMDGPU/GlobalISel: RegBankLegalize rules for readlane, writelane (#187386)
2026-03-20 08:17:11 -07:00
llvm.amdgcn.readlane.ptr.ll
…
llvm.amdgcn.reduce.add.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
llvm.amdgcn.reduce.and.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
llvm.amdgcn.reduce.fadd.ll
[AMDGPU] DPP implementations for Wave Reduction (#187214)
2026-03-23 11:41:12 +05:30
llvm.amdgcn.reduce.fmax.ll
[AMDGPU] DPP implementations for Wave Reduction (#187214)
2026-03-23 11:41:12 +05:30
llvm.amdgcn.reduce.fmin.ll
[AMDGPU] DPP implementations for Wave Reduction (#187214)
2026-03-23 11:41:12 +05:30
llvm.amdgcn.reduce.fsub.ll
[AMDGPU] DPP implementations for Wave Reduction (#187214)
2026-03-23 11:41:12 +05:30
llvm.amdgcn.reduce.max.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
llvm.amdgcn.reduce.min.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
llvm.amdgcn.reduce.or.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
llvm.amdgcn.reduce.sub.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
llvm.amdgcn.reduce.umax.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
llvm.amdgcn.reduce.umin.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
llvm.amdgcn.reduce.xor.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
llvm.amdgcn.rsq.bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.rsq.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
llvm.amdgcn.rsq.legacy.ll
…
llvm.amdgcn.rsq.ll
…
llvm.amdgcn.s.barrier.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_barrier/wave_barrier (#186512)
2026-03-16 08:55:07 -07:00
llvm.amdgcn.s.barrier.signal.isfirst.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.s.barrier.signal.isfirst.mir
[AMDGPU][SIInsertWaitcnts] Track SCC. Insert KM_CNT waits for SCC writes. (#157843)
2025-09-18 14:41:01 +02:00
llvm.amdgcn.s.buffer.load.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.s.buffer.prefetch.data.ll
…
llvm.amdgcn.s.dcache.inv.ll
…
llvm.amdgcn.s.dcache.inv.vol.ll
…
llvm.amdgcn.s.dcache.wb.ll
…
llvm.amdgcn.s.dcache.wb.vol.ll
…
llvm.amdgcn.s.decperflevel.ll
…
llvm.amdgcn.s.get.waveid.in.workgroup.ll
…
llvm.amdgcn.s.getpc.ll
…
llvm.amdgcn.s.getreg.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_getreg (#186253)
2026-03-13 15:12:00 -07:00
llvm.amdgcn.s.incperflevel.ll
…
llvm.amdgcn.s.memrealtime.ll
…
llvm.amdgcn.s.memtime.ll
…
llvm.amdgcn.s.monitor.sleep.ll
…
llvm.amdgcn.s.nop.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_setprio/sethalt/nop (#186244)
2026-03-13 11:33:59 -07:00
llvm.amdgcn.s.prefetch.data.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_sleep_var, s_prefetch (#187382)
2026-03-19 11:12:29 -07:00
llvm.amdgcn.s.sethalt.ll
[AMDGPU] Add s_sethalt to hasUnwantedEffectsWhenEXECEmpty (#186745)
2026-03-17 10:32:07 +08:00
llvm.amdgcn.s.setprio.inc.wg.ll
…
llvm.amdgcn.s.setprio.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_setprio/sethalt/nop (#186244)
2026-03-13 11:33:59 -07:00
llvm.amdgcn.s.setreg.ll
…
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.s.sleep.var.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_sleep_var, s_prefetch (#187382)
2026-03-19 11:12:29 -07:00
llvm.amdgcn.s.ttracedata.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_ttracedata (#187342)
2026-03-19 08:56:44 -07:00
llvm.amdgcn.s.wait.event.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_wait intrinsics (#186254)
2026-03-16 10:42:58 -07:00
llvm.amdgcn.s.wait.gfx12.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_wait intrinsics (#186254)
2026-03-16 10:42:58 -07:00
llvm.amdgcn.s.wait.gfx1250.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.s.waitcnt_gfx1250.ll
[AMDGPU] gfx1250 waitcnt related codegen tests update. NFC (#155317)
2025-08-25 15:23:59 -07:00
llvm.amdgcn.s.waitcnt.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_wait intrinsics (#186254)
2026-03-16 10:42:58 -07:00
llvm.amdgcn.sad.hi.u8.ll
…
llvm.amdgcn.sad.u8.ll
…
llvm.amdgcn.sad.u16.ll
…
llvm.amdgcn.sbfe.ll
[AMDGPU]Fix compute num sign bits unsigned underflow (#182723)
2026-02-25 09:55:09 +00:00
llvm.amdgcn.sched.barrier.ll
…
llvm.amdgcn.sched.group.barrier.gfx11.ll
[DAG] Remove AssertZext if the input is masked (#146052)
2025-07-29 13:05:30 +02:00
llvm.amdgcn.sched.group.barrier.gfx12.ll
[DAG] Remove AssertZext if the input is masked (#146052)
2025-07-29 13:05:30 +02:00
llvm.amdgcn.sched.group.barrier.iterative.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.sched.group.barrier.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
llvm.amdgcn.sdot2.ll
…
llvm.amdgcn.sdot4.ll
…
llvm.amdgcn.sdot8.ll
…
llvm.amdgcn.sendmsg.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_sendmsg (#187361)
2026-03-19 09:15:38 -07:00
llvm.amdgcn.sendmsg.rtn.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_sendmsg (#187361)
2026-03-19 09:15:38 -07:00
llvm.amdgcn.set.inactive.chain.arg.ll
[AMDGPU] Make chain functions receive a stack pointer (#184616)
2026-03-06 11:01:42 +01:00
llvm.amdgcn.set.inactive.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
llvm.amdgcn.sffbh.ll
AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_sffbh (#180099)
2026-02-09 09:18:03 -08:00
llvm.amdgcn.sin.bf16.ll
…
llvm.amdgcn.sin.f16.ll
…
llvm.amdgcn.sin.ll
…
llvm.amdgcn.smfmac.gfx950.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
llvm.amdgcn.softwqm.ll
…
llvm.amdgcn.sqrt.bf16.ll
…
llvm.amdgcn.sqrt.f16.ll
…
llvm.amdgcn.sqrt.ll
…
llvm.amdgcn.struct.atomic.buffer.load.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
…
llvm.amdgcn.struct.buffer.atomic.ll
…
llvm.amdgcn.struct.buffer.load.format.d16.ll
…
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for TFE buffer loads (#179529)
2026-02-05 13:42:11 -08:00
llvm.amdgcn.struct.buffer.load.format.v3f16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.buffer.load.lds.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer load lds intrinsics (#180998)
2026-02-12 14:04:58 -08:00
llvm.amdgcn.struct.buffer.load.ll
…
llvm.amdgcn.struct.buffer.load.tfe.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.struct.buffer.store.format.d16.ll
…
llvm.amdgcn.struct.buffer.store.format.ll
…
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
…
llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
…
llvm.amdgcn.struct.ptr.buffer.atomic.ll
…
llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
…
llvm.amdgcn.struct.ptr.buffer.load.format.ll
…
llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer load lds intrinsics (#180998)
2026-02-12 14:04:58 -08:00
llvm.amdgcn.struct.ptr.buffer.load.lds.ll
AMDGPU/GlobalISel: Regbanklegalize rules for buffer load lds intrinsics (#180998)
2026-02-12 14:04:58 -08:00
llvm.amdgcn.struct.ptr.buffer.load.ll
…
llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
…
llvm.amdgcn.struct.ptr.buffer.store.format.ll
…
llvm.amdgcn.struct.ptr.buffer.store.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
…
llvm.amdgcn.struct.ptr.tbuffer.load.ll
…
llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
…
llvm.amdgcn.struct.ptr.tbuffer.store.ll
…
llvm.amdgcn.struct.tbuffer.load.d16.ll
…
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for buffer loads with formats (#161291)
2025-09-30 07:56:23 -07:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
[AMDGPU] Fix duplicate RUN lines in tests (#182286)
2026-02-19 16:07:20 +00:00
llvm.amdgcn.struct.tbuffer.store.ll
…
llvm.amdgcn.sudot4.ll
…
llvm.amdgcn.sudot8.ll
…
llvm.amdgcn.tanh.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.tbuffer.load.dwordx3.ll
…
llvm.amdgcn.tbuffer.store.dwordx3.ll
…
llvm.amdgcn.tensor.load.store.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.trig.preop.ll
…
llvm.amdgcn.ubfe.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
llvm.amdgcn.udot2.ll
…
llvm.amdgcn.udot4.ll
…
llvm.amdgcn.udot8.ll
…
llvm.amdgcn.unreachable.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
llvm.amdgcn.update.dpp.gfx90a.ll
…
llvm.amdgcn.update.dpp.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.waitcnt.out.order.ll
…
llvm.amdgcn.wave.barrier.ll
…
llvm.amdgcn.wave.id.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.wave.shuffle.ll
[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)
2026-02-03 11:10:28 +09:00
llvm.amdgcn.wavefrontsize.ll
…
llvm.amdgcn.wmma_32.ll
…
llvm.amdgcn.wmma_64.ll
…
llvm.amdgcn.wmma.gfx1250.w32.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.wmma.imm.gfx1250.w32.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.wmma.imod.gfx1250.w32.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.wmma.index.gfx1250.w32.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.amdgcn.workgroup.id.ll
…
llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
…
llvm.amdgcn.workitem.id.ll
…
llvm.amdgcn.wqm.demote.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
llvm.amdgcn.wqm.ll
…
llvm.amdgcn.wqm.vote.ll
…
llvm.amdgcn.writelane.ll
AMDGPU/GlobalISel: RegBankLegalize rules for readlane, writelane (#187386)
2026-03-20 08:17:11 -07:00
llvm.amdgcn.writelane.ptr.ll
…
llvm.ceil.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
llvm.cos.bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.cos.f16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
llvm.cos.ll
…
llvm.dbg.value.ll
…
llvm.deoptimize.ll
DAG: Check if deoptimize call is available before emitting it (#170940)
2025-12-29 21:48:28 +00:00
llvm.exp2.bf16.ll
AMDGPU: Directly use v2bf16 as register type for bf16 vectors. (#175761)
2026-01-13 17:48:38 +01:00
llvm.exp2.f64.ll
AMDGPU: Implement expansion for f64 exp (#182539)
2026-02-25 21:06:13 +01:00
llvm.exp2.ll
AMDGPU: Fix dead checks in test (#185613)
2026-03-10 11:20:04 +00:00
llvm.exp10.f64.ll
AMDGPU: Implement expansion for f64 exp (#182539)
2026-02-25 21:06:13 +01:00
llvm.exp10.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
llvm.exp.f64.ll
AMDGPU: Implement expansion for f64 exp (#182539)
2026-02-25 21:06:13 +01:00
llvm.exp.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
llvm.floor.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
llvm.fma.f16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
llvm.fmuladd.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
llvm.fptrunc.round.err.ll
…
llvm.fptrunc.round.ll
[AMDGPU] add back the true16 pattern for cvt_pk_rtz (#184857)
2026-03-05 16:35:15 -05:00
llvm.frexp.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
llvm.get.fpmode.ll
…
llvm.get.rounding.ll
…
llvm.is.fpclass.bf16.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
llvm.is.fpclass.f16.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
llvm.is.fpclass.ll
[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)
2026-02-11 09:06:28 -08:00
llvm.ldexp.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
llvm.log2.bf16.ll
AMDGPU: Directly use v2bf16 as register type for bf16 vectors. (#175761)
2026-01-13 17:48:38 +01:00
llvm.log2.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
llvm.log10.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
llvm.log.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
llvm.maximum.f16.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
llvm.maximum.f32.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
llvm.maximum.f64.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
llvm.maxnum.f16.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
llvm.memcpy.ll
AMDGPU: Use ELF mangling in data layout (#163011)
2025-10-13 03:01:45 +00:00
llvm.minimum.f16.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
llvm.minimum.f32.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
llvm.minimum.f64.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
llvm.minnum.f16.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
llvm.modf.ll
[AMDGPU][GlobalISel] Add lowering for G_FMODF (#180152)
2026-02-07 18:43:55 +00:00
llvm.mulo.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.pow-gfx9.ll
…
llvm.pow.ll
…
llvm.powi.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
llvm.prefetch.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.r600.cube.ll
…
llvm.r600.dot4.ll
…
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll
…
llvm.r600.recipsqrt.clamped.ll
…
llvm.r600.recipsqrt.ieee.ll
…
llvm.r600.tex.ll
…
llvm.rint.f16.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
llvm.rint.f64.ll
…
llvm.rint.ll
…
llvm.round.f64.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
llvm.round.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
llvm.set.rounding.ll
…
llvm.sin.bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.sin.f16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
llvm.sin.ll
[DAGCombiner] Remove most UnsafeFPMath references (#146295)
2025-08-22 15:27:25 +08:00
llvm.sponentry.ll
[AMDGPU] DPP implementations for Wave Reduction (#185814)
2026-03-18 13:11:53 +05:30
llvm.sqrt.bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
llvm.sqrt.f16.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
llvm.trunc.f16.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
lo16-hi16-illegal-copy.mir
…
lo16-hi16-physreg-copy.mir
…
lo16-lo16-physreg-copy-agpr.mir
…
lo16-lo16-physreg-copy-sgpr.mir
…
load-constant-always-uniform.ll
Revert "[AMDGPU] SelectionDAG divergence tracking should take into account Target divergency. (#147560)" (#152548)
2025-08-08 09:05:59 +01:00
load-constant-f32.ll
…
load-constant-f64.ll
…
load-constant-i1.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
load-constant-i8.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
load-constant-i16.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
load-constant-i32.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
load-constant-i64.ll
…
load-global-f32.ll
…
load-global-f64.ll
…
load-global-i1.ll
…
load-global-i8.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
load-global-i16.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
load-global-i32.ll
[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
2026-02-25 15:24:54 -08:00
load-global-i64.ll
…
load-global-invariant.ll
AMDGPU: Add baseline test for split/widen invariant loads (#168913)
2025-11-21 13:53:14 -05:00
load-hi16.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
load-input-fold.ll
…
load-lo16.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
load-local-f32-no-ds128.ll
…
load-local-f32.ll
…
load-local-f64.ll
…
load-local-i1.ll
…
load-local-i8.ll
…
load-local-i16.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
load-local-i32.ll
…
load-local-i64.ll
…
load-local-redundant-copies.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
load-local.96.ll
…
load-local.128.ll
…
load-range-metadata-assert.ll
…
load-range-metadata-sign-bits.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
load-saddr-offset-imm.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
load-select-ptr.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
load-store-cnt.ll
…
load-store-opt-addc0.mir
…
load-store-opt-dlc.mir
…
load-store-opt-ds-regclass-constrain.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
load-store-opt-scale-offset.mir
[AMDGPU] Enable XNACK on gfx1250 (#161457)
2025-10-03 11:04:55 -04:00
load-store-opt-scc.mir
…
load-weird-sizes.ll
…
local-64.ll
…
local-atomicrmw-fadd.ll
[AMDGPU] Simplify legalization of PHI operands (#177352)
2026-01-26 15:39:13 +00:00
local-atomicrmw-fmax.ll
[AMDGPU] Simplify legalization of PHI operands (#177352)
2026-01-26 15:39:13 +00:00
local-atomicrmw-fmin.ll
[AMDGPU] Simplify legalization of PHI operands (#177352)
2026-01-26 15:39:13 +00:00
local-atomicrmw-fsub.ll
[AMDGPU] Simplify legalization of PHI operands (#177352)
2026-01-26 15:39:13 +00:00
local-atomics64.ll
…
local-atomics.ll
…
local-memory.amdgcn.ll
…
local-memory.ll
…
local-memory.r600.ll
…
local-stack-alloc-add-references.gfx8.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
local-stack-alloc-add-references.gfx9.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
local-stack-alloc-add-references.gfx10.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
local-stack-alloc-block-sp-reference.ll
[LowerMemIntrinsics] Optimize memset lowering (#169040)
2026-02-04 13:35:13 +01:00
local-stack-alloc-sort-framerefs.mir
[CodeGen] Consider imm offsets when sorting framerefs (#171012)
2026-01-08 17:48:30 -05:00
local-stack-slot-offset.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
long-branch-reserve-register.ll
…
loop_break.ll
…
loop_exit_with_xor.ll
…
loop_header_nopred.mir
…
loop-address.ll
…
loop-header-align-gfx950.mir
[AMDGPU] Align loop headers to prevent instruction fetch split on GFX950 (#181999)
2026-02-19 14:18:44 -05:00
loop-idiom.ll
…
loop-live-out-copy-undef-subrange.ll
…
loop-on-function-argument.ll
…
loop-prefetch-data.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
loop-prefetch.ll
…
loop-vector-sink.ll
[AMDGPU] Enable sinking of free vector ops that will be folded into their uses (#162580)
2026-02-09 14:14:31 -05:00
lower-brcond-with-xor.ll
[AMDGPU] Support xor cond, -1 when lowering BRCOND (#160341)
2025-09-23 17:16:21 -04:00
lower-buffer-fat-pointers-calls.ll
…
lower-buffer-fat-pointers-constants.ll
[AMDGPU][LowerBufferFatPointers] Fix lack of rewrite when loading/storing null (#154128)
2025-08-18 12:32:54 -05:00
lower-buffer-fat-pointers-contents-legalization.ll
…
lower-buffer-fat-pointers-control-flow.ll
[AMDGPU][LowerBufferFatPointers] Fix crash with select false (#166471)
2025-11-05 19:21:52 +00:00
lower-buffer-fat-pointers-dead-intrinsics.ll
[AMDGPU][LowerBufferFatPointers] Erase dead ptr(7) intrinsics (#160798)
2025-09-29 10:46:45 -05:00
lower-buffer-fat-pointers-lastuse-metadata.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
lower-buffer-fat-pointers-mem-transfer.ll
[LowerMemIntrinsics][AMDGPU] Optimize memset.pattern lowering (#185901)
2026-03-13 10:37:33 +01:00
lower-buffer-fat-pointers-memops.ll
…
lower-buffer-fat-pointers-nontemporal-metadata.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
lower-buffer-fat-pointers-p7-in-memory.ll
…
lower-buffer-fat-pointers-pointer-ops.ll
[LangRef] Specify icmp on pointers to only compare address (#163936)
2025-12-04 15:24:23 +00:00
lower-buffer-fat-pointers-unoptimized-debug-data.ll
[RemoveDIs][AMDGPU] Replace defunct getAssignmentMarkers call (#153212)
2025-08-12 17:20:38 +01:00
lower-control-flow-live-intervals.mir
…
lower-control-flow-live-variables-update.mir
…
lower-control-flow-live-variables-update.xfail.mir
…
lower-control-flow-other-terminators.mir
…
lower-ctor-dtor-constexpr-alias.ll
[AMDGPUCtorDtorLowering] Remove unnecessary pointer arithmetic (#182869)
2026-02-23 17:04:49 +01:00
lower-ctor-dtor-declaration.ll
…
lower-ctor-dtor-existing.ll
…
lower-ctor-dtor.ll
[AMDGPUCtorDtorLowering] Remove unnecessary pointer arithmetic (#182869)
2026-02-23 17:04:49 +01:00
lower-empty-ctor-dtor.ll
…
lower-i1-copies-clear-kills.mir
…
lower-i1-copies-implicit-def-unstructured-loop.mir
…
lower-indirect-lds-references.ll
…
lower-intrinsics-barriers.ll
AMDGPU: Refactor lowering of s_barrier to split barriers (#154648)
2025-08-28 07:01:20 -07:00
lower-intrinsics-cluster-barrier.ll
[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)
2025-09-16 14:49:48 -07:00
lower-intrinsics-split-barriers.ll
AMDGPU: Refactor lowering of s_barrier to split barriers (#154648)
2025-08-28 07:01:20 -07:00
lower-kernargs.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
lower-kernel-and-module-lds.ll
…
lower-kernel-lds-constexpr.ll
[ReplaceConstant] Don't create instructions for the same constant multiple times in the same basic block (#169141)
2025-11-26 22:44:40 -05:00
lower-kernel-lds-super-align.ll
…
lower-kernel-lds.ll
…
lower-lds-struct-aa-memcpy.ll
Revert "CodeGen: Record MMOs in finalizeBundle" (#166520)
2025-11-05 11:11:08 +01:00
lower-lds-struct-aa-merge.ll
…
lower-lds-struct-aa.ll
Revert "CodeGen: Record MMOs in finalizeBundle" (#166520)
2025-11-05 11:11:08 +01:00
lower-lds-with-alias-scope.ll
…
lower-lds-with-noalias.ll
…
lower-mem-intrinsics-threshold.ll
[LowerMemIntrinsics] Optimize memset lowering (#169040)
2026-02-04 13:35:13 +01:00
lower-mem-intrinsics.ll
[LowerMemIntrinsics] Optimize memset lowering (#169040)
2026-02-04 13:35:13 +01:00
lower-module-lds-all-indirect-accesses.ll
[AMDGPULowerLDS] Avoid unnecessary ptrtoint/inttoptr roundtrip (#181671)
2026-02-17 09:28:01 +01:00
lower-module-lds-check-metadata.ll
…
lower-module-lds-constantexpr-phi.ll
…
lower-module-lds-constantexpr.ll
[ReplaceConstant] Don't create instructions for the same constant multiple times in the same basic block (#169141)
2025-11-26 22:44:40 -05:00
lower-module-lds-inactive.ll
…
lower-module-lds-indirect-extern-uses-max-reachable-alignment.ll
[AMDGPULowerLDS] Avoid unnecessary ptrtoint/inttoptr roundtrip (#181671)
2026-02-17 09:28:01 +01:00
lower-module-lds-offsets.ll
…
lower-module-lds-precise-allocate-to-module-struct.ll
[AMDGPULowerLDS] Avoid unnecessary ptrtoint/inttoptr roundtrip (#181671)
2026-02-17 09:28:01 +01:00
lower-module-lds-single-var-ambiguous.ll
[AMDGPULowerLDS] Avoid unnecessary ptrtoint/inttoptr roundtrip (#181671)
2026-02-17 09:28:01 +01:00
lower-module-lds-single-var-unambiguous.ll
[AMDGPULowerLDS] Avoid unnecessary ptrtoint/inttoptr roundtrip (#181671)
2026-02-17 09:28:01 +01:00
lower-module-lds-used-list.ll
…
lower-module-lds-via-hybrid.ll
[AMDGPULowerLDS] Avoid unnecessary ptrtoint/inttoptr roundtrip (#181671)
2026-02-17 09:28:01 +01:00
lower-module-lds-via-table.ll
[AMDGPULowerLDS] Avoid unnecessary ptrtoint/inttoptr roundtrip (#181671)
2026-02-17 09:28:01 +01:00
lower-module-lds-zero-size-arr.ll
[AMDGPULowerLDS] Avoid unnecessary ptrtoint/inttoptr roundtrip (#181671)
2026-02-17 09:28:01 +01:00
lower-module-lds.ll
…
lower-multiple-ctor-dtor.ll
[AMDGPUCtorDtorLowering] Remove unnecessary pointer arithmetic (#182869)
2026-02-23 17:04:49 +01:00
lower-noalias-kernargs.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
lower-range-metadata-intrinsic-call.ll
…
lower-term-opcodes.mir
…
lower-work-group-id-intrinsics-hsa.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
lower-work-group-id-intrinsics-opt.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
lower-work-group-id-intrinsics-pal.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
lower-work-group-id-intrinsics.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
lrint.ll
…
lro-coerce-v4i8-phi-loop.ll
[AMDGPU] LiveRegOptimizer: consider i8/i16 binops on SDWA (#155800)
2025-12-15 12:04:33 -05:00
lro-phi-samebb-nonlookthrough-store.ll
[AMDGPU] LRO: allow same-BB non-lookthrough users for PHI (#160909)
2025-09-30 00:57:07 +09:00
lround.ll
[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#154875)
2025-09-09 10:27:25 -04:00
lshl64-to-32.ll
…
lshl-add-u64.ll
[AMDGPU] Support v_lshl_add_u64 with non-constant shift amount (#179904)
2026-02-06 16:03:58 +01:00
lshr.v2i16.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
lsr-cost-model-vector-iv.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
lto-lower-module-lds.ll
…
machine-cp-propagation.mir
[CodeGen] check artificial subregister before propagate copy (#185751)
2026-03-12 11:16:36 -04:00
machine-cse-commute-target-flags.mir
…
machine-cse-ssa.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
machine-function-info-cwsr.ll
[AMDGPU] AMDGPUPromoteAlloca: increase default max-regs to 32 (#155076)
2025-08-26 09:30:16 +09:00
machine-scheduler-rematerialization-scoring.mir
Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#177206)
2026-02-02 12:34:16 +01:00
machine-scheduler-sink-trivial-remats-attr.mir
Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#177206)
2026-02-02 12:34:16 +01:00
machine-scheduler-sink-trivial-remats-debug.mir
[AMDGPU] Move advanceBeforeNext before advanceToNext (#182808)
2026-02-23 10:00:03 -05:00
machine-scheduler-sink-trivial-remats.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
machine-sink-cycle.mir
…
machine-sink-fence.ll
[CodeGen] Treat hasOrderedMemoryRef as implying arbitrary loads or stores (#182000)
2026-03-04 17:49:11 +00:00
machine-sink-ignorable-exec-use.mir
…
machine-sink-lane-mask.mir
…
machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
…
machine-sink-temporal-divergence-swdev407790.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
machine-sink-temporal-divergence-swdev407790.mir
…
machinelicm-convergent.mir
…
machinelicm-copy-like-instrs.mir
…
machinelicm-undef-use.mir
…
macro-fusion-cluster-vcc-uses.mir
…
mad24-get-global-id.ll
…
mad_64_32.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
mad_int24.ll
[AMDGPU] Regenerate test checks for mad24 tests (#162455)
2025-10-08 13:36:50 +01:00
mad_u64_u32.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
mad_uint24.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
mad-combine.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
mad-mix-bf16.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
mad-mix-hi-bf16.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
mad-mix-hi.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)
2026-02-20 09:44:58 -08:00
mad-mix-lo-bf16.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
mad-mix-lo.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)
2026-02-20 09:44:58 -08:00
mad-mix.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)
2026-02-20 09:44:58 -08:00
mad.u16.ll
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
2025-08-20 10:26:49 -04:00
madak-inline-constant.mir
[AMDGPU] Skip debug uses in SIInstrInfo::foldImmediate (#160102)
2025-09-22 15:22:09 +01:00
madak.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
madmk.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
mai-hazards-gfx90a.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mai-hazards-gfx942.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mai-hazards-mfma-scale.gfx950.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mai-hazards.mir
[TableGen] Complete the support for artificial registers (#183371)
2026-03-04 13:33:26 +00:00
mai-inline.ll
…
make-buffer-rsrc-lds-fails.ll
[AMDGPU] Add the support for 45-bit buffer resource (#159702)
2025-09-24 11:12:02 -04:00
masked-load-vectortypes.ll
[AMDGPU] Simplify legalization of PHI operands (#177352)
2026-01-26 15:39:13 +00:00
match-perm-extract-vector-elt-bug.ll
[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)
2026-01-30 15:13:33 +00:00
materialize-frame-index-sgpr.gfx10.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
materialize-frame-index-sgpr.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
max3.ll
…
max-hard-clause-length.ll
…
max-literals.ll
…
max-sgprs.ll
…
max.i16.ll
…
max.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
maximumnum.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
maximumnum.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
mcexpr-knownbits-assign-crash-gh-issue-110930.ll
…
mcp-aligned-vgprs.mir
…
mcp-implicit-clobber.mir
…
mcp-overlap-after-propagation.mir
…
mcp-use-before-def.mir
…
mdt-preserving-crash.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
med3-knownbits.ll
…
med3-no-simplify.ll
…
mem-builtins.ll
…
memcpy_const_compare.ll
[AMDGPU][NFC] Pre-commit memcpy test with complex constant length (#182170)
2026-02-24 11:02:45 -06:00
memcpy-crash-issue63986.ll
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
2025-12-03 11:13:52 +01:00
memcpy-fixed-align.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memcpy-inline-fails.ll
…
memcpy-libcall.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memcpy-param-combinations.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memcpy-scalar-load.ll
…
memcpy-scoped-aa.ll
…
memintrinsic-unroll.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
memmove-param-combinations.ll
AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)
2025-09-15 05:03:02 -05:00
memmove-scalar-load.ll
…
memmove-var-size.ll
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
2025-12-03 11:13:52 +01:00
memory_clause.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
memory_clause.mir
…
memory-legalizer-atomic-insert-end.mir
…
memory-legalizer-barriers-mmra.ll
[AMDGPU] Insert waitcnt for non-global fence release in GFX12 (#159282)
2025-09-23 11:52:38 +02:00
memory-legalizer-barriers.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-buffer-atomics.ll
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
memory-legalizer-fence-mmra-global.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-fence-mmra-local.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-fence.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-flat-agent.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-flat-cluster.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-flat-lastuse.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-flat-nontemporal.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-flat-singlethread.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-flat-system.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-flat-volatile.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-flat-wavefront.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-flat-workgroup.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-global-agent.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-global-cluster.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-global-lastuse.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-global-nontemporal.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-global-singlethread.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-global-system.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-global-volatile.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-global-wavefront.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-global-workgroup.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-invalid-addrspace.mir
…
memory-legalizer-invalid-syncscope.ll
…
memory-legalizer-lds-dma-volatile-and-nontemporal.ll
[AMDGPU] Return two MMOs for load-to-lds and store-from-lds intrinsics (#175845)
2026-02-04 12:29:49 -08:00
memory-legalizer-local-agent.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-local-cluster.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-local-nontemporal.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-local-singlethread.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-local-system.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-local-volatile.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-local-wavefront.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-local-workgroup.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-local.mir
…
memory-legalizer-multiple-mem-operands-atomics.mir
…
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
memory-legalizer-non-volatile.ll
[AMDGPU][GFX12.5] Add support for emitting memory operations with nv bit set (#179413)
2026-02-06 11:35:46 +01:00
memory-legalizer-private-agent.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-private-cluster.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-private-lastuse.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-private-nontemporal.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-private-singlethread.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-private-system.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-private-volatile.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-private-wavefront.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-private-workgroup.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
memory-legalizer-region.mir
…
memory-legalizer-store-infinite-loop.ll
…
memset-param-combinations.ll
[LowerMemIntrinsics] Optimize memset lowering (#169040)
2026-02-04 13:35:13 +01:00
memset-pattern.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
merge-buffer-gfx12.mir
…
merge-buffer.mir
…
merge-consecutive-wait-alus.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
merge-flat-load-store.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
merge-flat-saddr-load-store.mir
[AMDGPU] Support merging of flat GVS ops (#154200)
2025-08-18 14:31:41 -07:00
merge-flat-with-global-load-store.mir
…
merge-global-load-store.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
merge-image-load-gfx10.mir
…
merge-image-load-gfx11.mir
…
merge-image-load-gfx12.mir
…
merge-image-load.mir
…
merge-image-sample-gfx10.mir
…
merge-image-sample-gfx11.mir
…
merge-image-sample-gfx12.mir
…
merge-image-sample.mir
…
merge-load-store-agpr.mir
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
2025-09-03 00:48:21 +00:00
merge-load-store-physreg.mir
…
merge-load-store-vreg.mir
…
merge-load-store.mir
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
merge-m0.mir
…
merge-out-of-order-ldst.ll
…
merge-out-of-order-ldst.mir
…
merge-s-load.mir
…
merge-sbuffer-load.mir
…
merge-store-crash.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
merge-store-usedef.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
merge-stores.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
merge-tbuffer-gfx9.mir
…
merge-tbuffer-gfx10.mir
…
merge-tbuffer-gfx11.mir
[AMDGPU] Support merging 16-bit and 8-bit TBUFFER load/store instruction (#145078)
2025-08-20 21:16:25 +08:00
merge-tbuffer-gfx12.mir
…
merged-bfx-opt.ll
[DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences (#146054)
2025-07-30 10:27:19 +02:00
mesa3d.ll
…
mesa_regression.ll
…
mfma-bf16-vgpr-cd-select.ll
…
mfma-cd-select.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
mfma-convergent.mir
[AMDGPU] Ensure v_mfma_scale_f32_{16x16x128|32x32x64}_f8f6f4 instructions are convergent (#178627)
2026-01-29 15:46:37 +01:00
mfma-loop.ll
Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#177206)
2026-02-02 12:34:16 +01:00
mfma-no-register-aliasing.ll
[AMDGPU] Add missing -wwm-regalloc=fast to 4 more tests (NFC) (#184966)
2026-03-09 00:09:57 +05:30
mfma-vgpr-cd-select-gfx942.ll
…
mfma-vgpr-cd-select.ll
…
min3.ll
…
min-waves-per-eu-not-respected.ll
…
min.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
minimummaximum.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
minimumnum.bf16.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
minimumnum.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
minmax.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
mir-print-dead-csr-fi.mir
…
misaligned-vgpr-regsequence.mir
[AMDGPU] Emit b32 movs if (a)v_mov_b64_pseudo dest vgprs are misaligned (#160547)
2026-01-30 15:01:14 +00:00
misched-into-wmma-hazard-shadow.mir
[AMDGPU] Allow hazard checks for WMMA co-exec (#168805)
2025-12-01 11:46:30 -08:00
misched-killflags.mir
…
misched-remat-revert.ll
[CodeGen] Treat hasOrderedMemoryRef as implying arbitrary loads or stores (#182000)
2026-03-04 17:49:11 +00:00
missing-store.ll
…
mixed_wave32_wave64.ll
…
mixed-vmem-types.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
mixed-wave32-wave64.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
mmo-target-flags-folding.ll
…
mmra.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
mode-register-fpconstrain.ll
…
mode-register-fptrunc.gfx11plus-fake16.mir
…
mode-register-fptrunc.gfx11plus.mir
…
mode-register-fptrunc.mir
…
mode-register.mir
…
modf-constant-fold.ll
[SelectionDAG] Add expansion for llvm.modf intrinsic (#179434)
2026-02-04 21:25:47 +01:00
module-lds-false-sharing.ll
…
move-addr64-rsrc-dead-subreg-writes.ll
…
move-load-addr-to-valu-flat.mir
…
move-load-addr-to-valu.mir
…
move-to-valu-absdiff.mir
[AMDGPU] Lower S_ABSDIFF_I32 to VALU instructions (#167691)
2025-11-13 14:35:44 +01:00
move-to-valu-addsubu64.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-atomicrmw-system.ll
…
move-to-valu-atomicrmw.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
move-to-valu-ctlz-cttz.ll
…
move-to-valu-lshl_add.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
move-to-valu-lshlrev.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-pseudo-scalar-trans-f16-fake16.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-pseudo-scalar-trans-f16-true16.ll
…
move-to-valu-pseudo-scalar-trans.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-vimage-vsample.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
move-to-valu-worklist.ll
…
movreld-bug.ll
…
movrels-bug.mir
…
mubuf-legalize-operands-non-ptr-intrinsics.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
mubuf-legalize-operands.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
mubuf-legalize-operands.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
mubuf-offset-private.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
mubuf-shader-vgpr-non-ptr-intrinsics.ll
…
mubuf-shader-vgpr.ll
…
mubuf.ll
…
mul24-pass-ordering.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
mul_int24.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
mul_uint24-amdgcn.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
mul_uint24-r600.ll
…
mul.i16.ll
…
mul.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
multi-call-resource-usage-mcexpr.ll
…
multi-divergent-exit-region.ll
…
multi-dword-vgpr-spill.ll
…
multilevel-break.ll
…
naked-fn-with-frame-pointer.ll
AMDGPU: Use ELF mangling in data layout (#163011)
2025-10-13 03:01:45 +00:00
nand.ll
…
narrow_math_for_and.ll
[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)
2026-01-30 15:13:33 +00:00
need-fp-from-vgpr-spills.ll
…
neg_ashr64_reduce.ll
[AMDGPU][SDAG] Only fold flat offsets if they are inbounds PTRADDs (#165427)
2025-11-19 11:48:12 +01:00
neighboring-mfma-padding.mir
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
nested-calls.ll
…
nested-loop-conditions.ll
…
no-bundle-asm.ll
…
no-corresponding-integer-type.ll
…
no-dup-inst-prefetch.ll
…
no-fold-accvgpr-mov.ll
[AMDGPU] Simplify legalization of PHI operands (#177352)
2026-01-26 15:39:13 +00:00
no-fold-accvgpr-mov.mir
…
no-fold-accvgpr-read.mir
…
no-folding-imm-to-inst-with-fi.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
no-hsa-graphics-shaders.ll
…
no-initializer-constant-addrspace.ll
…
no-limit-coalesce.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
no-remat-indirect-mov.mir
…
no-shrink-extloads.ll
…
no-source-locations-in-prologue.ll
…
noclobber-barrier.ll
[CodeGen] Drop uses of BranchInst (#186391)
2026-03-13 21:51:38 +00:00
nofpclass-call.ll
DAG: Fix assert on nofpclass call with aggregate return (#167725)
2025-11-12 18:12:20 +00:00
non-entry-alloca.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
noop-shader-O0.ll
…
nop-data.ll
…
nor-divergent-lanemask.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
nor.ll
…
not-scalarize-volatile-load.ll
…
nsa-reassign.ll
…
nsa-reassign.mir
…
nsa-vmem-hazard.mir
…
nullptr-long-address-spaces.ll
…
nullptr.ll
…
occupancy-levels.ll
[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)
2026-01-26 14:16:36 +01:00
offset-split-flat.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
offset-split-global.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
omod-nsz-flag.mir
[AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (#182107)
2026-03-04 12:16:41 +01:00
omod.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
opencl-image-metadata.ll
…
opencl-printf-and-hostcall.ll
…
opencl-printf-invalid-signature.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
opencl-printf-pipeline.ll
…
opencl-printf-unsupported.ll
…
opencl-printf.ll
AMDGPU: Stop checking for r600 in printf pass (#183536)
2026-02-26 17:18:36 +01:00
operand-folding.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
operand-spacing.ll
…
opt_exec_copy_fold.mir
…
opt-exec-masking-pre-ra-update-liveness-wave32.mir
…
opt-exec-masking-pre-ra-update-liveness.mir
…
opt-sgpr-to-vgpr-copy.mir
…
opt-vgpr-live-range-verifier-error.mir
…
optimize-compare.ll
[AMDGPU][ISel] Reduce 64-bit setcc to upper 32 bits if lower 32 bits are known (#181238)
2026-02-23 11:15:31 -07:00
optimize-compare.mir
[AMDGPU] Remove redundant s_cmp_* after add X, 1 (#176962)
2026-01-23 07:51:36 -06:00
optimize-exec-copies-extra-insts-after-copy.mir
…
optimize-exec-mask-pre-ra-alloc-failure.mir
…
optimize-exec-mask-pre-ra-def-after-use.mir
…
optimize-exec-mask-pre-ra-loop-phi.mir
…
optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
…
optimize-exec-masking-pre-ra.mir
…
optimize-exec-masking-strip-terminator-bits.mir
…
optimize-if-exec-masking.mir
…
optimize-negated-cond-exec-masking-wave32.mir
…
optimize-negated-cond-exec-masking.mir
…
optimize-negated-cond.ll
…
or3.ll
…
or.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
or.r600.ll
[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)
2025-09-11 13:32:44 +01:00
overlapping-tuple-copy-implicit-op-failure.ll
…
pack.v2f16.ll
…
pack.v2i16.ll
…
packed-fp32.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
packed-op-sel.ll
…
packetizer.ll
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
pal-metadata-3.0-callable-dvgpr.ll
…
pal-metadata-3.0-callable.ll
[AMDGPU] Remove subtarget features for dynamic VGPRs (#160822)
2025-10-06 09:50:11 +02:00
pal-metadata-3.0-dvgpr.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
pal-metadata-3.0.gfx950.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
pal-metadata-3.0.gfx1250.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
pal-metadata-3.0.ll
[AMDGPU] Add attribute for FWD_PROGRESS (#181675)
2026-02-26 11:35:36 +00:00
pal-metadata-3.6-dvgpr.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
pal-metadata-3.6.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
pal-simple-indirect-call.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
pal-userdata-regs.ll
…
parallelandifcollapse.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
parallelorifcollapse.ll
…
partial-forwarding-hazards.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
partial-regcopy-and-spill-missed-at-regalloc.ll
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
partial-sgpr-to-vgpr-spills.ll
…
partial-shift-shrink.ll
…
partially-dead-super-register-immediate.ll
…
peephole-fold-imm-multi-use.mir
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
peephole-fold-imm.mir
[AMDGPU] Emit b32 movs if (a)v_mov_b64_pseudo dest vgprs are misaligned (#160547)
2026-01-30 15:01:14 +00:00
peephole-opt-fold-reg-sequence-subreg.mir
…
peephole-opt-regseq-removal.mir
PeepholeOpt: Fix losing subregister indexes on full copies (#161310)
2025-10-02 13:36:47 +09:00
pei-amdgpu-cs-chain-preserve.mir
[AMDGPU] Make chain functions receive a stack pointer (#184616)
2026-03-06 11:01:42 +01:00
pei-amdgpu-cs-chain.mir
[AMDGPU] Make chain functions receive a stack pointer (#184616)
2026-03-06 11:01:42 +01:00
pei-build-av-spill.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
pei-build-spill-offset-overflow-gfx950.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
pei-build-spill-partial-agpr.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
pei-build-spill.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
pei-reg-scavenger-position.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
pei-scavenge-sgpr-carry-out.mir
…
pei-scavenge-sgpr-gfx9.mir
…
pei-scavenge-sgpr.mir
…
pei-scavenge-vgpr-spill.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
pei-vgpr-block-spill-csr.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
perfhint.ll
…
permlane16_opsel.ll
…
permlane16_var-op-sel.ll
[AMDGPU] Encode unused VALU src0/1/2 fields as inline 0 on GFX10+ (#175753)
2026-01-14 18:23:27 +00:00
permlane-op-sel.ll
…
permute_i8.ll
[AMDGPU] Select v_bfe_u32 for i8/i16 (and (srl x, c), mask) (#182446)
2026-03-04 13:31:15 -06:00
permute.ll
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
phi-av-pressure.ll
[AMDGPU] Simplify legalization of PHI operands (#177352)
2026-01-26 15:39:13 +00:00
phi-elim-mli-available.mir
[PHIElimination] Declare MachineLoopInfo dependency for Legacy PM (#169693)
2025-12-06 19:56:01 +05:30
phi-elimination-assertion.mir
…
phi-elimination-end-cf.mir
…
phi-vgpr-input-moveimm.mir
[AMDGPU] Simplify legalization of PHI operands (#177352)
2026-01-26 15:39:13 +00:00
phys-partial-liveness.mir
…
pk_max_f16_literal.ll
…
post-ra-sched-kill-bundle-use-inst.mir
…
post-ra-sched-reset.mir
…
post-ra-soft-clause-dbg-info.ll
…
postra-bundle-memops.mir
[LLVM] Fix typo "LABLE" in test checks (#178451)
2026-01-28 17:31:05 +00:00
postra-bundle-vimage-vsample-gfx12.mir
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
postra-machine-sink-livein-subrange.mir
[MachineSink] Remove subrange of live-ins from super register as well. (#159145)
2025-09-26 14:45:26 +09:00
postra-machine-sink.mir
…
postra-norename.mir
…
postra-sched-attribute.ll
[AMDGPU] Support function attribute to override postRA scheduling direction (#147708)
2025-08-01 16:07:09 +08:00
postra-sink-update-dependency.mir
…
power-sched-no-instr-sunit.mir
…
pr51516.mir
…
pr155452.ll
[DAG] ComputeNumSignBits - ISD::EXTRACT_ELEMENT needs to return at least 1 (#155455)
2025-08-26 14:28:02 -07:00
predicate-dp4.ll
…
predicates.ll
…
preload-implicit-kernargs-debug-info.ll
…
preload-implicit-kernargs-IR-lowering.ll
…
preload-implicit-kernargs.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
preload-kernarg-header.ll
AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
2025-08-26 20:09:32 +09:00
preload-kernargs-IR-lowering.ll
…
preload-kernargs.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
preserve-hi16.ll
[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)
2025-09-24 11:27:26 -04:00
preserve-only-inactive-lane.mir
…
preserve-user-waitcnt.ll
…
preserve-wwm-copy-dst-reg.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
prevent-fmul-hoist-ir.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
print-pipeline-passes.ll
…
printf_builtin.ll
…
printf_nobuiltin.ll
…
printf-defined.ll
…
printf-existing-format-strings.ll
…
private-access-no-objects.ll
…
private-function.ll
[UTC] Update AMDGPU asm regexp for private functions (#166169)
2025-11-04 11:59:43 +00:00
private-memory-atomics.ll
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
2026-01-22 18:34:06 +00:00
private-memory-r600.ll
…
prologue-epilogue-markers.ll
…
promote-alloca-addrspacecast.ll
…
promote-alloca-array-aggregate.ll
…
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
…
promote-alloca-budget-exhausted.ll
…
promote-alloca-calling-conv.ll
…
promote-alloca-cfg.ll
Reland "AMDGPU/PromoteAlloca: Simplify how deferred loads work (#170510)" (#170955)
2025-12-06 01:15:28 +00:00
promote-alloca-globals.ll
…
promote-alloca-invariant-markers.ll
…
promote-alloca-lifetime.ll
…
promote-alloca-loadstores.ll
[AMDGPU][SROA] Unify cast chain implementations (#177945)
2026-02-03 11:12:02 +00:00
promote-alloca-max-regs.ll
[AMDGPU] AMDGPUPromoteAlloca: increase default max-regs to 32 (#155076)
2025-08-26 09:30:16 +09:00
promote-alloca-mem-intrinsics.ll
[AMDGPU] AMDGPUPromoteAlloca: increase default max-regs to 32 (#155076)
2025-08-26 09:30:16 +09:00
promote-alloca-memset.ll
…
promote-alloca-multidim.ll
Reland "AMDGPU/PromoteAlloca: Always use i32 for indexing (#170511)" (#170956)
2025-12-06 08:54:44 -08:00
promote-alloca-negative-index.ll
AMDGPU/PromoteAlloca: Refactor into analysis / commit phases (#170512)
2025-12-12 01:24:38 +00:00
promote-alloca-no-opts.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
promote-alloca-non-byte-sizes.ll
…
promote-alloca-non-constant-index.ll
…
promote-alloca-padding-size-estimate.ll
…
promote-alloca-pointer-array.ll
…
promote-alloca-scoring.ll
AMDGPU/PromoteAlloca: Refactor into analysis / commit phases (#170512)
2025-12-12 01:24:38 +00:00
promote-alloca-shufflevector.ll
…
promote-alloca-stored-pointer-value.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
promote-alloca-strip-abi-opt-attributes.ll
…
promote-alloca-subvecs.ll
…
promote-alloca-to-lds-constantexpr-use.ll
…
promote-alloca-to-lds-icmp.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
promote-alloca-to-lds-phi.ll
…
promote-alloca-to-lds-select.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-use-after-erase.ll
[AMDGPU] Fix a potential use-after-erase in AMDGPUPromoteAlloca pass (#174529)
2026-01-08 11:44:16 -05:00
promote-alloca-user-mult.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
[AMDGPU] In promote-alloca, if index is dynamic, sandwich load with bitcasts to reduce excessive codegen (#171253)
2025-12-19 14:06:52 -05:00
promote-alloca-vector-dynamic-idx-bitcasts.ll
[AMDGPU] In promote-alloca, if index is dynamic, sandwich load with bitcasts to reduce excessive codegen (#171253)
2025-12-19 14:06:52 -05:00
promote-alloca-vector-gep-of-gep.ll
[AMDGPU] Generate canonical additions in AMDGPUPromoteAlloca (#157810)
2025-09-10 14:46:46 +02:00
promote-alloca-vector-gep.ll
[AMDGPU] Support i8/i16 GEP indices when promoting allocas to vectors (#175489)
2026-02-27 18:24:43 +08:00
promote-alloca-vector-to-vector.ll
Reland "AMDGPU/PromoteAlloca: Always use i32 for indexing (#170511)" (#170956)
2025-12-06 08:54:44 -08:00
promote-alloca-vgpr-ratio.ll
…
promote-alloca-volatile.ll
…
promote-constOffset-to-imm-gfx10.mir
…
promote-constOffset-to-imm-gfx12.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
promote-constOffset-to-imm-gfx12.mir
[AMDGPU] Disable negative imm offset for async load/store instructions (#185078)
2026-03-06 21:55:39 +00:00
promote-constOffset-to-imm-gfx90a.mir
…
promote-constOffset-to-imm.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
promote-constOffset-to-imm.mir
…
promote-kernel-arguments.ll
…
promote-vect3-load.ll
…
propagate-amdgpu-cluster-dims.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
propagate-attributes-bitcast-function.ll
…
propagate-flat-work-group-size.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
propagate-waves-per-eu.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
ps-shader-arg-count.ll
[IR][Verifier] Verification for target-features attribute (#173119)
2025-12-22 11:13:56 +01:00
pseudo-scalar-transcendental.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
pseudo-scalar-transcendental.mir
[AMDGPU] Update features for gfx1170 (#186107)
2026-03-20 17:04:17 +01:00
ptr-arg-dbg-value.ll
…
ptr-buffer-alias-scheduling.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
ptradd-sdag-mubuf.ll
[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)
2025-10-02 10:06:25 +02:00
ptradd-sdag-optimizations.ll
[AMDGPU] Global and Buffer loads to LDS should not increase lgkmcnt (#179305)
2026-02-05 09:36:00 -08:00
ptradd-sdag-undef-poison.ll
[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)
2025-10-02 10:06:25 +02:00
ptradd-sdag.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
ptrmask.ll
…
pv-packing.ll
…
pv.ll
…
r600-constant-array-fixup.ll
…
r600-encoding.ll
…
r600-export-fix.ll
…
r600-infinite-loop-bug-while-reorganizing-vector.ll
[SDAG] Remove non-canonical fabs libcall handling (#177967)
2026-01-26 15:11:17 +00:00
r600-legalize-umax-bug.ll
…
r600.add.ll
…
r600.alu-limits.ll
…
r600.amdgpu-alias-analysis.ll
…
r600.bitcast.ll
…
r600.extract-lowbits.ll
…
r600.func-alignment.ll
…
r600.global_atomics.ll
…
r600.llvm.is.fpclass.ll
…
r600.private-memory.ll
…
r600.sub.ll
…
r600.work-item-intrinsics.ll
…
r600cfg.ll
…
ra-inserted-scalar-instructions.mir
…
ran-out-of-registers-error-all-regs-reserved.ll
…
ran-out-of-registers-errors.ll
…
ran-out-of-sgprs-allocation-failure.mir
[AMDGPU] Mark VOPC_e64 instructions rematerializable (#186195)
2026-03-13 21:16:18 +00:00
rcp_iflag.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
rcp-pattern.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
read_register.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
read-register-invalid-register.ll
…
read-register-invalid-subtarget.ll
…
read-register-invalid-type-i32.ll
…
read-register-invalid-type-i64.ll
…
read-write-register-illegal-type.ll
DAG: Emit an error if trying to legalize read/write register with illegal types (#145197)
2025-07-26 10:54:59 +09:00
readcyclecounter.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_READCYCLECOUNTER (#165754)
2025-10-31 09:12:56 -07:00
readlane_exec0.mir
…
README
…
readsteadycounter.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_READSTEADYCOUNTER (#163661)
2025-10-16 09:45:33 -07:00
reassoc-mul-add-1-to-mad.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
reassoc-scalar.ll
…
recursion.ll
…
recursive_global_initializer.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
recursive-resource-usage-mcexpr.ll
…
reduce-build-vec-ext-to-ext-build-vec.ll
…
reduce-load-width-alignment.ll
…
reduce-saveexec.mir
…
reduce-store-width-alignment.ll
…
reduction.ll
…
reg-coalescer-sched-crash.ll
…
reg-coalescer-subreg-liveness.mir
[AMDGPU] Add suffix _d4 to tensor load/store with 4 groups D#, NFC (#184176)
2026-03-03 14:10:38 -08:00
reg-sequence-like-v-pk-mov-b32.mir
…
regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
…
regalloc-failure-overlapping-insert-assert.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
regalloc-fast-dont-drop-subreg-index-issue61134.mir
…
regalloc-illegal-eviction-assert.ll
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
regalloc-introduces-copy-sgpr-to-agpr.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
regalloc-sgpr128-partial-def.mir
[AMDGPU] Shrink S_MOV_B64 to S_MOV_B32 during rematerialization (#184333)
2026-03-20 15:09:13 +01:00
regalloc-spill-wmma-scale.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
regalloc-undef-copy-fold.mir
…
regcoal-subrange-join-seg.mir
…
regcoal-subrange-join.mir
…
regcoalesce-64-bit-only-regs.mir
[AMDGPU] Drop high 32 bits of aperture registers (#158725)
2025-09-16 02:11:39 -07:00
regcoalesce-cannot-join-failures.mir
…
regcoalesce-dbg.mir
…
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
…
regcoalesce-prune.mir
…
regcoalescer-resolve-lane-conflict-by-subranges.mir
…
regcoalescing-remove-partial-redundancy-assert.mir
…
register-coalescer--set-undef-full-reg-use-implicit-def-erase-issue109249.mir
…
register-count-comments.ll
…
register-killed-error-after-alloc-failure0.mir
[regalloc][basic] Fix non-deterministic codegen in basic register allocator (#177998)
2026-01-27 08:37:47 -08:00
register-killed-error-after-alloc-failure1.ll
…
regpressure_printer.mir
[AMDGPU] Use correct SlotIndex to calculate live-out register set. (#161720)
2025-10-10 14:03:27 +02:00
reject-agpr-usage-before-gfx908.ll
…
rel32.ll
…
release-vgprs-dbg-loc.mir
…
release-vgprs-gfx12-dvgpr.mir
…
release-vgprs-gfx12.mir
…
release-vgprs-spill.ll
[AMDGPU] Fix DEALLOC_VGPRS in the presence of spills to scratch (#178461)
2026-01-29 20:57:16 +01:00
release-vgprs.mir
[AMDGPU] Fix buggy insertion of DEALLOC_VGPRS message (#178401)
2026-01-28 13:29:26 +00:00
rem_i128.ll
[CodeGen] Expand power-of-2 div/rem at IR level in ExpandIRInsts. (#180654)
2026-02-25 22:54:34 +01:00
remaining-virtual-register-operands.ll
…
remaining-virtual-register-operands.mir
…
remat-dead-subreg.mir
…
remat-fp64-constants.ll
AMDGPU/GlobalISel: Regbanklegalize rules for G_PHI (#179735)
2026-03-06 14:01:50 +01:00
remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
…
remat-smrd.mir
…
remat-sop.mir
[SlotIndexes] Further pack indices to improve spill placement time (#182640)
2026-02-27 10:55:20 -08:00
remat-vop.mir
AMDGPU: Fix not diagnosing unaligned VGPRs for vsrc operands (#155104)
2025-08-25 17:42:58 +09:00
remove-incompatible-extended-image-insts.ll
…
remove-incompatible-functions.ll
…
remove-incompatible-gws.ll
…
remove-incompatible-s-time.ll
…
remove-incompatible-wave32-feature.ll
…
remove-incompatible-wave64-feature.ll
[AMDGPU] Remove wave64 functions (#153690)
2025-08-14 15:54:33 -07:00
remove-no-kernel-id-attribute.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
remove-not-short-exec-branch-on-unconditional-jump.mir
…
remove-register-flags.mir
[AMDGPU] Allow any SGPRs for chain callees (#168345)
2025-12-02 09:44:35 +01:00
remove-short-exec-branches-gpr-idx-mode.mir
…
remove-short-exec-branches-special-instructions.mir
…
rename-disconnected-bug.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
rename-independent-subregs-mac-operands.mir
…
rename-independent-subregs.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
reorder-stores.ll
…
repeated-divisor.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
replace-store-of-insert-load.ll
…
reqd-work-group-size.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
required-export-priority.ll
[AMDGPU] Update features for gfx1170 (#186107)
2026-03-20 17:04:17 +01:00
required-export-priority.mir
[AMDGPU] Update features for gfx1170 (#186107)
2026-03-20 17:04:17 +01:00
reserved-reg-in-clause.mir
…
resource-optimization-remarks.ll
…
resource-usage-crash-unhandled-reg.mir
…
resource-usage-dead-function.ll
[AMDGPU] Move LowerBufferFatPointers after LoadStoreVectorizer and remove the fixme (#161531)
2025-10-01 17:52:15 -07:00
resource-usage-pal.ll
…
ret_jump.ll
…
ret.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
return-with-successors.mir
…
returnaddress.ll
…
rewrite-out-arguments-address-space.ll
…
rewrite-out-arguments.ll
…
rewrite-partial-reg-uses-dbg.mir
…
rewrite-partial-reg-uses-gen.mir
…
rewrite-partial-reg-uses.mir
…
rewrite-undef-for-phi.ll
…
rewrite-vgpr-mfma-scale-to-agpr.mir
[AMDGPU] Fix AGPR_32 reg assign for mfma scale ops (#168964)
2025-12-02 13:41:16 -05:00
rewrite-vgpr-mfma-to-agpr-copy-from.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
rewrite-vgpr-mfma-to-agpr-phi.ll
[AMDGPU] Use larger immediate values in S_NOP (#158990)
2025-09-16 15:51:06 +01:00
rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
rewrite-vgpr-mfma-to-agpr.gfx90a.ll
AMDGPU: Add tests for every mfma intrinsic v-to-a mapping (#153026)
2025-09-04 11:24:54 +09:00
rewrite-vgpr-mfma-to-agpr.gfx950.ll
AMDGPU: Add tests for every mfma intrinsic v-to-a mapping (#153026)
2025-09-04 11:24:54 +09:00
rewrite-vgpr-mfma-to-agpr.ll
[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
2026-02-25 15:24:54 -08:00
rotate-add.ll
…
rotl.i64.ll
…
rotl.ll
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
rotr.i64.ll
…
rotr.ll
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
roundeven.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
rsq.f32-safe.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
rsq.f32.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
rsq.f64.ll
AMDGPU: Introduce f64 rsq pattern in AMDGPUCodeGenPrepare (#172053)
2025-12-22 15:49:59 +01:00
rv7x0_count3.ll
…
s_add_co_pseudo_lowering.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
s_addk_i32.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
s_cmp_0.ll
[AMDGPU] Remove redundant s_cmp_* after add X, 1 (#176962)
2026-01-23 07:51:36 -06:00
s_code_end.ll
[AMDGPU] Set preferred function alignment based on icache geometry (#183064)
2026-03-11 07:57:37 -04:00
s_movk_i32.ll
…
s_mulk_i32.ll
…
s_or_b32_transformation.ll
[AMDGPU] Optimize S_OR_B32 to S_ADDK_I32 where possible (#177949)
2026-02-07 09:10:12 +00:00
s_or_saveexec_xor_combine.mir
…
s_uaddo_usubo_pseudo.ll
[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)
2025-10-22 08:42:29 -05:00
s-barrier-lowering.ll
[AMDGPU] Add amdgpu-lower-exec-sync pass to lower named-barrier globals (#165692)
2025-11-17 10:08:40 +05:30
s-barrier.ll
[AMDGPU] Schedule independent instructions between s_barrier_signal and s_barrier_wait (#172057)
2025-12-16 11:48:50 +05:30
s-cluster-barrier.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
s-getpc-b64-remat.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
s-wakeup-barrier.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
sad.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
saddo.ll
[AMDGPU][ISel] setcc peephole for comparisons with upper 32 bits of a 64-bit register pair (#177662)
2026-02-11 13:41:03 -07:00
saddsat.ll
[AMDGPU][ISel] setcc peephole for comparisons with upper 32 bits of a 64-bit register pair (#177662)
2026-02-11 13:41:03 -07:00
salu-to-valu.ll
…
same-lds-variable-multiple-use-in-one-phi-node.ll
[ReplaceConstant] Don't create instructions for the same constant multiple times in the same basic block (#169141)
2025-11-26 22:44:40 -05:00
same-slot-agpr-sgpr.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
sampler-resource-id.ll
…
save-fp.ll
…
scalar_to_vector_v2x16.ll
…
scalar_to_vector.gfx11plus.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
scalar_to_vector.ll
[AMDGPU] Fix scalar_to_vector v4f16 pattern (#186188)
2026-03-12 19:07:53 +01:00
scalar_to_vector.v8i16.ll
[AMDGPU] Allocate AVRegClass last (#146606)
2025-07-25 13:46:41 -07:00
scalar-branch-missing-and-exec.ll
…
scalar-float-sop1.ll
[AMDGPU] Improve codegen for uniform f16<-->i32 conversions (#176833)
2026-01-21 13:07:14 -06:00
scalar-float-sop2.ll
…
scalar-float-sopc.ll
…
scalar-store-cache-flush.mir
…
scalarize-insert-subvector.ll
…
scale-offset-flat.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
scale-offset-global.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
scale-offset-scratch.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
scale-offset-smem.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
scc-clobbered-sgpr-to-vmem-spill.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
sched_mfma_rewrite_copies.mir
Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#177206)
2026-02-02 12:34:16 +01:00
sched_mfma_rewrite_cost.mir
Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#177206)
2026-02-02 12:34:16 +01:00
sched_mfma_rewrite_diff_types.mir
[AMDGPU] Fix handling of setting register classes in MFMA scheduler rewrite stage (#181047)
2026-02-19 21:01:03 +01:00
sched-assert-dead-def-subreg-use-other-subreg.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
sched-assert-onlydbg-value-empty-region.mir
…
sched-barrier-hang-weak-dep.mir
…
sched-barrier-post-RA.mir
…
sched-barrier-pre-RA.mir
…
sched-crash-dbg-value.mir
…
sched-group-barrier-pipeline-solver.mir
…
sched-group-barrier-pre-RA.mir
…
sched-handleMoveUp-subreg-def-across-subreg-def.mir
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
sched-image-sample-post-RA.mir
…
sched-no-schedmodel.mir
…
sched-prefer-non-mfma.mir
…
sched-setprio.ll
…
sched.barrier.inverted.mask.ll
…
sched.group.classification.mir
[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)
2026-02-11 05:26:58 +00:00
schedule-addrspaces.ll
…
schedule-amdgpu-tracker-physreg-crash.ll
…
schedule-amdgpu-tracker-physreg.ll
…
schedule-amdgpu-trackers.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
schedule-avoid-spills.ll
…
schedule-barrier-fpmode.mir
…
schedule-barrier-latency-gfx9.mir
[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
2026-02-25 15:24:54 -08:00
schedule-barrier-latency.mir
[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutation (#168500)
2025-11-19 17:49:14 +09:00
schedule-barrier.mir
…
schedule-fs-loop-nested-if.ll
…
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
[SDAG] Remove non-canonical fabs libcall handling (#177967)
2026-01-26 15:11:17 +00:00
schedule-if.ll
…
schedule-ilp-liveness-tracking.mir
…
schedule-ilp.ll
…
schedule-ilp.mir
…
schedule-kernel-arg-loads.ll
…
schedule-pending-queue.mir
[AMDGPU] Examine instructions in pending queues during scheduling (#147653)
2025-10-16 08:46:29 -07:00
schedule-physregdeps.mir
…
schedule-regpressure-ilp-metric-spills.mir
…
schedule-regpressure-lds.ll
…
schedule-regpressure-limit2.ll
…
schedule-regpressure-limit3.ll
…
schedule-regpressure-limit-clustering.ll
…
schedule-regpressure-limit.ll
…
schedule-regpressure-misched-max-waves.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
schedule-regpressure-no-unclustered-regions.mir
[AMDGPU] Avoid changing minOccupancy if unclustered schedule was not run for any region. (#162025)
2025-11-12 10:11:22 -08:00
schedule-regpressure.mir
…
schedule-relaxed-occupancy.ll
…
schedule-vs-if-nested-loop-failure.ll
…
schedule-vs-if-nested-loop.ll
…
schedule-xdl-resource.ll
…
scheduler-handle-move-bundle.mir
…
scheduler-rp-calc-one-successor-two-predecessors-bug.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
scheduler-subrange-crash.ll
…
scratch-buffer.ll
…
scratch-pointer-sink.ll
AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (#153176)
2025-09-11 11:26:20 +02:00
scratch-simple.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
sdag-print-divergence.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
sdiv64.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
sdiv.ll
[AMDGPU] 32-bit ABS is a legal DAG node (#163907)
2025-10-17 16:11:59 -05:00
sdivrem24.ll
…
sdivrem64.r600.ll
…
sdwa-commute.ll
…
sdwa-cse.mir
…
sdwa-gfx9.mir
…
sdwa-op64-test.ll
…
sdwa-ops.mir
…
sdwa-peephole-cndmask-fail.ll
…
sdwa-peephole-cndmask-sext.ll
…
sdwa-peephole-cndmask-wave32.mir
…
sdwa-peephole-cndmask-wave64.mir
…
sdwa-peephole-instr-combine-sel-dst.mir
…
sdwa-peephole-instr-combine-sel-src.mir
…
sdwa-peephole-instr-combine-sel.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
sdwa-peephole-instr-combine-sel.mir
…
sdwa-peephole-instr-gfx10.mir
…
sdwa-peephole-instr.mir
…
sdwa-peephole.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
sdwa-preserve.mir
…
sdwa-scalar-ops.mir
…
sdwa-stack.mir
…
sdwa-vop2-64bit.mir
…
select64.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
select-cmp-shared-constant-fp.ll
…
select-cmp-shared-constant-int.ll
…
select-constant-cttz.ll
Revert "[AMDGPU] Replace AMDGPUISD::FFBH_I32 with ISD::CTLS" (#178837)
2026-01-29 21:19:15 -08:00
select-constant-xor.ll
…
select-fabs-fneg-extract-legacy.ll
…
select-fabs-fneg-extract.f16.ll
[AMDGPU] Remove NoSignedZerosFPMath uses (#178343)
2026-01-30 09:18:40 +08:00
select-fabs-fneg-extract.legal.f16.ll
…
select-fabs-fneg-extract.ll
[AMDGPU] Remove NoSignedZerosFPMath uses (#178343)
2026-01-30 09:18:40 +08:00
select-fabs-fneg-extract.v2f16.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
select-flags-to-fmin-fmax.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
select-i1.ll
…
select-load-to-load-select-ptr-combine.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
select-nsz-known-values-to-fmin-fmax.ll
AMDGPU: Add more tests for fp min/max combines (#184336)
2026-03-12 13:11:31 +01:00
select-opt.ll
…
select-phi-s16-fp.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
select-undef.ll
…
select-vectors.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
select.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
select.ll
…
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
…
selectcc.ll
…
sema-v-unsched-bundle.ll
[AMDGPU][Scheduler] Simplify scheduling revert logic (#177203)
2026-02-01 17:55:12 +01:00
sendmsg-m0-hazard.mir
…
set_kill_i1_for_floation_point_comparison.ll
…
set-dx10.ll
…
set-gpr-idx-peephole.mir
[AMDGPU] Skip debug instructions when eliminating S_SET_GPR_IDX_ON/OFF (#160715)
2025-11-04 12:03:16 +00:00
set-inactive-wwm-overwrite.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
set-wave-priority.ll
…
setcc64.ll
…
setcc-equivalent.ll
…
setcc-fneg-constant.ll
…
setcc-limit-load-shrink.ll
…
setcc-multiple-use.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
setcc-opt.ll
…
setcc-select-hi32mask.ll
[AMDGPU][ISel] Reduce 64-bit setcc to upper 32 bits if lower 32 bits are known (#181238)
2026-02-23 11:15:31 -07:00
setcc-select.ll
[AMDGPU][ISel] setcc peephole for comparisons with upper 32 bits of a 64-bit register pair (#177662)
2026-02-11 13:41:03 -07:00
setcc-sext.ll
…
setcc.ll
…
seto.ll
…
setuo.ll
…
sext-divergence-driven-isel.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
sext-eliminate.ll
…
sext-in-reg-failure-r600.ll
…
sext-in-reg-vector-shuffle.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
sext-in-reg.ll
…
sgpr-control-flow.ll
…
sgpr-copy-duplicate-operand.ll
…
sgpr-copy-local-cse.ll
…
sgpr-copy.ll
[InstSimplify] Simplify fcmp implied by dominating fcmp (#161090)
2025-10-05 16:15:51 +08:00
sgpr-count-graphics.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
sgpr-phys-copy.mir
[AMDGPU] Enable saving SHARED_BASE to VCC (#163244)
2025-10-13 15:38:28 -05:00
sgpr-regalloc-flags.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
sgpr-spill-dead-frame-in-dbg-value.mir
…
sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
…
sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
…
sgpr-spill-incorrect-fi-bookkeeping-bug.ll
…
sgpr-spill-no-vgprs.ll
…
sgpr-spill-overlap-wwm-reserve.mir
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
sgpr-spill-partially-undef.mir
…
sgpr-spill-to-vmem-scc-clobber-unhandled.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
sgpr-spill-to-vmem-scc-clobber.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
sgpr-spill-update-only-slot-indexes.ll
[AMDGPU] Add missing -wwm-regalloc=fast to 4 more tests (NFC) (#184966)
2026-03-09 00:09:57 +05:30
sgpr-spill-vmem-large-frame.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
sgpr-spill-wrong-stack-id.mir
…
sgpr-spill.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
sgpr-spills-empty-prolog-block.mir
…
sgpr-spills-split-regalloc.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
sgpr-to-vreg1-copy.ll
[AMDGPU][ISel] Reduce 64-bit setcc to upper 32 bits if lower 32 bits are known (#181238)
2026-02-23 11:15:31 -07:00
sgpr-to-vreg1-copy.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
sgprcopies.ll
…
shader-addr64-nonuniform.ll
…
shared-op-cycle.ll
…
shift-and-i64-ubfe.ll
[AMDGPU] Ensure divergence for v_alignbit (#129159)
2025-09-26 10:55:56 -07:00
shift-and-i128-ubfe.ll
…
shift-i64-opts.ll
…
shift-i128.ll
…
shift-select.ll
…
shl64_reduce_flags.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
shl64_reduce.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
shl_add_constant.ll
…
shl_add_ptr_csub.ll
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
2025-12-05 12:37:33 +00:00
shl_add_ptr_global.ll
AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)
2025-08-22 05:29:36 +00:00
shl_add_ptr.ll
…
shl_add.ll
…
shl_or.ll
…
shl-add-to-add-shl.ll
…
shl.ll
[AMDGPU] Make rotr illegal (#166558)
2025-12-05 12:39:50 +00:00
shl.v2i16.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
shlN_add.ll
[AMDGPU] Generate s_lshl?_add_u32 (#167032)
2025-11-11 08:47:53 -06:00
should-not-hoist-set-inactive.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
shrink-add-sub-constant.ll
[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)
2025-09-17 10:09:06 -04:00
shrink-carry.mir
…
shrink-fma-f64.mir
…
shrink-i32-kimm.mir
…
shrink-instructions-flags.mir
…
shrink-instructions-illegal-fold.mir
…
shrink-instructions-implicit-vcclo.mir
…
shrink-insts-scalar-bit-ops.mir
[AMDGPU] When shrinking and/or to bitset*, remove implicit scc def (#168128)
2025-11-15 09:21:43 -06:00
shrink-mad-fma-fake16.mir
…
shrink-mad-fma-gfx10.mir
…
shrink-mad-fma.mir
…
shrink-true16.mir
…
shrink-v-cmp-wave32-dead-vcc-lo.mir
…
shrink-vop3-carry-out.mir
…
shufflevector-physreg-copy.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
shufflevector.v2bf16.v2bf16.ll
…
shufflevector.v2bf16.v3bf16.ll
…
shufflevector.v2bf16.v4bf16.ll
…
shufflevector.v2bf16.v8bf16.ll
…
shufflevector.v2f16.v2f16.ll
…
shufflevector.v2f16.v3f16.ll
…
shufflevector.v2f16.v4f16.ll
…
shufflevector.v2f16.v8f16.ll
…
shufflevector.v2f32.v2f32.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2f32.v3f32.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2f32.v4f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2f32.v8f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i16.v2i16.ll
…
shufflevector.v2i16.v3i16.ll
…
shufflevector.v2i16.v4i16.ll
…
shufflevector.v2i16.v8i16.ll
…
shufflevector.v2i32.v2i32.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2i32.v3i32.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2i32.v4i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i32.v8i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i64.v2i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i64.v3i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i64.v4i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2i64.v8i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2p0.v2p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2p0.v3p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2p0.v4p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2p3.v2p3.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2p3.v3p3.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v2p3.v4p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v2p3.v8p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3bf16.v2bf16.ll
…
shufflevector.v3bf16.v3bf16.ll
…
shufflevector.v3bf16.v4bf16.ll
…
shufflevector.v3f16.v2f16.ll
…
shufflevector.v3f16.v3f16.ll
…
shufflevector.v3f16.v4f16.ll
…
shufflevector.v3f32.v2f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3f32.v3f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3f32.v4f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i16.v2i16.ll
…
shufflevector.v3i16.v3i16.ll
…
shufflevector.v3i16.v4i16.ll
…
shufflevector.v3i32.v2i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i32.v3i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i32.v4i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i64.v2i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i64.v3i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3i64.v4i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p0.v2p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p0.v3p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p0.v4p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p3.v2p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p3.v3p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v3p3.v4p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4bf16.v2bf16.ll
…
shufflevector.v4bf16.v3bf16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4bf16.v4bf16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4f16.v2f16.ll
…
shufflevector.v4f16.v3f16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4f16.v4f16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4f32.v2f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4f32.v3f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4f32.v4f32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i16.v2i16.ll
…
shufflevector.v4i16.v3i16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4i16.v4i16.ll
AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)
2025-11-11 13:50:57 -08:00
shufflevector.v4i32.v2i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i32.v3i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i32.v4i32.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i64.v2i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i64.v3i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4i64.v4i64.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p0.v2p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p0.v3p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p0.v4p0.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p3.v2p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p3.v3p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
shufflevector.v4p3.v4p3.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
si-annotate-cf-kill.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
si-annotate-cf-noloop.ll
…
si-annotate-cf-unreachable.ll
…
si-annotate-cf.ll
…
si-annotate-cfg-loop-assert.ll
…
si-annotate-dbg-info.ll
…
si-annotate-nested-control-flows.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
si-annotatecfg-multiple-backedges.ll
…
si-fix-sgpr-copies-av-constrain.mir
AMDGPU: Constrain readfirstlane operand when writing to m0 (#168004)
2025-11-14 17:18:43 +00:00
si-fix-sgpr-copies-copy-to-sgpr.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
si-fix-sgpr-copies.mir
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
si-fold-aligned-agprs.mir
AMDGPU: Stop special casing aligned VGPR targets in operand folding (#155559)
2025-09-02 16:15:25 +00:00
si-fold-aligned-vgprs.mir
AMDGPU: Stop special casing aligned VGPR targets in operand folding (#155559)
2025-09-02 16:15:25 +00:00
si-fold-copy-kills.mir
…
si-fold-kimm.mir
…
si-fold-operands-agpr-copy-reg-sequence.mir
AMDGPU: Avoid using exact class check in reg_sequence AGPR fold (#156135)
2025-09-03 09:05:48 +09:00
si-fold-operands-commute-same-operands-assert.mir
…
si-fold-operands-requires-ssa.mir
…
si-fold-operands-subreg-imm.gfx942.mir
…
si-fold-operands-subreg-imm.mir
…
si-fold-reg-sequence.mir
[AMDGPU] Fold into uses of splat REG_SEQUENCEs through COPYs. (#145691)
2025-08-04 16:18:33 +01:00
si-fold-scalar-clamp.mir
…
si-i1-copies.mir
…
si-init-whole-wave.mir
…
si-instr-info-correct-implicit-operands.ll
…
si-instr-info-vopc-exec.mir
…
si-late-branch-lowering-preserve-loop-info.mir
[AMDGPU] Teach SILateBranchLowering pass to preserve MachineLoopInfo (#178276)
2026-01-29 22:23:00 +05:30
si-lower-control-flow-kill.ll
…
si-lower-control-flow-preserve-dom-tree.mir
[AMDGPU] Fix DomTree preservation in SILowerControlFlow when nodes are removed (#176691)
2026-01-25 09:45:44 +05:30
si-lower-control-flow-unreachable-block.ll
…
si-lower-control-flow.mir
…
si-lower-i1-copies-order-of-phi-incomings.mir
…
si-lower-i1-copies.mir
[NFC][AMDGPU] New test for untested case in SILowerI1Copies (#186127)
2026-03-19 16:33:15 +01:00
si-lower-sgpr-spills-vgpr-lanes-usage.mir
[StackSlotColoring] Check for zero stack slot size in RemoveDeadStores (#182673)
2026-03-11 20:57:49 +08:00
si-lower-sgpr-spills.mir
…
si-lower-wwm-copies.mir
…
si-opt-vgpr-liverange-bug-deadlanes.mir
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
si-optimize-vgpr-live-range-dbg-instr.ll
…
si-optimize-vgpr-live-range-dbg-instr.mir
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
si-pre-allocate-wwm-regs.mir
[AMDGPU] Add target features to guard DPP controls (#182391)
2026-02-20 07:59:10 -07:00
si-pre-allocate-wwwmregs-dbg-noreg.mir
[AMDGPU] Fixed llvm-debuginfo-analyzer for AMDGPU. (#145125)
2025-08-12 22:04:52 +00:00
si-pre-emit-peephole-preserve-loop-info.mir
[AMDGPU] Teach SIPreEmitPeephole pass to preserve MachineLoopInfo (#178868)
2026-02-17 20:57:47 +05:30
si-scheduler-exports.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
si-scheduler.ll
…
si-sgpr-spill.ll
…
si-spill-cf.ll
…
si-split-load-store-alias-info.ll
[AMDGPU] Propagate AA info in vector load/store splitting. (#168871)
2025-11-24 03:30:35 +00:00
si-triv-disjoint-mem-access.ll
…
si-unify-exit-multiple-unreachables.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
si-unify-exit-return-unreachable.ll
…
si-vector-hang.ll
…
sibling-call.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
sign_extend.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
siloadstoreopt-misaligned-regsequence.ll
Reapply "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325) (#184114)
2026-03-02 14:47:35 +00:00
simple-indirect-call-2.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
simple-indirect-call.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
simplify-libcall-nobuiltin-def.ll
…
simplify-libcalls2.ll
[AMDGPU] Fix duplicate RUN lines in tests (#182286)
2026-02-19 16:07:20 +00:00
simplify-libcalls.ll
AMDGPU: Stop adding uniform-work-group-size=false (#183502)
2026-02-26 14:53:20 +00:00
simplifydemandedbits-recursion.ll
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
2025-11-19 17:39:10 -08:00
simulated-trap-pseudo-expand.ll
[AMDGPU] Fix insertSimulatedTrap to return correct continuation block (#174774)
2026-01-21 11:52:38 +05:30
sink-addr-memory-intrinsics.ll
[CodeGenPrepare] Consider target memory intrinics as memory use (#159638)
2025-09-19 14:18:21 -07:00
sink-after-control-flow-postra.mir
…
sink-after-control-flow.mir
…
sink-image-sample.ll
…
sint_to_fp.f64.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
sint_to_fp.i64.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
sint_to_fp.ll
…
sitofp.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
skip-branch-taildup-ret.mir
…
skip-branch-trap.ll
…
skip-fold-regsequence.mir
…
skip-if-dead.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
skip-promote-alloca-vector-users.ll
…
smed3.ll
…
smem-no-clause-coalesced.mir
…
smem-war-hazard.mir
…
smfmac_alloc_failure_no_agpr_O0.ll
AMDGPU: Track minNumAGPRs in MFI instead of mayUseAGPRs (#161996)
2025-10-07 08:48:45 +09:00
smfmac_no_agprs.ll
AMDGPU: Really use AV classes by default for vector classes (#166483)
2025-11-13 18:54:02 +00:00
sminmax.ll
…
sminmax.v2i16.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
smrd_vmem_war.ll
…
smrd-fold-offset.mir
…
smrd-gfx10.ll
…
smrd-vccz-bug.ll
…
smrd.ll
…
snippet-copy-bundle-regression.mir
…
soft-clause-dbg-value.mir
…
soft-clause-exceeds-register-budget.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
sopk-compares.ll
…
sopk-no-literal.ll
…
speculative-execution-freecasts.ll
…
spill192.mir
…
spill224.mir
…
spill288.mir
…
spill320.mir
…
spill352.mir
…
spill384.mir
…
spill_kill_v16.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
spill_more_than_wavesize_csr_sgprs.ll
…
spill-agpr-partially-undef.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
spill-agpr.ll
AMDGPU: Select VGPR MFMAs by default (#159493)
2026-01-22 13:41:25 +00:00
spill-agpr.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
spill-alloc-sgpr-init-bug.ll
…
spill-before-exec.mir
Revert "[RegAlloc] Relax the split constrain on MBB prolog" (#169990)
2025-11-29 08:01:23 -05:00
spill-cfg-position.ll
…
spill-csr-frame-ptr-reg-copy.ll
…
spill-empty-live-interval.mir
…
spill-m0.ll
…
spill-offset-calculation.ll
…
spill-partial-csr-sgpr-live-ins.mir
…
spill-reg-tuple-super-reg-use.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
spill-regpressure-less.mir
…
spill-restore-partial-copy.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
spill-scavenge-offset.ll
Revert "[RegAlloc] Relax the split constrain on MBB prolog" (#169990)
2025-11-29 08:01:23 -05:00
spill-sgpr-csr-live-ins.mir
…
spill-sgpr-stack-no-sgpr.ll
…
spill-sgpr-to-virtual-vgpr.mir
…
spill-sgpr-used-for-exec-copy.mir
…
spill-special-sgpr.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
spill-to-agpr-partial.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
spill-vector-superclass.ll
[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
2026-03-13 21:38:10 +00:00
spill-vgpr-block.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
spill-vgpr-to-agpr-update-regscavenger.ll
[AMDGPU] Stop optimising readfirstlane in pass AMDGPUUniformIntrinsicCombine (#166955)
2025-11-08 01:17:39 +05:30
spill-vgpr-to-agpr.ll
…
spill-vgpr.ll
…
spill-wait.mir
…
spill-wide-sgpr.ll
…
spill-writelane-vgprs.ll
…
spillv16.ll
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
spillv16.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
split-arg-dbg-value.ll
…
split-liverange-overlapping-copies.mir
…
split-mbb-lis-subrange.mir
…
split-scalar-i64-add.ll
…
split-smrd.ll
…
split-vector-memoperand-offsets.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
splitkit-copy-bundle.mir
…
splitkit-copy-live-lanes.mir
…
splitkit-do-not-undo-subclass-split-with-remat.mir
…
splitkit-getsubrangeformask.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
splitkit-nolivesubranges.mir
…
splitkit.mir
…
sra.ll
[DAG] Always use stack to promote bitcast when the source is vector (#151065)
2025-08-02 15:32:10 -07:00
sram-ecc-default.ll
[AMDGPU] gfx1250 sram-ecc feature codegen tests. NFC. (#155293)
2025-08-25 14:32:29 -07:00
sramecc-subtarget-feature-any.ll
[AMDGPU] gfx1250 sram-ecc feature codegen tests. NFC. (#155293)
2025-08-25 14:32:29 -07:00
sramecc-subtarget-feature-disabled.ll
…
sramecc-subtarget-feature-enabled.ll
[AMDGPU] gfx1250 sram-ecc feature codegen tests. NFC. (#155293)
2025-08-25 14:32:29 -07:00
sreg-xnull-regclass-bitwidth.mir
…
srem64.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
srem-seteq-illegal-types.ll
…
srem.ll
[AMDGPU][ISel] Reduce 64-bit setcc to upper 32 bits if lower 32 bits are known (#181238)
2026-02-23 11:15:31 -07:00
srl64_reduce_flags.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
srl64_reduce.ll
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
srl.ll
AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)
2025-09-06 08:22:09 +09:00
sroa-before-unroll.ll
…
SRSRC-GIT-clobber-check.mir
…
ssubo.ll
[AMDGPU] Regenerate add/sub overflow tests
2025-07-28 12:51:21 +01:00
ssubsat.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
stack-passed-subdword-arg-crash-issue157997.ll
AMDGPU: Fix returning wrong type for stack passed sub-dword arguments (#158002)
2025-09-12 10:50:03 +09:00
stack-pointer-offset-relative-frameindex.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
stack-realign-kernel.ll
…
stack-realign.ll
Reland: CodeGen: Record MMOs in finalizeBundle (#166689)
2025-11-06 07:34:36 -08:00
stack-size-overflow.ll
…
stack-slot-color-sgpr-vgpr-spills.mir
…
stackguard.ll
CodeGen: Fix crash when no libcall is available for stackguard (#164211)
2025-10-23 10:40:40 +09:00
stacksave_stackrestore.invalid.ll
…
stacksave_stackrestore.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
stale-livevar-in-twoaddr-pass.mir
…
statepoint-asm-printer.mir
AMDGPU: Avoid crashing on statepoint-like pseudoinstructions (#170657)
2025-12-29 19:08:08 +01:00
statepoint-insert-waitcnts.mir
AMDGPU: Avoid crashing on statepoint-like pseudoinstructions (#170657)
2025-12-29 19:08:08 +01:00
stop-tail-duplicate-cfg-intrinsic.mir
…
store_typed.ll
…
store-barrier.ll
…
store-clobbers-load.ll
[AMDGPU][LIT][NFC] Adding -mtriple for AMDGPUAnnotateUniformValues Pass tests (#156437)
2025-09-03 15:32:28 +05:30
store-global.ll
…
store-hi16.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
store-local.96.ll
…
store-local.128.ll
…
store-local.ll
…
store-private.ll
…
store-to-constant.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
store-v3i64.ll
…
store-vector-ptrs.ll
…
store-weird-sizes.ll
[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)
2025-10-02 10:06:25 +02:00
stress-calls.ll
…
strict_fadd.f16.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fadd.f32.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fadd.f64.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fma.f16.ll
…
strict_fma.f32.ll
…
strict_fma.f64.ll
…
strict_fmul.f16.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fmul.f32.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fmul.f64.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
2025-12-02 06:55:25 -08:00
strict_fpext.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
strict_fptrunc.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
strict_fsub.f16.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_FSUB (#173929)
2025-12-30 09:20:51 -08:00
strict_fsub.f32.ll
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_FSUB (#173929)
2025-12-30 09:20:51 -08:00
strict_fsub.f64.ll
[AMDGPU] Update strict floating point tests to be more comprehensive (#169578)
2025-11-25 21:15:42 -08:00
strict_ldexp.f16.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_STRICT_FLDEXP (#177525)
2026-01-23 10:49:14 -08:00
strict_ldexp.f32.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_STRICT_FLDEXP (#177525)
2026-01-23 10:49:14 -08:00
strict_ldexp.f64.ll
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_STRICT_FLDEXP (#177525)
2026-01-23 10:49:14 -08:00
strictfp_f16_abi_promote.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
structurize1.ll
…
structurize-hoist.ll
[StructurizeCFG] nested-if zerocost hoist bugfix (#155408)
2025-08-28 09:04:14 -05:00
structurize.ll
…
sub64-low-32-bits-known-zero.ll
…
sub_i1.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
sub_u64.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
sub-zext-cc-zext-cc.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
sub.i16.ll
…
sub.ll
Reapply "[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments." (#174977)
2026-01-20 16:39:08 +00:00
sub.v2i16.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
subreg_interference.mir
…
subreg-coalescer-crash.ll
[AMDGPU] Add missing comma between export target and first export data (#181641)
2026-02-17 09:24:34 +01:00
subreg-coalescer-undef-use.ll
…
subreg-eliminate-dead.ll
…
subreg-intervals.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
subreg-split-live-in-error.mir
[RegAlloc] Account for use availability when applying rematerializable weight discount (#159180)
2025-09-26 07:57:12 +08:00
subreg-undef-def-with-other-subreg-defs.mir
[MIR] Support symbolic INLINEASM extra-info flags (#186818)
2026-03-17 11:08:28 +00:00
subvector-test.mir
…
swdev282079.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
swdev282079.mir
…
swdev373493.ll
…
swdev380865.ll
[DAGCombiner] Relax nsz constraint for FP optimizations (#165011)
2025-12-09 12:07:46 +02:00
swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
[RegAlloc] Account for use availability when applying rematerializable weight discount (#159180)
2025-09-26 07:57:12 +08:00
swdev503538-move-to-valu-stack-srd-physreg.ll
[NFC] Reduce fragility of swdev503538-... test. (#176302)
2026-01-30 18:46:05 +01:00
swdev504645-global-fold.ll
…
swdev-549940.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
switch-default-block-unreachable.ll
…
switch-unreachable.ll
…
swizzle-export.ll
…
swizzle.bit.extract.ll
…
syncscopes.ll
…
tail-call-amdgpu-gfx.ll
…
tail-call-cgp.ll
…
tail-call-inreg-arguments.convergencetokens.ll
[AMDGPU] Fix caller/callee mismatch in SGPR assignment for inreg args (#182754)
2026-02-23 18:13:41 +00:00
tail-call-inreg-arguments.error.ll
[AMDGPU] Fix caller/callee mismatch in SGPR assignment for inreg args (#182754)
2026-02-23 18:13:41 +00:00
tail-call-inreg-arguments.ll
[AMDGPU] Fix caller/callee mismatch in SGPR assignment for inreg args (#182754)
2026-02-23 18:13:41 +00:00
tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
tail-call-uniform-target-in-vgprs-issue110930.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
tail-dup-bundle.mir
…
tail-duplication-convergent.ll
…
target-cpu.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
target-mem-intrinsic-metadata.ll
…
tex-clause-antidep.ll
…
texture-input-merge.ll
…
tgsplit.ll
…
threeaddr-wmma.mir
…
tid-kd-xnack-any.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
tid-kd-xnack-off.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
tid-kd-xnack-on.ll
[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)
2025-09-16 15:37:01 -04:00
tid-mul-func-xnack-all-any.ll
…
tid-mul-func-xnack-all-not-supported.ll
…
tid-mul-func-xnack-all-off.ll
…
tid-mul-func-xnack-all-on.ll
…
tid-mul-func-xnack-any-off-1.ll
…
tid-mul-func-xnack-any-off-2.ll
…
tid-mul-func-xnack-any-on-1.ll
…
tid-mul-func-xnack-any-on-2.ll
…
tid-mul-func-xnack-invalid-any-off-on.ll
…
tid-one-func-xnack-any.ll
…
tid-one-func-xnack-not-supported.ll
…
tid-one-func-xnack-off.ll
…
tid-one-func-xnack-on.ll
…
tied-op-for-wwm-scratch-reg-spill-restore.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
token-factor-inline-limit-test.ll
…
track-spilled-vgpr-liveness.mir
…
trans-coexecution-hazard.mir
…
trans-forwarding-hazards.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
transform-block-with-return-to-epilog.ll
[SelectionDAGBuilder] Remove NoNaNsFPMath uses (#169904)
2026-02-09 09:48:07 +08:00
trap-abis.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
trap.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
triton_regression_no_waterfall.ll
…
triton_regression_no_waterfall.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
triv-disjoint-mem-access-neg-offset.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
true16-fold.mir
AMDGPU: Delete redundant recursive copy handling code (#157032)
2025-11-05 18:01:12 -08:00
true16-imm-folded-to-0-regression.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
true16-ra-pre-gfx11-regression-test.mir
…
true16-saveexec.mir
…
trunc-bitcast-vector.ll
…
trunc-cmp-constant.ll
…
trunc-combine.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
trunc-store-f64-to-f16.ll
AMDGPU: Fix truncstore from v6f32 to v6f16 (#171212)
2025-12-08 22:46:36 +00:00
trunc-store-i1.ll
…
trunc-store-i64.ll
…
trunc-store-vec-i16-to-i8.ll
…
trunc-store.ll
AMDGPU: Perform zero/any extend combine into permute (#177370)
2026-01-28 10:47:22 -06:00
trunc-vector-store-assertion-failure.ll
…
trunc.ll
…
truncate-lshr-cast-build-vector-combine.ll
…
tti-unroll-prefs.ll
…
tuple-allocation-failure.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
twoaddr-bundle.mir
CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (#166213)
2025-11-12 22:04:46 +00:00
twoaddr-constrain.ll
AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
2025-08-12 15:03:31 +02:00
twoaddr-fma-f64.mir
…
twoaddr-fma.mir
…
twoaddr-mad.mir
…
twoaddr-regsequence-keep-copy-on-use.mir
[CodeGen][AMDGPU] TwoAddress: Only skip undef COPY at REG_SEQUENCE lowering when there is Live info or no uses for subreg (#175598)
2026-02-13 08:46:30 -08:00
twoaddr-regsequence.mir
…
twoaddr-wmma.mir
AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)
2025-11-20 16:25:47 -08:00
uaddo.ll
[AMDGPU] Delete redundant s_or_b32 (#165261)
2025-11-07 09:27:20 -06:00
uaddsat.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
udiv64.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
udiv.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
udivrem24.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
udivrem64.r600.ll
…
udivrem.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
uint_to_fp.f64.ll
Revert "[LSV] Merge contiguous chains across scalar types" (#170381)
2025-12-02 18:27:58 -05:00
uint_to_fp.i64.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
uint_to_fp.ll
…
uitofp.f16.ll
[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)
2026-02-04 10:54:11 -05:00
umed3.ll
…
umin-sub-to-usubo-select-combine.ll
AMDGPU: Add baseline test for #161651 (#165921)
2025-10-31 21:50:17 +00:00
unaligned-buffer.ll
[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)
2026-01-29 10:39:35 -08:00
unaligned-load-store.ll
…
unallocatable-bundle-regression.mir
…
undef-build-vector.ll
…
undef-copy-propagation.mir
…
undef-handling-crash-in-ra.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
undef-subreg-use-after-coalesce.mir
…
undefined-physreg-sgpr-spill.mir
…
undefined-subreg-liverange.ll
…
unexpected-reg-unit-state.mir
…
unfold-masked-merge-scalar-variablemask.ll
…
unhandled-loop-condition-assertion.ll
…
uniform_branch_with_floating_point_cond.ll
…
uniform-alignbit.ll
[AMDGPU] Ensure divergence for v_alignbit (#129159)
2025-09-26 10:55:56 -07:00
uniform-branch-intrinsic-cond.ll
…
uniform-cfg.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
uniform-crash.ll
…
uniform-load-from-tid.ll
[AMDGPU] Mark workitem IDs uniform in more cases (#152581)
2025-08-29 01:21:04 -05:00
uniform-loop-inside-nonuniform.ll
…
uniform-phi-with-undef.ll
…
uniform-select.ll
[AMDGPU] Use reverse iteration in CodeGenPrepare (#145484)
2025-10-10 13:00:40 +02:00
uniform-vgpr-to-sgpr-return.ll
…
uniform-work-group-attribute-missing.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
uniform-work-group-multistep.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
uniform-work-group-nested-function-calls.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
uniform-work-group-prevent-attribute-propagation.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
uniform-work-group-propagate-attribute.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
uniform-work-group-recursion-test.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
uniform-work-group-test.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
unigine-liveness-crash.ll
…
unknown-processor.ll
…
unnamed-function-resource-info.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
unpack-half.ll
…
unpack-non-coissue-insts-post-ra-scheduler.mir
[AMDGPU]: Packed instructions unpacking to co-issue post-RA scheduling - fix flag handling (#160195)
2025-10-10 08:56:38 -07:00
unroll.ll
…
unspill-vgpr-after-rewrite-vgpr-mfma.ll
Greedy: Take copy hints involving subregisters (#159570)
2025-09-19 09:37:36 +09:00
unstructured-cfg-def-use-issue.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
unsupported-atomics.ll
…
unsupported-calling-conv-call.ll
…
unsupported-calling-conv-func.ll
…
unsupported-calls.ll
…
unsupported-cc.ll
…
unsupported-code-object-version.ll
…
unsupported-cs-chain.ll
…
unsupported-image-a16.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
unsupported-image-g16.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
unsupported-image-sample.ll
…
update-lds-alignment.ll
…
update-phi.ll
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
2025-11-03 20:59:48 +01:00
urem64.ll
[AMDGPU] Delete redundant s_or_b32 (#165261)
2025-11-07 09:27:20 -06:00
urem-seteq-illegal-types.ll
…
urem.ll
…
use_restore_frame_reg.mir
…
use-after-free-after-cleanup-failed-vreg.ll
RenameIndependentSubregs: try to only implicit def used subregs (#167486)
2025-11-20 09:28:34 +09:00
use-sgpr-multiple-times.ll
…
usubo.ll
[AMDGPU] Delete redundant s_or_b32 (#165261)
2025-11-07 09:27:20 -06:00
usubsat.ll
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
2026-01-22 17:24:29 +01:00
v1i64-kernel-arg.ll
…
v1024.ll
…
v_add_u64_pseudo_sdwa.ll
[AMDGPU] Skip debug uses in SIPeepholeSDWA (#160092)
2025-09-22 14:40:00 +01:00
v_ashr_pk.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
v_cmp_gfx11.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
v_cndmask.ll
[AMDGPU][ISel] setcc peephole for comparisons with upper 32 bits of a 64-bit register pair (#177662)
2026-02-11 13:41:03 -07:00
v_cvt_pk_u8_f32.ll
…
v_mac_f16.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
v_mac.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
v_madak_f16.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
v_mov_b64_expand_and_shrink.mir
…
v_mov_b64_expansion.mir
[AMDGPU] Emit b32 movs if (a)v_mov_b64_pseudo dest vgprs are misaligned (#160547)
2026-01-30 15:01:14 +00:00
v_pack.ll
[AMDGPU][True16] remove pack32 pattern from true16 mode (#171756)
2025-12-11 09:49:27 -05:00
v_sat_pk_u8_i16.ll
[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)
2025-10-17 14:29:37 -04:00
v_sub_u64_pseudo_sdwa.ll
…
v_swap_b16.ll
Revert "[AMDGPU] Generate more swaps" (#187723)
2026-03-20 12:03:20 -05:00
v_swap_b32.mir
Revert "[AMDGPU] Generate more swaps" (#187723)
2026-03-20 12:03:20 -05:00
valu-i1.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
valu-mask-write-hazard-true16.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
valu-mask-write-hazard.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
valu-read-sgpr-hazard-attrs.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
valu-read-sgpr-hazard.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
vccz-corrupt-bug-workaround.mir
…
vcmp-saveexec-to-vcmpx-set-kill.mir
…
vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
…
vcmp-saveexec-to-vcmpx.ll
…
vcmp-saveexec-to-vcmpx.mir
…
vcmpx-exec-war-hazard.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
vcmpx-permlane16var-hazard.mir
…
vcmpx-permlane-hazard-sdwa.mir
…
vcmpx-permlane-hazard.mir
…
vcmpx-permlane-vgpr-msb-gfx1250.mir
[AMDGPU] Fix GFX1250 hazard: S_SET_VGPR_MSB dropped (#184904)
2026-03-10 09:35:45 -04:00
vector_range_metadata.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
vector_rebroadcast.ll
[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)
2025-10-17 14:29:37 -04:00
vector_shuffle.packed.ll
[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)
2025-10-17 14:29:37 -04:00
vector-alloca-addrspacecast.ll
[InstCombine] Canonicalize GEP source element types (#180745)
2026-03-06 14:48:01 +00:00
vector-alloca-atomic.ll
AMDGPU: Generalize and normalize some tests to avoid future churn (#170508)
2025-12-03 17:11:05 +00:00
vector-alloca-bitcast.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
vector-alloca-limits.ll
…
vector-alloca.ll
[AMDGPU] Remove FeaturePromoteAlloca (#177636)
2026-02-23 15:24:57 -05:00
vector-extract-insert.ll
…
vector-legalizer-divergence.ll
AMDGPU: Stop implementing shouldCoalesce (#168988)
2025-11-21 10:10:35 -05:00
vector-reduce-add.ll
[AMDGPU] [GlobalIsel] Enabling lit tests for new regbank select (#180680)
2026-02-11 07:52:47 +05:30
vector-reduce-and.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
vector-reduce-fadd.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
vector-reduce-fmax.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
vector-reduce-fmaximum.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
vector-reduce-fmin.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
vector-reduce-fminimum.ll
[AMDGPU] Codegen for min/max instructions for gfx1170 (#185625)
2026-03-12 12:32:56 +01:00
vector-reduce-fmul.ll
AMDGPU: Move softPromoteHalfType override to R600 only (#177419)
2026-01-26 15:23:04 +00:00
vector-reduce-mul.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
vector-reduce-or.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
vector-reduce-smax.ll
[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
2026-02-25 15:24:54 -08:00
vector-reduce-smin.ll
[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
2026-02-25 15:24:54 -08:00
vector-reduce-umax.ll
[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
2026-02-25 15:24:54 -08:00
vector-reduce-umin.ll
[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
2026-02-25 15:24:54 -08:00
vector-reduce-xor.ll
[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)
2026-03-12 17:12:45 -04:00
vector-spill-restore-to-other-vector-type.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
vectorize-buffer-fat-pointer.ll
…
vectorize-global-local.ll
…
vectorize-loads.ll
…
vectorize-unroll-metadata.ll
…
verifier-sdwa-cvt.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-constant-bus-violations.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-ds-gws-align.mir
AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)
2025-11-25 18:55:34 +00:00
verify-duplicate-literal.mir
…
verify-gfx12-gds.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-gfx90a-aligned-vgprs.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-image-vaddr-align.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-image.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-scalar-store.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-sop.mir
…
verify-vimage-vsample.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-vopd-gfx12.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
verify-vopd.mir
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
vertex-fetch-encoding.ll
…
vgpr_constant64_to_sgpr.mir
…
vgpr_constant_to_sgpr.ll
…
vgpr-agpr-limit-gfx90a.ll
[AMDGPU] Add missing -wwm-regalloc=fast to 4 more tests (NFC) (#184966)
2026-03-09 00:09:57 +05:30
vgpr-blocks-funcinfo.mir
…
vgpr-count-compute.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-count-graphics-chain.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-count-graphics.ll
[AMDGPU] Ignore inactive VGPRs in .vgpr_count (#149052)
2025-08-13 10:47:00 +02:00
vgpr-descriptor-waterfall-loop-idom-update.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
vgpr-large-tuple-alloc-error.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
vgpr-limit-gfx1250.ll
[AMDGPU] Add missing -wwm-regalloc=fast to 4 more tests (NFC) (#184966)
2026-03-09 00:09:57 +05:30
vgpr-liverange-ir.ll
AMDGPU: Select vector reg class for divergent build_vector (#168169)
2025-11-14 21:53:39 -08:00
vgpr-liverange.ll
…
vgpr-lowering-gfx1250-t16.mir
[AMDGPU] Fix wrong MSB encoding for V_FMAMK instructions (#168107)
2025-11-14 22:50:17 +00:00
vgpr-lowering-gfx1250.mir
[AMDGPU] Fix piggybacking after commute in AMDGPULowerVGPREncoding (#183778)
2026-02-27 22:16:14 -08:00
vgpr-mark-last-scratch-load.ll
[AMDGPU] New test for untested line in AMDGPUMarkLastScratchLoad (#185430)
2026-03-10 20:04:02 +01:00
vgpr-mark-last-scratch-load.mir
…
vgpr-remat-v_pk_mov_b32.mir
…
vgpr-remat.mir
AMDGPU: Add pseudoinstruction for 64-bit agpr or vgpr constants (#154499)
2025-08-20 22:54:37 +09:00
vgpr-set-msb-coissue.mir
[AMDGPU] Handle S_WAIT_XCNT in SIInstrInfo::isWaitcnt (#187726)
2026-03-23 10:19:43 +00:00
vgpr-setreg-mode-swar.mir
[AMDGPU] Fix decoding of SETREG MSBs (#187578)
2026-03-19 14:08:03 -07:00
vgpr-spill-dead-frame-in-dbg-value.mir
…
vgpr-spill-emergency-stack-slot-compute.ll
…
vgpr-spill-emergency-stack-slot.ll
Revert "[LICM] Sink unused l-invariant loads in preheader. #157559"
2025-11-14 14:51:33 +01:00
vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
…
vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
…
vgpr-spill-placement-issue61083.ll
[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)
2025-08-27 13:18:18 +01:00
vgpr-spill-scc-clobber.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
vgpr-spill.mir
[AMDGPU] Remove alignment constraint from spill pseudos (#177317)
2026-03-09 09:33:23 +05:30
vgpr-tuple-allocation.ll
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
2025-11-25 11:55:26 +00:00
vi-removed-intrinsics.ll
…
virtregrewrite-undef-identity-copy.mir
…
visit-physreg-vgpr-imm-folding-bug.ll
…
vmem-to-salu-hazard.mir
[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)
2026-01-31 10:46:59 -08:00
vmem-vcc-hazard.mir
…
vni8-across-blocks.ll
AMDGPU: Perform zero/any extend combine into permute (#177370)
2026-01-28 10:47:22 -06:00
vni8-live-reg-opt.ll
…
vop-shrink-frame-index.mir
…
vop-shrink-non-ssa.mir
…
vop-shrink.ll
…
vopc_dpp-true16.mir
…
vopc_dpp.ll
…
vopc_dpp.mir
…
vopc-remat.mir
[AMDGPU] Mark VOPC_e64 instructions rematerializable (#186195)
2026-03-13 21:16:18 +00:00
vopd-combine-gfx1250.mir
[AMDGPU] Fix VOPD checks for commuting OpX and OpY (#178772)
2026-01-30 15:13:33 +00:00
vopd-combine.mir
[AMDGPU] Allow bank conflicts on src0 for V_DUAL_MOV_B32 for gfx1170 (#186100)
2026-03-12 13:49:52 +01:00
vopd-src2acc-delay.mir
…
vselect64.ll
…
vselect.ll
…
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait-before-stores-with-scope_sys.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
wait-before-stores-with-scope_sys.mir
[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#168852)
2025-11-25 10:11:04 +01:00
wait-xcnt-atomic-rmw-optimization.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
wait-xcnt.mir
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
wait.ll
…
waitcnt-agpr.mir
…
waitcnt-back-edge-loop.mir
…
waitcnt-bvh.mir
…
waitcnt-debug-non-first-terminators.mir
…
waitcnt-debug-output-crash.ll
[AMDGPU] Use a general form of intrinsic for tensor load/store (#182334)
2026-02-20 17:28:32 -08:00
waitcnt-debug.mir
[AMDGPU] Readd assertions requirement to test after #170468
2025-12-04 02:24:52 +00:00
waitcnt-flat.ll
…
waitcnt-func-global-inv.mir
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
2025-12-17 17:53:00 +05:30
waitcnt-gfx1250.mir
[AMDGPU] High VGPR waitcnt generation tests. NFC. (#157533)
2025-09-08 16:13:27 -07:00
waitcnt-global-inv-wb.mir
…
waitcnt-kmcnt-scc-different-block.mir
[AMDGPU][SIInsertWaitcnts] Track SCC. Insert KM_CNT waits for SCC writes. (#157843)
2025-09-18 14:41:01 +02:00
waitcnt-loop-ds-prefetch-flushed.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
waitcnt-loop-ds-prefetch-flushed.mir
[AMDGPU] Extend DS loop wait optimization with flush point tracking (#175658)
2026-03-02 09:19:46 -08:00
waitcnt-loop-ds-prefetch-pattern.ll
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
2026-03-23 12:18:11 +01:00
waitcnt-loop-ds-store-barrier.mir
[AMDGPU] BackOffBarrier feature added to gfx1250; Removed incorrect "DS Store drain" check. (#179818)
2026-02-19 08:41:44 -08:00
waitcnt-loop-irreducible.mir
…
waitcnt-loop-opt.mir
[AMDGPU] Add DS loop waitcnt optimization for GFX12+ (#172728)
2026-01-12 13:34:02 -08:00
waitcnt-loop-single-basic-block.mir
…
waitcnt-looptest.ll
llvm: Convert some assorted lit tests to opaque pointers (#174564)
2026-01-06 11:41:27 +00:00
waitcnt-meta-instructions.mir
…
waitcnt-multiple-funcs.mir
…
waitcnt-no-redundant.mir
…
waitcnt-overflow.mir
…
waitcnt-permute.mir
…
waitcnt-preexisting-vscnt.mir
[AMDGPU] Reenable BackOffBarrier on GFX11/12 (#155370)
2025-09-02 09:37:43 +02:00
waitcnt-preexisting.mir
…
waitcnt-sample-out-order.mir
…
waitcnt-sample-waw.mir
…
waitcnt-skip-meta.mir
…
waitcnt-trailing.mir
…
waitcnt-unscoped.ll
[AMDGPU] Return two MMOs for load-to-lds and store-from-lds intrinsics (#175845)
2026-02-04 12:29:49 -08:00
waitcnt-vinterp.mir
…
waitcnt-vmcnt-loop.mir
[AMDGPU] Skip debug uses in SIInsertWaitcnts::shouldFlushVmCnt (#160818)
2025-09-26 08:39:11 +01:00
waitcnt-vmem-waw.mir
…
waitcnt-vscnt.ll
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)
2025-12-08 16:07:27 -06:00
waitcnt-vscnt.mir
…
waitcnt-wbl2.ll
[AMDGPU] Fix missing waitcnt after buffer_wbl2 (#178316)
2026-02-05 10:13:51 -06:00
waitcnt-wcg-attributes.mir
[AMDGPU][SIInsertWaitcnts] Add test functions in waitcnt-wcg-attributes.mir (#186504)
2026-03-20 12:34:11 -07:00
waitcnt.mir
…
waterfall_kills_scc.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
waterfall-call-target-av-register-failure.ll
AMDGPU: Fix verifier error when waterfall call target is in AV register (#168017)
2025-11-14 09:49:40 -08:00
wave32.ll
[AMDGPU][ISel] Reduce 64-bit setcc to upper 32 bits if lower 32 bits are known (#181238)
2026-02-23 11:15:31 -07:00
wave_dispatch_regs.ll
[AMDGPU] AsmPrinter: Unify arg handling (#151672)
2025-08-08 12:00:37 +02:00
while-break.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
whole-wave-functions-pei.mir
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
2026-02-06 11:14:14 +00:00
whole-wave-functions.ll
Revert "[AMDGPU] Generate more swaps" (#187723)
2026-03-20 12:03:20 -05:00
whole-wave-register-copy.ll
…
whole-wave-register-spill.ll
[AMDGPU] Remove odd syntax in some RUN lines. NFC. (#169831)
2025-11-27 17:00:54 +00:00
widen_extending_scalar_loads.ll
…
widen-smrd-loads.ll
AMDGPU: Perform zero/any extend combine into permute (#177370)
2026-01-28 10:47:22 -06:00
widen-vselect-and-mask.ll
[AMDGPU][ISel] setcc peephole for comparisons with upper 32 bits of a 64-bit register pair (#177662)
2026-02-11 13:41:03 -07:00
wmma_modifiers.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
wmma_multiple_32.ll
…
wmma_multiple_64.ll
…
wmma-coexecution-valu-hazards.mir
[AMDGPU] Include TRANS instructions in WMMA coexecution hazard checking (#186269)
2026-03-16 16:10:58 -07:00
wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-gfx12-w32-imm.ll
[AMDGPU] Allow bank conflicts on src0 for V_DUAL_MOV_B32 for gfx1170 (#186100)
2026-03-12 13:49:52 +01:00
wmma-gfx12-w32-iu-modifiers.ll
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-gfx12-w32-swmmac-index_key.ll
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-gfx12-w32.ll
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-gfx12-w64-imm.ll
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-gfx12-w64-iu-modifiers.ll
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-gfx12-w64-swmmac-index_key.ll
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-gfx12-w64.ll
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-hazards-gfx12-w32.mir
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-hazards-gfx12-w64.mir
[AMDGPU] Add WMMA and SWMMAC instructions for gfx1170 (#180731)
2026-02-18 19:17:48 +01:00
wmma-hazards-gfx1250-w32.mir
Reapply "[AMDGPU] Rework the clamp support for WMMA instructions" (#174674) (#174697)
2026-01-07 06:12:19 +00:00
wmma-hazards.mir
…
wmma-nop-hoisting.mir
[AMDGPU] Hoist WMMA coexecution hazard V_NOPs from loops to preheaders (#176895)
2026-02-26 17:19:00 +05:30
workgroup-id-in-arch-sgprs.ll
[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)
2026-03-18 20:00:08 +00:00
workitem-intrinsic-opts.ll
[AMDGPU] Invert scc uses to delete s_cmp_eq* (#167382)
2026-01-14 10:24:24 -06:00
wqm-debug-instr.mir
[AMDGPU] Fix crash in SIWholeQuadMode with debug instructions. (#178282)
2026-01-30 02:11:07 +01:00
wqm-gfx11.ll
…
wqm-terminators.mir
…
wqm.ll
[NFC][AMDGPU] Use zeroinitializer instead of null for ptr addrspace(2/3/5) in AMDGPU tests (#181710)
2026-02-17 18:46:18 -05:00
wqm.mir
[AMDGPU] Generate some WQM/WWM tests (NFC) (#152635)
2025-08-08 14:10:13 +09:00
write_register.ll
AMDGPU/GlobalISel: RegBankLegalize rules for s_barrier/wave_barrier (#186512)
2026-03-16 08:55:07 -07:00
write-register-invalid-register.ll
…
write-register-vgpr-into-sgpr.ll
…
wrong-transalu-pos-fix.ll
…
wwm-reg-shift-down-gfx11plus.mir
…
wwm-regalloc-error.ll
AMDGPU: Avoid contraction in wwm allocation failure message (#150888)
2025-07-28 17:11:28 +09:00
wwm-reserved-spill.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
wwm-reserved.ll
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
2025-11-21 17:52:08 +00:00
wwm-spill-superclass-pseudo.mir
…
xfail.r600.bitcast.ll
…
xnack-subtarget-feature-any.ll
…
xnack-subtarget-feature-disabled.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
xnack-subtarget-feature-enabled.ll
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
2025-09-03 16:39:29 +01:00
xnor.ll
…
xor3-i1-const.ll
[InstCombine] Optimize redundant floating point comparisons in or/and inst's (#158097)
2025-09-16 20:52:11 +05:30
xor3.ll
…
xor_add.ll
…
xor-r600.ll
…
xor.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
zero_extend.ll
…
zext-divergence-driven-isel.ll
RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)
2025-11-10 09:37:14 -08:00
zext-i64-bit-operand.ll
…
zext-lid.ll
…

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.